Class / Patent application number | Description | Number of patent applications / Date published |
345532000 | Plural memory controllers | 8 |
20080198170 | SYSTEM AND METHOD FOR DMA CONTROLLED IMAGE PROCESSING - A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data. | 08-21-2008 |
20110032261 | METHOD OF IMPLEMENTING AN ACCELERATED GRAPHICS PORT FOR A MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM - An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions. | 02-10-2011 |
20110074799 | SCAN-TYPE DISPLAY DEVICE CONTROL CIRCUIT - A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data. | 03-31-2011 |
20120075318 | DISPLAY DEVICE AND METHOD FOR TRANSFERRING IMAGE DATA - For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU | 03-29-2012 |
20120162237 | Bundle-Based CPU/GPU Memory Controller Coordination Mechanism - A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests. | 06-28-2012 |
20130265318 | VOLUME RENDERING ON SHARED MEMORY SYSTEMS WITH MULTIPLE PROCESSORS BY OPTIMIZING CACHE REUSE - A method, system and product are disclosed for volume rendering of medical images on a shared memory system implemented on a multi-socket mainboard with multiple multi-core processors and multiple last level caches, cores that share a cache being united in a socket. The method includes decomposing the image space to be used for rendering in regions, each region including a plurality of tiles; assigning two sockets to each of the decomposed regions; determining a tile enumeration scheme for a region; rendering all tiles within a region according to a determined tile enumeration scheme on the assigned two sockets until the respective region is finished; if a region is finished, assigning the two sockets to another region; and if no region is left, splitting an existing region of un-rendered tiles into sub-regions according to a splitting scheme and applying the steps recursively for the sub-regions. | 10-10-2013 |
20140085320 | EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE - A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests. | 03-27-2014 |
20140118372 | DISPLAY APPARATUS, DRIVING CHIP SET, AND OPERATING METHOD THEREOF - A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal. | 05-01-2014 |