Entries |
Document | Title | Date |
20080204464 | Image display system and method for preventing image tearing effect - An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation. If the writing and reading addresses are the same or if a difference between the start addresses for the writing and reading operations is less than the burst length, the tearing-protection bus arbiter outputs the reading address to the memory controller and holds the writing address. | 08-28-2008 |
20080252648 | Method And Apparatus For Providing Bandwidth Priority - A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included. | 10-16-2008 |
20080259088 | Display device - Disclosed herein is a display device in which input data is written to a RAM as current frame data and read from the RAM as preceding frame data. Then, the current frame data and the preceding frame data are added up in a correction circuit and the result is subjected to an overdriving processing. After this, the processed (over-driven) data is assumed as current frame corrected data, which is then written to the RAM. The written corrected data is read from the RAM and subjected to a double-speed driving processing. | 10-23-2008 |
20080291209 | Encoding Multi-media Signals - An aspect of the present invention mitigates bottlenecks in components such as buses in the path of a system memory and a GPU memory. In an embodiment, a graphics processing unit (GPU) receives digital values representing a multi-media signal from an external source, encodes the digital values, and stores the encoded values in a RAM. The RAM may also store instructions which are executed by a CPU. As the digital values are received by the GPU without being stored in the RAM, bottlenecks may be mitigated. | 11-27-2008 |
20080303836 | VIDEO DISPLAY DRIVER WITH PARTIAL MEMORY CONTROL - Partial memory control for a video display driver in which data storage is provided for storing and providing a plurality of video pixel data having selectable ones of a plurality of pixel color depths to be displayed by a plurality of video displays having a plurality of mutually distinct dimensions. | 12-11-2008 |
20090002383 | MEMORY FOR PROVIDING A GRAPHIC CONTENT - A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content. | 01-01-2009 |
20090027408 | DISPLAY APPARATUS, CONTROL METHOD THEREOF AND DISPLAY SYSTEM HAVING THE SAME - A display apparatus, a control method thereof and a display system having the same are provided. The display apparatus includes: a communication unit; a memory in which the same data as that of an external display apparatus is loaded in the same reference address as that of the external display apparatus; and a controller which controls to change data loaded in a reference address corresponding to address information from the external display apparatus based on data change information from the external display apparatus and to display the changed data if the address information and the data change information are received from the external display apparatus via the communication unit. | 01-29-2009 |
20090066707 | SOURCE DRIVER FOR IMAGE SCROLLING - A source driver comprising a frame memory, a first line buffer, and a second line buffer. The frame memory stores bits of pixel values of an image. The first line buffer then sequentially latches the bits of the pixel values from the frame memory with a first address index. The second line buffer then sequentially latch the bits of the pixel values from the first line buffer with a second address index, which is different from the first address index, and writes the bits of the pixel values back to the frame memory, such that the image is scrolled. The present invention also provides a method of refreshing the frame memory in a source driver. | 03-12-2009 |
20090066708 | Hands-free, user-formatted instruction display system - An instruction display system includes memory for storing instruction information in a format specified by the user, a display, and a hands-free user-controlled processor. Hands-free user inputs define selected portions of the stored instruction information that are to be displayed. The memory, display and processor are coupled to the user by a mounting assembly that allows the user to readily view the display for a particular activity. | 03-12-2009 |
20090079748 | Apparatus, System, and Method For Graphics Memory Hub - A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub. | 03-26-2009 |
20090091580 | Integrated circuit device and electronic instrument - An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel. | 04-09-2009 |
20090096799 | DISPLAY APPARATUS - A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit. | 04-16-2009 |
20090096800 | DISPLAY APPARATUS - A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit. | 04-16-2009 |
20090115789 | METHODS, SYSTEMS AND APPARATUS FOR MAXIMUM FRAME SIZE - Apparatus, methods, and systems are disclosed for capturing video frames. The system determines a maximum memory size available for video capture. The system initiates video capture and acquires a frame. The system then analyzes the incoming frame and determines if the frame is larger than the maximum memory size. If the frame is larger than the maximum memory size and if a quality parameter is greater than zero, the quality parameter is lowered. | 05-07-2009 |
20090115790 | DISPLAY CONTROL DEVICE AND MOBILE ELECTRONIC APPARATUS - A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc. | 05-07-2009 |
20090135192 | PROGRAMMABLE DATA PROCESSING CIRCUIT - A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit ( | 05-28-2009 |
20090153574 | METHOD AND SYSTEM FOR UPDATING FIRMWARE - A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I | 06-18-2009 |
20090160868 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a connector, a graphics controller, a management controller, and a power supply control module. The graphics controller controls output of video signals and audio signals from the connector. The management controller inputs/outputs the various commands via the connector. The power supply control module supplies power for operation to both of the graphics controller and the management controller during a power-off state, and supplies power for operation only to the management controller in a power-on state. Both of the graphics controller and the management controller include a function of acquiring identification information of the connection destination by means of the signal line. And, the management controller deactivates the function of acquiring identification information of the connection destination by means of the signal line during a power-on state. | 06-25-2009 |
20090201305 | ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY - An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image. | 08-13-2009 |
20090237412 | Data display system, data relay device, data relay method, data system, sink device, and data read method - A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater. | 09-24-2009 |
20090244077 | SEMICONDUCTOR MEMORY DEVICE, IMAGE PROCESSING SYSTEM, AND IMAGE PROCESSING METHOD - A semiconductor memory device comprises: a memory cell group, the memory cell including a number of which is 2n, the n being a positive integer; and a first decoder provided with respect to each of the memory cell groups and a second decoder. The first decoder activates a word line by the memory cell group based upon a first address and an n bit in a second address and the second decoder activates a bit line based upon the second address. | 10-01-2009 |
20090295813 | Integrated circuit design method for improved testability - A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing. | 12-03-2009 |
20090309889 | Method and Apparatus for Contolling Writing of Data to Graphic Memory - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space. | 12-17-2009 |
20090315904 | Information Processing Apparatus - An information processing apparatus including: a display section; a memory section which memorizes a display configuration for displaying each processing condition of a job on the display section, the display configuration having been selected from a plurality of display configuration types and set by being correlated with the each processing condition; and a control section which controls to display a plurality of processing conditions on the display section by utilizing the display configuration having been correlated with the each processing condition and memorized in the memory section. | 12-24-2009 |
20100026693 | DISPLAY DEVICE AND METHOD FOR UPDATING DATA IN DISPLAY DEVICE - Provided is an image display device. The image display device includes an interface, a memory, a controller, and a display unit. The interface supports communication with an external storage medium, and the memory stores data transmitted through the interface. The controller compares attribute information of data stored in the memory with that of data stored in the external storage medium when the external storage medium is connected through the interface and controls changing of a data name of data stored in the memory or a data name of data stored in the external storage medium depending on whether the attribute information is identical. The display unit displays whether a data name is changed in response to a control signal from the controller. | 02-04-2010 |
20100053180 | METHOD AND SYSTEM FOR CRYPTOGRAPHICALLY SECURING A GRAPHICS SYSTEM - A system and method for cryptographically securing a graphics system connectable via an external bus to a computing system, the graphics system including a graphics processor, a video memory and a memory controller for controlling the flow of data to and from the video memory. The graphics system further includes a copy engine for copying data between a system memory of the computing system and the video memory, where this copy engine acts independently of the graphics processor of the graphics system. The present invention enables the copy engine of the graphics system to decrypt encrypted data in the course of copying data from the system memory to the video memory and to encrypt unencrypted data in the course of copying data from the video memory to the system memory. Thus, cryptographic protection of secure content may be assured by the graphics system without the excessive usage of its primary resources for this non-graphical purpose. | 03-04-2010 |
20100053181 | METHOD AND DEVICE OF PROCESSING VIDEO - A memory controller is disclosed that allocates local memory space to a set of macroblocks of a picture being processed. Information associated with a specific macroblock of the set of macroblocks is written to non-local memory when it is no longer needed to complete processing of a current row of macroblocks. When information associated with the specific macroblock is later needed to process a different row of macroblocks, the memory controller allocates local memory space to the specific macroblock and stores the previously saved information from non-local memory to the local memory. | 03-04-2010 |
20100118040 | METHOD, SYSTEM AND COMPUTER-READABLE RECORDING MEDIUM FOR PROVIDING IMAGE DATA - The present disclosure relates to a method, system and computer-readable medium for providing image data. According to an exemplary embodiment, a method of providing image data includes storing a particular region on image data in association with a keyword, comparing conditional information with the keyword associated with the particular region, when receiving the conditional information from a user terminal unit, and controlling a display state of the image data to allow the particular region to be displayed on a screen of the user terminal unit. When a user inputs a keyword including content relating to a geographical feature or object, an actual shape of the geographical feature or object can be displayed on a screen of the user terminal unit. | 05-13-2010 |
20100171747 | DDC COMMUNICATION MODULE - Provided is a display data channel (DDC) communication module reading and storing extended display identification data (EDID) of a display device and providing the stored EDID to a host device. The DDC communication module includes: a serial electrically erasable and programmable read only memory (EEPFROM) in which the EDID is stored; a comparator outputting logic data indicating that the comparator is connected to the display device or the host device; and a controller reading and storing EDID, or providing EDID stored in the serial EEPROM to the host device, according to the logic data output from the comparator. | 07-08-2010 |
20100177106 | ARBITRATION CIRCUIT TO ARBITRATE CONFLICT BETWEEN READ/WRITE COMMAND AND SCAN COMMAND AND DISPLAY DRIVER INTEGRATED CIRCUIT HAVING THE SAME - An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation. | 07-15-2010 |
20100188411 | Non-Graphics Use of Graphics Memory - Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc. | 07-29-2010 |
20100201697 | Die Customization using Programmable Resistance Memory Elements - A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display. | 08-12-2010 |
20100207952 | MAGNETIC MEMORY DISPLAY DRIVER SYSTEM - In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver. | 08-19-2010 |
20100271377 | Electrophoretic Display Controller Providing PIP And Cursor Support - Data pixels defining first and second images are stored in first and second image buffers, respectively. A second image coordinate location within a display matrix of a display device having display pixels that have multiple stable states is stored in a memory. Data pixels of the first image are read from the first image buffer. If a data pixel read from the first image buffer is within the second image coordinate location, a data pixel from the second image buffer corresponding with the data pixel read from the first image buffer is read, and the data pixel read from the second image buffer is combined with the corresponding data pixel read from the first image buffer to generate a derived data pixel. Synthesized pixels corresponding with at least each of the data pixels of the second image are generated. The synthesized pixels respectively include the derived data pixels. | 10-28-2010 |
20100271378 | Rapid Activation Of A Device Having An Electrophoretic Display - A method for booting up a system includes detecting a reset condition, and in response to detecting the reset condition, driving a display device having display pixels that have multiple stable states with a reset drive scheme. The reset drive scheme is used to drive the display pixels to a known display state. The driving of the display device may be performed by a display controller. In addition, initialization instructions are executed to place at least one component of the system in an active state. The executing of initialization instructions may be performed by a host. The driving of the display device with the reset drive scheme and the executing of the initialization instructions are performed in parallel. The method may include driving the display device with a first drive scheme to display an initial start-up screen in parallel with the executing of the initialization instructions. | 10-28-2010 |
20100295859 | VIRTUALIZATION OF GRAPHICS RESOURCES AND THREAD BLOCKING - Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map. | 11-25-2010 |
20100321397 | Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System - In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed. | 12-23-2010 |
20100328329 | APPARATUS AND METHOD FOR PROCESSING DATA - Incoming video data is processed. According to an example embodiment, video data as presented in rows of pixels is stored in terms of blocks of pixels of corresponding images making up the video. When a particular pixel is read from memory, the block of pixels is retrieved (e.g., with a single read), facilitating (simultaneous) access to pixels in adjacent rows or columns, without necessarily accessing entire rows and columns to do so. | 12-30-2010 |
20100328330 | MEMORY CONTROLLER AND MEMORY SYSTEM USING THE SAME - According to an aspect of embodiment, a memory controller for controlling a memory having areas of data unit of K bits, includes a data mapping unit dividing N bits of data, where N is not a multiple of K, into K bits and (N−K) bits, and in regard to L pieces of the data, arranging L K-bit data into L data units, and arranging L (N−K)-bit data into M (M=L×(N−K)/K) data units by packing; and an access control unit access-controlling the memory to access the L K-bit data as L data units, and access-controlling the memory to access the packed L (N−K)-bit data as M data units. | 12-30-2010 |
20110018885 | METHOD AND APPARATUS FOR MIRRORING FRAME - A method and an apparatus for mirroring a frame are provided. The method is suitable for a display device having a first storage unit and a second storage unit. In the present method, pixel values of a pixel row of the frame are read from the first storage unit and written into the second storage unit. Then, the pixel values of the pixel row of the frame are read from the second storage unit and written back to the first storage unit. When performing one of foregoing reading and writing steps, the pixel values of the pixel row are read or written in a reverse direction to mirror the pixel row. Finally, foregoing steps are repeated to mirror each pixel row of the frame, so as to mirror the entire frame. | 01-27-2011 |
20110025699 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes a first pad group connected to a first memory pad group arranged along a first chip side of a chip of an image memory stacked on the integrated circuit device, a second pad group connected to a second memory pad group arranged along a third chip side, a control section which controls display of an electro-optical device, and a third pad group from which a data signal and a control signal for display control. The first pad group is arranged along a first side of the integrated circuit device, wherein the second pad group is arranged along a third side facing the first side, and wherein the third pad group is arranged along a second side which intersects with the first side and the third side. | 02-03-2011 |
20110037770 | Memory Address Re-mapping of Graphics Data - A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries. | 02-17-2011 |
20110050714 | Image processing device and imaging apparatus - An image processing device includes a memory interface to read out image data from a memory, and a memory access controller to control reading process of the memory interface so as to keep a number of pixels in a main scanning direction of the image data read out from the memory smaller than a number of pixels in a main scanning direction of a screen to which the image data is output. | 03-03-2011 |
20110063313 | MEMORY COHERENCY IN GRAPHICS COMMAND STREAMS AND SHADERS - One embodiment of the present invention sets forth a technique for performing a computer-implemented method that controls memory access operations. A stream of graphics commands includes at least one memory barrier command. Each memory barrier command in the stream of graphics command delays memory access operations scheduled for any command specified after the memory barrier command until all memory access operations scheduled for commands specified prior to the memory barrier command have completely executed. | 03-17-2011 |
20110063314 | DISPLAY CONTROLLER SYSTEM - A display controller system with a memory controller and buffers is described. The system enables transferring data from the main memory of the CPU to the image memory without interfering the image updating. As a result, the present invention may allow continuously updating the display image and continuously writing new image data from CPU to the image memory which improves overall system performance. | 03-17-2011 |
20110080419 | Methods of and apparatus for controlling the reading of arrays of data from memory - A display controller reads blocks of data from a frame buffer and stores them in a local memory buffer of the display controller before outputting the blocks of data to a display. The display controller uses similarity meta-data associated with the output frame in the frame buffer to determine whether a new block of data to be processed for display is similar to a block of data already stored in the local memory of the display controller or not. If it is determined that the data block to be processed is similar to a data block already stored in the local buffer of the display controller, the display controller does not read a new data block from the frame buffer but instead provides the existing data block in its buffer to the display. | 04-07-2011 |
20110102444 | INFORMATION DISPLAY DEVICE AND INFORMATION DISPLAY METHOD - The digital photo frame ( | 05-05-2011 |
20110115803 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC DEVICE - An integrated circuit device includes: a memory controller; and a read-modify-write circuit, when the number of bits of each pixel of a first image data is N (N is a natural number), the number of rewrite unit bits of the first image data is M (M is a natural number of M≧N), and the number of bits for which the memory controller can access a image memory at one time is L (L is a natural number of two or more that fulfills L>M), the read-modify-write circuit rewrites pixel data of the first image data corresponding to active write enable signals, among L/M (L and M are each a natural number multiple of N) of write enable signals corresponding to the L bits, into corresponding pixel data of the second image data. | 05-19-2011 |
20110122141 | MAP DATA RECORDING DEVICE, MAP DISPLAY, MAP DATA RECORDING METHOD, MAP DISPLAY METHOD, MAP DATA RECORDING PROGRAM, MAP DISPLAY PROGRAM, AND RECORDING MEDIUM - In a map data recording device ( | 05-26-2011 |
20110134133 | IMAGE PROCESSING DEVICE - Provided is an image processing device with which processing performance can be improved at low cost. The image processing device ( | 06-09-2011 |
20110148891 | Method and Apparatus for Frame Buffer Management - Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively. | 06-23-2011 |
20110157198 | Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source. | 06-30-2011 |
20110242120 | DISPLAY APPARATUS AND DRIVIING DEVICE FOR DISPLAYING - The display unit can reduce the electric power consumed by the process of calculating an adjustment coefficient for display data, as typified by gradient control, and it can be readily adapted even to a display panel with a higher resolution. The display unit includes: a plurality of driving units arrayed in parallel and each operable to output a drive signal to a display panel; a plurality of first calculation units, and a plurality of display RAMs, each paired with one first calculation unit, the pairs of the first calculation units and display RAMs laid out along a direction of the parallel array of the driving units; and a second calculation unit which distributes display data supplied from outside to the display RAMs, receives display data from the display RAMs in parallel to analyze a histogram of tone distribution of pixel data corresponding to one screen, and calculates the adjustment coefficient based on a result of the analysis. In the display unit, the adjustment coefficient thus calculated is sent back to the first calculation units. The first calculation unit performs a calculation using display data read from the corresponding display RAM and the adjustment coefficient thereby to create drive data for the display panel. | 10-06-2011 |
20110242121 | SLIDE PREPARATION - Presenting a slide. Anticipating a slide to be selected for display. Receiving data of the anticipated slide in an unconstructed format. Constructing the anticipated slide from the received data. Caching the constructed slide. Pre-drawing the constructed slide in construction memory. Receiving instructions to display a slide. In the event that the instructed slide is the cached and pre-drawn slide, rendering the pre-drawn slide to display memory. | 10-06-2011 |
20110261064 | 10T SRAM FOR GRAPHICS PROCESSING - A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value. | 10-27-2011 |
20110267361 | SCANNING IMAGE DISPLAY APPARATUS - A scanning image display apparatus includes a light source unit ( | 11-03-2011 |
20110298814 | SWITCHING VIDEO STREAMS FOR A DISPLAY WITHOUT A VISIBLE INTERRUPTION - The disclosed embodiments provide a system that facilitates driving a display in a computer system. During operation, the system receives an input video stream from a graphics source, wherein the input video stream comprises a sequence of video frames. Next, the system directs the input video stream through a set of two or more memory buffers including a front buffer and a back buffer to produce an output video stream, which is used to drive the display. While directing the input video stream through the set of memory buffers, the system writes a video frame from the input video stream into the back buffer, and concurrently drives the output video stream from a preceding video frame in the front buffer. When the writing of the video frame completes, the system switches buffers so that the back buffer becomes the front buffer, which drives the output video stream, and the front buffer becomes either a spare buffer or the back buffer, which receives a subsequent frame from the input video stream. | 12-08-2011 |
20120007872 | Method And Computer Program For Operation Of A Multi-Buffer Graphics Memory Refresh, Multi-Buffer Graphics Memory Arrangement And Communication Apparatus - A method for refresh operation of a multi-buffer arrangement for a graphics memory having a first and a second operation mode is disclosed. The method comprises writing information to one of a first and second buffers of the multi-buffer arrangement; presetting the one of the buffers, when previous refresh operation was in the second operation mode, before the writing of information to the one of the buffers; dynamically selecting one of the first and the second operation mode; copying information, when in the first operation mode, between a first and a second buffer of the multi-buffer arrangement, before the writing of information to the one of the buffers; and providing information from the buffer arrangement to a display. Computer programs, multi-buffer arrangements and communication apparatuses comprising such multi-buffer arrangements are also disclosed. | 01-12-2012 |
20120013628 | INFORMATION PROCESSING APPARATUS, SCREEN DISPLAY CONTROL METHOD AND PROGRAM - An information processing apparatus includes memories | 01-19-2012 |
20120013629 | Reading Compressed Anti-Aliased Images - Embodiments of the present invention enable the reduction of the memory bandwidth required for graphics rendering. According to an embodiment, a method to render a pixel from a compressed anti-aliased image includes: accessing metadata for the pixel, where the metadata includes entries for respective samples generated by multisampling the pixel; and retrieving a subset of said samples based upon the metadata, wherein the subset is stored in the compressed anti-aliased image stored in a memory. | 01-19-2012 |
20120019544 | IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING THE SAME - An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory. | 01-26-2012 |
20120019545 | DISPLAY DEVICE AND IMAGE DISPLAY METHOD - An image display device of the present invention comprises a first determination section for monitoring information respectively appended to a plurality of images, and detecting information that has been appended to the most images among the plurality of images as first information, a second determination section for detecting information other than the first information, among the information that has been respectively appended to the plurality of images, as auxiliary information, and a third determination section for detecting an image to which the first information has been appended, and which is an image having the auxiliary information, as a priority image. | 01-26-2012 |
20120069034 | QoS-aware scheduling - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 03-22-2012 |
20120081379 | IMAGE DISPLAY SYSTEM - A method of storing an image on a storage device in a tiled format is provided. The method includes formatting the storage device to include a block size such that a tile size is an integer multiple of the block size, and the tile size corresponds to a display output. The method further includes reading pixel data of a source image; and generating, from the read pixel data, a first tile and a second tile. The first tile and the second tile each have overlapping portions that overlap by an adjustable amount, and the overlapping portions include substantially identical pixel data. The method also includes storing the first tile and the second tile on the storage device; and repeating the reading, generating, and storing a plurality of times to store the image. The image is stored on the storage device as a contiguous string of data. | 04-05-2012 |
20120098843 | APPARATUS FOR CONTROLLING MEMORY DEVICE AND RELATED METHOD - A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units. | 04-26-2012 |
20120127185 | SYSTEM AND METHOD FOR AN OPTIMIZED ON-THE-FLY TABLE CREATION ALGORITHM - A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer. | 05-24-2012 |
20120127186 | DISPLAY CONTROL APPARATUS, DISPLAY CONTROL METHOD, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM AND INTEGRATED CIRCUIT - A display control apparatus includes: an updating frequency calculator ( | 05-24-2012 |
20120139931 | DISPLAY SYSTEM HAVING FLOATING POINT RASTERIZATION AND FLOATING POINT FRAMEBUFFERING - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 06-07-2012 |
20120169750 | DISPLAY DEVICE AND DRIVE METHOD FOR DISPLAY DEVICE - Provided are a memory-type display device capable of improving image quality during a normal mode and a method for driving such a display device. Each memory circuit (MR | 07-05-2012 |
20120169751 | DISPLAY APPARATUS AND DISPLAY APPARATUS DRIVING METHOD - In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t | 07-05-2012 |
20120176388 | LIQUID CRYSTAL DISPLAY DEVICE AND DRIVE METHOD THEREFOR - In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t | 07-12-2012 |
20120229483 | PANEL DRIVING DEVICE AND DISPLAY DEVICE HAVING THE SAME - A panel driving device for driving a display panel including N data lines is disclosed. The panel driving device includes a memory array and a source driver. The memory array includes M memory blocks, a controller and an output unit. Each memory block includes N memory units. The controller is configured to divide serial image data into M groups of sub-image data and write each group of sub-image data into the corresponding memory block sequentially, wherein each group of sub-image data has N sub-image data. The output unit is configured to output the data in the M memory blocks sequentially in a time division manner in response to a selection signal. The source driver includes N driving units having the same configuration. After the driving unit receives the time-divided data output from the output unit, signal processing is performed to generate an image signal to be output to the corresponding data line. | 09-13-2012 |
20120236015 | IMAGE DISPLAY SYSTEMS AND METHODS OF PROCESSING IMAGE DATA - Image display systems include a first memory, a memory controller and a device driver. The controller is configured to generate an interrupt signal in response to a command to write first image data into a first range of addresses within the first memory, which at least partially overlaps with a reference range of addresses. The device driver is configured to read the first image data from the first memory in response to the interrupt signal. | 09-20-2012 |
20120249565 | SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING METHOD, AND DISPLAY APPARATUS - A signal processing circuit includes: a memory storing an image signal; a write control unit generating a write control signal in synchronization with the input image signal and frame identification information, and storing the input image signal in the memory so that the input image signal corresponds to the frame identification information on the basis of the write control signal; and a read control unit generating a read control signal through obtaining a vertical synchronization signal supplied from outside based on a timing signal of an output horizontal frequency, and reading an image signal that corresponds to the frame identification information from the memory on the basis of the read control signal and the frame identification information supplied from outside. | 10-04-2012 |
20120249566 | FLOATING POINT COMPUTER SYSTEM WITH FRAME BUFFER FOR STORING COLOR VALUES DURING OR AFTER RASTERIZATION - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 10-04-2012 |
20120256932 | FLOATING POINT COMPUTER SYSTEM ON A SINGLE CHIP - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 10-11-2012 |
20120256933 | FLOATING POINT COMPUTER SYSTEM WITH FLOATING POINT MEMORY - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 10-11-2012 |
20120262467 | IMAGE PROCESSING APPARATUS THAT ENABLES TO REDUCE MEMORY CAPACITY AND MEMORY BANDWIDTH - An image processing apparatus includes a memory control circuit that stores pixel data in a frame memory, an image processing circuit that processes the pixel data stored in the frame memory, and an output circuit that outputs processed pixel data. The memory control circuit divides the pixel data into upper bit portions and lower bit portions, and a lower bit processing circuit stores the lower bit portions in the frame memory by one of (i) dividing lower bit portion of each of the pixel data into n unit portions and storing corresponding one of n unit portions in the frame memory during each of n successive frame periods, and (ii) dividing pixels constituting each of the frames into n groups and storing the lower bit portions of the pixel data of pixels in corresponding one of n groups in the frame memory during each of n successive frame periods. | 10-18-2012 |
20120274647 | PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES - This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate. | 11-01-2012 |
20120293525 | INTEGRATED CIRCUIT DESIGN METHOD FOR IMPROVED TESTABILITY - A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing. | 11-22-2012 |
20120320072 | Data Access Method and Electronic Apparatus for Accessing Data - A data access method applicable to a storage apparatus for reducing or eliminating an image tearing effect includes defining at least one write check point; comparing an actual write speed for writing data into the storage apparatus with a predetermined write speed at the write check point; and adjusting the actual write speed when a difference between the actual write speed and the predetermined write speed is larger than a predetermined value, for adaptively reducing the difference to be smaller than or equal to the predetermined value. | 12-20-2012 |
20120327096 | IMAGE GENERATING DEVICE - There is provided with an image generating device in which the selecting unit selects a first buffer from frame buffers, the storage stores identification information of a frame buffer storing a latest image on an area-basis, the drawing unit draws and writes image data in the first buffer and specifies an update area including a written area, the updating unit updates the identification information to show that a latest image of the written area is stored i n the first b uffer, the modifying unit specifies an area storing an image that is not the latest in the update area and reads latest image data relating to the area from another frame buffer storing the latest image, and writes it in the area of the first buffer, the image generating unit reads image data of the update area in the first buffer, the communication unit transmits it to the display terminal. | 12-27-2012 |
20130002693 | VIDEO DISPLAY APPARATUS, BUFFER MANAGEMENT METHOD AND VIDEO DISPLAY SYSTEM - One embodiment provides a video display apparatus, including: a buffer configured to receive data; a buffer controller configured to control the buffer; and a reproduction part configured to reproduce the data accumulated in the buffer, wherein, when reproduction from an arbitrary position is designated for a time during which the reproduction part reproduces the data, the buffer controller controls the buffer to accumulate data of a designated destination while continuing reproduction of the data left in the buffer. | 01-03-2013 |
20130021354 | METHOD AND SYSTEM FOR DISPLAYING USING BUFFER SWAPPING - Methods and systems which may implement buffer swapping are provided. The methods include rendering, onto screen locations of a display screen, data from a memory having a first buffer and a second buffer, each buffer having respective buffer memory locations which correspond to the screen locations of the display screen. The methods can include: rendering first data from the first buffer onto the display screen; writing, to the second buffer, second data based on at least some of the first data from the first buffer by performing at least one of transforming at least some first data and changing corresponding screen locations of at least some first data from the first buffer, by writing at most once to each buffer memory location of the second buffer; and rendering the second data from the second buffer onto the display screen. | 01-24-2013 |
20130021355 | METHOD AND SYSTEM FOR DISPLAYING PROIRITIZED LIVE THUMBNAIL OF PROCESS GRAPHIC VIEWS - The system for displaying prioritized live thumbnail of process graphic views includes at least one real time data source | 01-24-2013 |
20130033510 | Techniques for Controlling Power Consumption of a System - A chipset can detect whether a relevant portion of the system frame buffer has been updated and can send an interrupt to the display driver to invoke a registered hardware watchpoint routine to inform display driver of the updating. If the display is currently in display self refresh (DSR) state, display driver wakes up display controller components and requests to transmit a MIPI compatible DCS command to request copying of the updated data from system frame buffer into an on-panel frame buffer or a frame buffer associated with the display. The display driver can power-down graphics system components and enter DSR state again to save power. | 02-07-2013 |
20130069965 | TWO DIMENSIONAL MEMORY ACCESS CONTROLLER - A memory control device derives a two dimensional location on a graphic display surface from address signals of a graphics processing unit (GPU). The memory controller compares the derived two dimensional location to a two dimensional range of authorized locations corresponding to a subset of the display surface. The memory controller modifies the address signals of the graphics processing unit (GPU) if the address signals do not fall within the two-dimensional range of authorized locations corresponding to a subset of the display surface, and propagates the address signals unmodified to a display memory otherwise. | 03-21-2013 |
20130100148 | DISPLAY CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME - A display controller includes a graphic memory, a graphic memory control unit and a scan control unit. The graphic memory has a storage capacity defined by a first directional size multiplied by a second directional size. The graphic memory control unit converts two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, converts the 1-D addresses to physical 2-D addresses based on the first directional size and controls the graphic memory to store the input data. The display panel has a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel. The scan control unit increases scan addresses one line by one line to display data stored in the graphic memory according to a display resolution. | 04-25-2013 |
20130100149 | Portable Digital Display - A portable digital display assembly is disclosed. The portable digital display device is configured to be operated by a wired or wireless device. The portable digital display is battery powered and has arrays of LED's configured to creating a display. | 04-25-2013 |
20130120419 | Memory Controller for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments. | 05-16-2013 |
20130127884 | DISPLAY CONTROL APPARATUS, DISPLAY CONTROL METHOD, AND PROGRAM - The present technology relates to a display control apparatus, a display control method and a program which can suppress, for example, distortion of an image caused when an image transmitted from a data transmission channel is displayed with a little delay. A write information measurement unit measures a write preparation time required to start writing a received image in a display buffer which temporarily holds the image, a write control unit controls the writing of the image according to whether or not the write preparation time is a threshold time or more which represents a write preparation time at which the writing of the image is finished at a display end time at which the image is displayed in synchronization with a display timing at which the image needs to be displayed, and a display control unit displays the image written in the display buffer under control of the write control unit in synchronization with the display timing by a write time at which the image can be displayed in synchronization with the display timing. The present technology is applicable to, for example, a display apparatus which displays image data to be transmitted with a little delay. | 05-23-2013 |
20130155084 | Virtualization of Graphics Resources and Thread Blocking - Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map. | 06-20-2013 |
20130169655 | ELECTRONIC SYSTEM, CONTROL METHOD THEREOF, DISPLAY APPARATUS, UPGRADE APPARATUS, AND DATA INPUT/OUTPUT PROCESSING METHOD OF DISPLAY APPARATUS - An electronic system, a control method for the electronic system, a display apparatus, an upgrade apparatus, and a data input/output processing method of the display apparatus are provided. The electronic system includes a first system on chip (SOC) including a first functional block which performs a first function, a second functional block which performs a second function, and a first bus network which performs communication between the first functional block and the second functional block, a connection unit which connects a second SOC to the first SOC, wherein the second SOC comprises a third functional block configured to upgrade the first function and a second bus network, and a power supply unit which supplies power to the first SOC and the second SOC, wherein the power supply unit blocks power from being supplied to the first functional block if the second SOC is connected to the connection unit. | 07-04-2013 |
20130194285 | STORAGE APPARATUS AND METHOD OF CONTROLLING THE SAME - There is provided a storage apparatus for providing an effective memory addressing method. The storage apparatus includes at least one memory and at least one controller coupled to the at least one memory to provide address information. Each of the controllers includes a first controller for providing on/off information of subfields included in one frame for driving pixels in a display panel, a third controller for horizontal position information corresponding to a selected scan line from scan lines of a display panel, and a second controller for providing vertical position information corresponding to a pixel on the selected scan line. On/off information of subfields for at least two pixels is stored in a cell located at the vertical position and the horizontal position in the at least one memory. | 08-01-2013 |
20130207985 | IMAGE PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An image processing apparatus involving various settings, that allows a user to easily restore setting values after changing the setting values. Extracted difference in setting value indicating a difference between setting information at the time of execution of n−1 | 08-15-2013 |
20130215130 | DISPLAY APPARATUS AND DISPLAY CONTROL METHOD - A rendering control unit determines movie and graphic display modes with reference to a rendering processing command, and acquires maximum speed information indicating the maximum value of a read/write speed allowed for a memory. The rendering control unit decides a speed to be distributed to a read/write speed of the movie data and a speed to be distributed to a read/write speed of the graphic data with respect to the memory, of a maximum speed indicated by the maximum speed information, based on the determination result. The rendering control unit controls a read/write access of an image with respect to the memory based on the rendering processing command, in accordance with the decided speeds. | 08-22-2013 |
20130229424 | METHOD AND APPARATUS FOR WIRELESS IMAGE TRANSMISSION TO A PROJECTOR - A method and apparatus is provided in which a digital image is transmitted to a presentation projector resource over a wireless transmission medium using a reduced amount of bandwidth by transmitting a subset of the digital image data. The subset of image data may be a delta subset that represents those areas of the image that have changed since the previous transmission. The subset image data may also be a scalable vector graphics representation of the subset of the digital image. A projector discovery logic selects a suitable projector resource based on the order or signal strength of the discovery replies. A wireless image transmission session is established with the selected projector resource during which the projector is unavailable to other devices. The subset image data may be compressed and transmission coordinated with the projector resource so that the data is sent only when it is ready to be received. | 09-05-2013 |
20130249921 | SERVER, SCREEN TRANSFER SYSTEM, AND SCREEN TRANSFER METHOD - There is provided a server in which a screen update generating unit generates screen update information representing an image of an update area in a screen; a distributing unit distributes the screen update information to a transmitting unit selected from first to N-th transmitting units; a storage stores a generation history of the screen update information; and a precedence possibility determining unit specifies, based on the generation history of the screen update information, screen update information X and Y such that the screen update information X is more previously generated than the screen update information Y and that the image of the screen update information Y is permitted to be displayed prior to the screen update information X, wherein the distributing unit distributes the screen update information Y to the transmitting unit different from that of distributing the screen update information X. | 09-26-2013 |
20130249922 | INFORMATION PROCESSING APPARATUS, DISPLAY CONTROL METHOD, AND PROGRAM - According to one embodiment, an information processing apparatus having an internal display and a connection module for an external display, includes a storage module configured to store items of virtual desktop information to be displayed on an actual display screen of one of the internal display and the external display and items of information of a display which displays the items of virtual desktop information in association with each other, and a control module configured to read out, from the storage module, an item of virtual desktop information in association with the external display and to supply the item of virtual desktop information in association with the external display to external display upon detecting that the external display is connected to the connection module when one of the items of virtual desktop information is displayed on the actual display screen of the internal display. | 09-26-2013 |
20130271477 | METHOD FOR MANAGING MEMORY AND IMAGE DISPLAY DEVICE FOR SAME - The method for managing memory according to the plurality of accounts in an image display device includes: obtaining memory management data according to the plurality of accounts; obtaining information on one account when a command for storing data, which are selected while logged on to the one account, is inputted; and displaying a memory management menu accordingly. The storage space of an image display device may be used to ensure usage efficiency for a user using a plurality of accounts. | 10-17-2013 |
20130278616 | RESOLUTION LOSS MITIGATION FOR 3D DISPLAYS - Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the display mode, where preparing the stereoscopic image content includes storing a full resolution left image and a full resolution right image in memory, and determining a display refresh rate in response to at least a content frame rate of the stereoscopic image content. The stereoscopic image content may then be processed for display according to the display type, the display refresh rate, and a power policy. | 10-24-2013 |
20130278617 | TILE ENCODING AND DECODING - A tile of pixels is encoded by variable length encoding at least a first block of pixels into a first sequence of symbols and a second block of pixels into a second sequence of symbols. The symbols of the first and second sequences are co-organized into a combined sequence of symbols in which the symbols of the first sequence are readable in a first reading direction and at least a portion of the symbols in the second sequence are readable in a second, opposite reading direction. The encoding of the tile to form one or more combined sequences significantly reduces the bandwidth requirements when writing the tile to a pixel value buffer. The co-organization of the first and second sequences enables parallel reading and decoding of the first and second sequences from the pixel value buffer, thereby reducing any decoding latency. | 10-24-2013 |
20130293560 | RENDERING DEVICE AND RENDERING METHOD - A DMA controller operates independently from a CPU, reads image data stored on an ROM sequentially in given units from the first reading start position of the image data and writes the image data into a buffer. A DMA controller operates independently from the CPU, writes the data read into the buffer to a VRAM one byte at a time from the writing start position. The controller of a companion chip updates the writing start position in the VRAM to the position of the same column in the next row each time writing the data string in each row is completed. | 11-07-2013 |
20130314428 | IMAGE PROCESSING APPARATUS AND ASSOCIATED METHOD - An image processing apparatus includes a first memory, a second memory, a buffer, a fetching module and a processing module. The first memory module stores an original image having a first width. The buffer has a second width smaller than the first width. The fetching module fetches a sub-image of the original image from the first memory and stores the fetched sub-image into the buffer. The processing module performs an image processing process on the sub-image stored in the buffer to generate a processed sub-image. The processed sub-image is then stored into the second memory. | 11-28-2013 |
20130314429 | ADAPTIVE FRAME BUFFER COMPRESSION - Image data is subject to compression and decompression when it is respectively written to and read from a frame buffer. If a portion of the image data is identified as static (subject to less than a threshold amount of change for greater than a threshold time), then compression control parameters used for compression of that portion of the image are adjusted so as to increase the compression ratio achieved, hold the degree of lossiness substantially constant and increase the energy consumed while compressing that portion. The increased energy consumption during this high compression ratio compression is likely compensated for by a reduction in energy subsequently consumed when writing that frame-buffer image data to the frame buffer and reading that frame-buffer image data multiple times from the frame buffer. The compression characteristics varied may be to increase the block size used in the compression. Other variations in compression applied may be to change from single-pass compression to multi-pass compression, switch compression on and off altogether, or reorder the data when it has been compressed so as to match the order it will be read and so achieve support for longer read burst. | 11-28-2013 |
20130328896 | TILED VIEWPORT COMPOSITION - A system that buffers an application image reduces bandwidth requirements for accessing memory. The application image may be logically separated into tiles. A viewport may identify a visible portion of the application image, where the visible portion is smaller than the application image. The tiles overlapped by the viewport may be buffered in a front buffer and a back buffer. The tiles not overlapped by the viewport may be buffered in the back buffer but not in the front buffer. A composition manager, with knowledge of the viewport and at least two noncontiguous tile buffers in the front buffer, may extract the visible portion of the application image directly from the noncontiguous tile buffers. | 12-12-2013 |
20130342550 | METHOD AND APPARATUS FOR BUFFERING READ-ONLY IMAGES AND/OR READABLE AND WRITABLE IMAGES INTO BUFFER DEVICE - An exemplary method for buffering an image into a buffer device includes following steps: checking a first predetermined criterion; when the first predetermined criterion is not met, converting at least a first image in the buffer device into at least a corresponding second image in the buffer device, wherein a size of the corresponding second image is smaller than a size of the first image; and when the first predetermined criterion is met, storing a third image derived from the image into the buffer device. | 12-26-2013 |
20140043348 | Display Control Device and Mobile Electronic Apparatus - A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc. | 02-13-2014 |
20140055473 | IMAGE DATA PROCESSING CIRCUIT AND DISPLAY SYSTEM - There is an image data processing circuit including a memory storing input image data, the input image data being limited to a specific number of colors or to a specific image range, and a correction processing part replacing, when a predetermined tone change is present between a pixel in image data previous by one frame whose data is stored by the memory and a pixel in image data in a current frame whose data is input, a relevant pixel in the current frame with a color of a specific tone. The memory is built in an integrated circuit included in the correction processing part. | 02-27-2014 |
20140063030 | SYSTEMS AND METHODS OF PARTIAL FRAME BUFFER UPDATING - Aspects include a pixel source that produces data for a rendered surface divided into regions. A mapping identifies memory segments storing pixel data for each region of the surface. The mapping can identify memory segments storing pixel data from a prior rendered surface, for regions that were unchanged during rendering the rendering. Such changed/unchanged status is tracked on a region by region basis. A counter can be maintained for each memory segments to track how many surfaces use pixel data stored therein. A pool of free memory segments can be maintained. Reading a surface, such as to display a rendered surface by a display controller, includes identifying and reading the mapping to identify each memory segment storing pixel data for regions of the surface, reading such, and updating the counters for the memory segments that were read. | 03-06-2014 |
20140071142 | DISPLAY APPARATUS INCORPORATING VERTICALLY ORIENTED ELECTRICAL INTERCONNECTS - This disclosure provides systems, methods and apparatus for enabling a display to have a faster switching rate and an increased aperture ratio by using vertically oriented electrical interconnects with a reduced footprint. In one aspect, a display apparatus includes an array of display elements and an electrical interconnect connected to at least one display element in the array of display elements. A cross sectional aspect ratio of the electrical interconnect can be up to 1:1 or greater than 1:1. | 03-13-2014 |
20140071143 | Image Compression Circuit, Display System Including the Same, and Method of Operating the Display System - An image compression circuit includes an encoder configured to compress a current frame and to output current frame compressed data and a current frame bitstream; a decoder configured to decode the previous frame bitstream and to output previous frame compressed data; a frame memory controller configured to write the current frame bitstream to a frame memory and simultaneously read a previous frame bitstream from the frame memory; a dynamic capacitance compensation controller configured to output a previous frame reference value based on the current frame, the current frame compressed data, and the previous frame compressed data; and an overdrive circuit configured to generate a current overdriven frame including an overdrive pixel value for a current pixel based on a pixel value of the current pixel in the current frame and the previous frame reference value. | 03-13-2014 |
20140078160 | DISPLAY-CONTROLLING METHOD AND DISPLAY DEVICE - A display-controlling method for controlling a display device to dynamically adjust a display configuration tag is disclosed in this invention. The display-controlling method includes steps of: determining whether a predetermined display function is enabled on the display device; selectively writing the display configuration tag complying with different display signal transmission protocols into a storage unit of the display device according to whether the predetermined display function is enabled on the display device; and, reading the display configuration tag and selectively providing a display signal complying with one of the different display signal transmission protocols. In addition, a display device is also disclosed herein. | 03-20-2014 |
20140078161 | IMAGE PROCESSING DEVICE FOR SCROLLING DISPLAY OF AN IMAGE - An image processing device reads data of plural pixels constituting an image in plural rows and plural columns from a display memory and displays the image at a display device. All of the pixel data constituting the image is continuously read in a sequence of addresses, continuing from an address that stores pixel data that is read last in one row to an address that stores pixel data that is read first in the next row. When the position of the image being displayed on the display device is to be changed, the address at which the continuous reading starts is altered. | 03-20-2014 |
20140085319 | TIMING CONTROLLER, DRIVING METHOD THEREOF, AND FLAT PANEL DISPLAY DEVICE USING THE SAME - Provided are a timing controller for converting RGB data to WRGB data, a driving method thereof, and an LCD device using the same. The timing controller according to an embodiment includes a reception unit to receive input RGB data from an external device; a converter to convert the input RGB data into input WRGB data composed of W, R, G and B data; an aligner to convert one of the W, R, G, and B data into 0 to generate conversion WRGB data, the conversion WRGB data having bits less than the total number of bits composing the W, R, G, and B data; a controller to transfer the conversion WRGB data to an external memory; and a re-aligner to convert the conversion WRGB data received from the external memory into digital WRGB data corresponding to the input WRGB data, and to output the digital WRGB data. | 03-27-2014 |
20140092111 | METHOD OF AND CIRCUIT FOR DISPLAYING AN IMAGE OF A PLURALITY OF IMAGES ON A DISPLAY - A method of displaying a plurality of picture files on a display of a portable wireless communication device is described. The method comprises receiving a plurality of picture files, wherein each picture file of the plurality of picture files has location data stored in a location field for the picture file and relationship data in a relationship field related to at least one other picture file; displaying a first image associated with a first picture file; and displaying a second image in response to a prompt for a next image. | 04-03-2014 |
20140104288 | THROUGH SUBSTRATE VIA INDUCTORS - This disclosure provides systems, methods, and apparatus for through substrate via inductors. In one aspect, a cavity is defined in a glass substrate. At least two metal bars are in the cavity. A first end of each metal bar is proximate a first surface of the substrate, and a second end of each metal bar is proximate a second surface of the substrate. A metal trace connects a first metal bar and a second metal bar. In some instances, one or more dielectric layers can be disposed on surfaces of the substrate. In some instances, the metal bars and the metal trace define an inductor. The inductor can have a degree of flexibility corresponding to a variable inductance. Metal turns can be arranged in a solenoidal or toroidal configuration. The toroidal inductor can have tapered traces and/or thermal ground planes. Transformers and resonator circuitry can be realized. | 04-17-2014 |
20140132614 | DIGITAL ART UNDO AND REDO - The subject disclosure is directed towards saving undo state information for a digital art program. Changed state data is computed (e.g., via GPU-side logic) based upon the state information of the current state of a canvas and the previous state information, e.g., via an XOR operation or parallel XOR operations. The changed state data is compressed into compressed state data, e.g., via run-length encoding, and the compressed state data is stored, e.g., in a circular buffer in GPU memory. For an undo command, the compressed data is decompressed into the changed state data, and the bitwise operation reversed. | 05-15-2014 |
20140139535 | Buffer Underrun Handling - A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller. | 05-22-2014 |
20140146064 | GRAPHICS MEMORY LOAD MASK FOR GRAPHICS PROCESSING - Systems and methods are described including creating a mask that indicates which pixel groups do not need to be loaded from Graphics Memory (GMEM). The mask indicates a pixel group does not need to be loaded from GMEM. The systems and methods may further include rendering a tile on a screen. This may include loading the GMEM based on the indication from the mask and skipping a load from the GMEM based on the indication from the mask. | 05-29-2014 |
20140160137 | FIELD-SEQUENTIAL COLOR MODE TRANSITIONS - This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for selecting an operational mode of a reflective display device from a plurality of operational modes that include at least one field-sequential color mode. The operational mode may be selected based, at least in part, on ambient light data. The ambient light data may include ambient light intensity data, ambient light spectrum data and/or ambient light direction data. The operational mode may be selected based, at least in part, on other criteria, such as display application type and/or battery state data. | 06-12-2014 |
20140168244 | Color Buffer Caching - A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile being rendered is completely inside a triangle. If so, the cache lines that correspond to this tile may be marked as “less useful”. As a result of being marked as less useful, those cache lines may be replaced before other cache lines in one embodiment. Thus a color buffer cache is used for those tiles that overlap with at least one triangle edge. The use of such a color buffer cache scheme may be more efficient and therefore may reduce memory bandwidth in some embodiments. | 06-19-2014 |
20140192073 | GRAPHIC PROCESSOR BASED ACCELERATOR SYSTEM AND METHOD - An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPU), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards (this includes but is not limited to PCI-Express, PCI-X, USB 2.0, or functionally similar technologies). The controller handles most of the primitive operations needed to set up and control GPU computation. As a result, the computer's central processing unit (CPU) is freed from this function and is dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are the information exchanged between CPU and the expansion card. Moreover, since on every time step of the simulation the results from the previous time step are used but not changed, the results are preferably transferred back to CPU in parallel with the computation. | 07-10-2014 |
20140198116 | A METHOD AND DEVICE TO AUGMENT VOLATILE MEMORY IN A GRAPHICS SUBSYSTEM WITH NON-VOLATILE MEMORY - Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command. | 07-17-2014 |
20140204104 | DISPLAY APPATATUS AND METHOD OF DRIVING THE SAME - A display apparatus includes pixels connected to gate lines and data lines, a gate driver configure to drive the gate lines, a data driver including a plurality of data driving parts configured to drive the data lines. The control board includes a processor that outputs an image signal and a control signal and a timing controller that outputs a first control signal to control the gate driver and a second control signal and a data signal to control the data driver in response to the image signal and the control signal. | 07-24-2014 |
20140204105 | DRAM COMPRESSION SCHEME TO REDUCE POWER CONSUMPTION IN MOTION COMPENSATION AND DISPLAY REFRESH - Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module. In addition, the compressed data can be stored to one or more memory chips. Moreover, a read request may be received, wherein stored data is retrieved from at least one of the one or more memory chips in response to the request. Additionally, a decompression of the stored data may be conducted to obtain decompressed data. | 07-24-2014 |
20140218380 | METHOD AND APPARATUS FOR WIRELESS IMAGE TRANSMISSION TO A PROJECTOR - A method and apparatus is provided in which a digital image is transmitted to a presentation projector resource over a wireless transmission medium using a reduced amount of bandwidth by transmitting a subset of the digital image data. The subset of image data may be a delta subset that represents those areas of the image that have changed since the previous transmission. The subset image data may also be a scalable vector graphics representation of the subset of the digital image. A projector discovery logic selects a suitable projector resource based on the order or signal strength of the discovery replies. A wireless image transmission session is established with the selected projector resource during which the projector is unavailable to other devices. The subset image data may be compressed and transmission coordinated with the projector resource so that the data is sent only when it is ready to be received. | 08-07-2014 |
20140232731 | DISPLAY POWER MANAGEMENT - Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines. | 08-21-2014 |
20140232732 | Parameter FIFO - A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit. | 08-21-2014 |
20140240332 | Multiple Quality of Service (QoS) Thresholds or Clock Gating Thresholds Based on Memory Stress Level - In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller. | 08-28-2014 |
20140240333 | DATA PROCESSING DEVICE, DISPLAY CONTROL DEVICE, SEMICONDUCTOR CHIP, METHOD OF CONTROLLING DISPLAY DEVICE, AND COMPUTER-READABLE MEDIUM - A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory. The controller is configured to, when the processed update-data and the update-control-information identifier are stored on the first memory, execute the drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored in the first memory in response to the instruction from the updating unit. | 08-28-2014 |
20140253570 | Network Display Support in an Integrated Circuit - In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation. | 09-11-2014 |
20140253571 | MOBILE DEVICE WITH CONTEXT SPECIFIC TRANSFORMATION OF DATA ITEMS TO DATA IMAGES - In a mobile device with a processing unit, main memory, display memory and display, a context module identifies a user-context, a determiner module determines correspondence or non-correspondence of data images in the main memory to the user-context, a first selector module selects corresponding data images for access by the display memory in case of correspondence, a second selector module select data items in case of non-correspondence, a transformation module transforms selected data items to corresponding data images and stores them in the main memory, and an access module lets the display memory access the selected data images. | 09-11-2014 |
20140253572 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes a first pad group connected to a first memory pad group arranged along a first chip side of a chip of an image memory stacked on the integrated circuit device, a second pad group connected to a second memory pad group arranged along a third chip side, a control section which controls display of an electro-optical device, and a third pad group from which a data signal and a control signal for display control. The first pad group is arranged along a first side of the integrated circuit device, wherein the second pad group is arranged along a third side facing the first side, and wherein the third pad group is arranged along a second side which intersects with the first side and the third side. | 09-11-2014 |
20140253573 | GRAPHICS PROCESSING APPARATUS, DISPLAY APPARATUS FOR AN AIRCRAFT COCKPIT, AND METHOD FOR DISPLAYING GRAPHICAL DATA - Graphics cards normally control the image display of data processing systems. | 09-11-2014 |
20140267331 | DISPLAY APPARATUS INCORPORATING DUAL-LEVEL SHUTTERS - This disclosure provides systems, methods and apparatus for modulating light to form an image on a display, as well as methods manufacturing such apparatus. The display apparatus includes dual-level shutter assemblies. Each dual-level shutter assembly includes front and rear light obstructing levels positioned adjacent to respective front and rear light blocking layers. The front and rear light blocking layers define apertures providing optical paths from a backlight to the front of the display. The dual-level shutters selectively obstruct these optical paths to generate an image. | 09-18-2014 |
20140267332 | Secure Rendering of Display Surfaces - A protected graphics module can send its output to a display engine securely. Secure communications with the display can provide a level of confidentiality of content generated by protected graphics modules against software and hardware attacks. | 09-18-2014 |
20140267333 | IMAGE DISPLAY DEVICE AND IMAGE DISPLAY METHOD - An image display device includes a memory component, a color specification component and a display component. The memory component stores frame data that forms a display image, a color table that stores color data for each selection condition with the color data being indicative of a plurality of colors specified to the frame data, and reference data that associates the selection condition with the color data of the color table. The color specification component specifies the color data to the frame data based on the reference data according to the selection condition. The display component generates the display image based on the frame data and the color data. | 09-18-2014 |
20140292787 | Compressed Frame Writeback and Read for Display in Idle Screen On Case - In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content. | 10-02-2014 |
20140292788 | Mechanism to Detect Idle Screen On - In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content. | 10-02-2014 |
20140300615 | MEMORY ACCESS CONTROLLER, DATA PROCESSING SYSTEM, AND METHOD FOR MANAGING DATA FLOW BETWEEN A MEMORY UNIT AND A PROCESSING UNIT - A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed. | 10-09-2014 |
20140313211 | Color Buffer Compression - In accordance with some embodiments, a mask or table may be maintained to record information about whether or not each pixel within a tile is cleared. As used herein, a “cleared” tile is one that is not covered by any other depicted objects. The clear mask may store a bit per pixel or sample to indicate whether the pixel or sample contains a color value or whether it is cleared. As a result, the compression ratio may be increased for partially covered tiles in some embodiments. | 10-23-2014 |
20140313212 | DISPLAY DEVICE AND INFORMATION COLLECTING METHOD USING THE SAME - A display device is provided. The device includes memories, a display unit, and a data collecting memory. The memories store a plurality of kinds of image data generated based on information acquired from different kinds of sensors, respectively. The display unit displays the image data that is selected by a user among the plurality of kinds of image data. The data collecting memory stores, in response to a predetermined report instruction, at least data of an image displayed on the display unit at the timing of the report instruction and, among the image data stored in the memories at the timing of the report instruction, the image data that is not displayed on the display unit. | 10-23-2014 |
20140320511 | DISPLAY CONTROLLER INTERRUPT REGISTER - Systems, apparatus, articles, and methods are described including operations to set an interrupt range in an interrupt register associated with a display controller. A determination may be made regarding whether a front buffer portion of a frame buffer is within the interrupt range. An interrupt may be communicated based at least in part on the determination that the front buffer portion of the frame buffer is within the interrupt range. | 10-30-2014 |
20140340413 | LAYER ACCESS METHOD, DATA ACCESS DEVICE AND LAYER ACCESS ARRANGEMENT METHOD - A data access method is provided. The data access method is applied for a data device access device to access data from N layers to display an image, where N is a positive integer. Each of the N layers includes a horizontal start point, a horizontal end point, a vertical start point and a vertical end point. The data access method includes: dividing the image into a plurality of regions according to the horizontal start points, the horizontal end points, the vertical start points and the vertical end points, wherein the regions respectively correspond to the N layers; and accessing data from the respective layers corresponding to the regions when displaying the image. | 11-20-2014 |
20140347378 | CONTROL DEVICE, CONTROL METHOD, AND PROGRAM - A remote control, upon determining that a power-saving flag is on, or in other words, upon determining that the remote control is conducting power-saving operating behavior, decides on a monochrome image stored in a reduced image memory as image information to be read by a renderer. The monochrome image has ⅛ the amount of information compared to a color image stored in a normal image memory. Consequently, in the case of power-saving operating behavior by the remote control, the renderer is able to read a monochrome image stored in the reduced image memory with less power compared to the case of reading a color image stored in the normal image memory. Consequently, power consumed in the remote control may be restricted in the case of power-saving operating behavior by the remote control. | 11-27-2014 |
20140362094 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR RECOVERING FROM A MEMORY UNDERFLOW CONDITION ASSOCIATED WITH GENERATING VIDEO SIGNALS - A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame. | 12-11-2014 |
20140362095 | IMAGE CACHE MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT - An image cache memory performs caching of image data, the image cache memory includes a cache buffer, a cache tag unit, a comparator, and a controller. The cache buffer stores cache data for each rectangular block including a plurality of pixels arranged in rectangle, and the cache tag unit stores tags each corresponding to a rectangular-block group including a plurality of rectangular blocks. The comparator makes comparison by using the tags stored in the cache tag unit, and the controller performs the caching by controlling the cache buffer, the cache tag unit, and the comparator. | 12-11-2014 |
20140362096 | DISPLAY CONTROLLER, SCREEN TRANSFER DEVICE, AND SCREEN TRANSFER METHOD - There is provided a display controller for reading frame data from a frame buffer, and generating a screen output image to be displayed on a display, wherein the display controller is provided with a path for extracting the screen output image as a screen image for transfer to be transferred to another apparatus, and writing the screen image for transfer to a dedicated memory provided separately from the frame buffer. | 12-11-2014 |
20150022539 | IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD - An image processing apparatus including a display unit including pixels and more than one core processor. Each core processor includes: a diffusion module changing first pixel data of an image signal divided according to rows and then outputting it using a threshold value corresponding to the first pixel data, generating diffusion data using a difference between the changed first pixel data and the first pixel data, and changing second pixel data and third pixel data using the diffusion data; a memory storing an image signal including the image signal divided according to rows and then outputting it and the pixel data changed in the diffusion module; and a memory controller reading an image signal including pixel data changed in the diffusion module and displaying the read image signal to the display unit. | 01-22-2015 |
20150022540 | METHOD AND APPARATUS FOR CONTROLLING WRITING OF DATA TO GRAPHIC MEMORY - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space. | 01-22-2015 |
20150029203 | Filtering Mechanism for Render Target Line Modification - Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered. | 01-29-2015 |
20150042667 | TECHNIQUES FOR REDUCING MEMORY BANDWIDTH FOR DISPLAY COMPOSITION - Various embodiments are generally directed to an apparatus, method and other techniques to determine color information for multiple graphical layers of a graphical display at a location of a pixel, and to determine a pixel color information for the pixel at the location based on the color information for each of the multiple graphical layers. | 02-12-2015 |
20150049102 | METHOD AND APPARATUS FOR THE PROGRESSIVE LOADING OF MEDICAL MULTIDIMENSIONAL IMAGES INTO A MEDICAL APPLICATION - A method includes a) loading a first number n of image sets with an image size k | 02-19-2015 |
20150062137 | IMAGE QUALITY COMPENSATION DEVICE AND METHOD FOR ORGANIC LIGHT EMITTING DISPLAY - An image quality compensation device for an organic light emitting display includes: a memory having first and second update blocks selectively storing first and second period compensation values, which are sequentially updated at regular intervals; and a timing controller that configures the first update block as either the current memory page for data loading or the next memory page for data writing and the second update block as the other one of the two, based on a preset check code, and updates the memory by calculating the second period compensation value with the passage of driving time based on the first period compensation value loaded from the update block configured as the current memory page, writing the second period compensation value to the update block configured as the next memory page, and then erasing the first period compensation value from the update block configured as the current memory page. | 03-05-2015 |
20150077424 | METHOD AND DEVICE FOR DETECTING A SYNCHRONIZATION SIGNAL OF A DISPLAY, AND DISPLAY - A method for detecting a synchronization signal of a display comprises: obtaining an actual V-sync frequency of the display, comparing the actual V-sync frequency with standard V-sync frequencies prestored in a standard synchronization signal table, and selecting a standard V-sync frequency as a candidate V-sync frequency so that difference between the candidate V-sync frequency and the actual V-sync frequency is within a first error range; obtaining an actual H-sync frequency of the display, comparing the actual H-sync frequency with standard H-sync frequencies in the standard horizontal synchronization signal sub-table which corresponds to the selected candidate V-sync frequency, and selecting a standard H-sync frequency as a correct H-sync frequency so that difference between the correct H-sync frequency and the actual H-sync frequency is within a second error range, thereby a resolution of the display is obtained. | 03-19-2015 |
20150097847 | MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS - One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management. | 04-09-2015 |
20150097848 | DISPLAY APPARATUS, DISPLAY SYSTEM, AND PROGRAM - A display apparatus which can communicate with an information terminal via a network is disclosed. The display apparatus includes a receiving unit which receives content data which are caused to be displayed on the display apparatus and reproduction control information on reproduction of the content data from the information terminal, a storage unit which saves thereon the content data and/or the reproduction control information based on whether there was an occurrence of a stopping cause in a process of saving the content data and/or the reproduction control information that are received from the receiving unit, and a display unit which causes the content data to be displayed on the display apparatus based on the reproduction control information saved in the storage unit. | 04-09-2015 |
20150116340 | SELECTIVE UTILIZATION OF GRAPHICS PROCESSING UNIT (GPU) BASED ACCELERATION IN DATABASE MANAGEMENT - A method for the selective utilization of graphics processing unit (GPU) acceleration of database queries in database management is provided. The method includes receiving a database query in a database management system executing in memory of a host computing system. The method also includes estimating a time to complete processing of one or more operations of the database query using GPU accelerated computing in a GPU and also a time to complete processing of the operations using central processor unit (CPU) sequential computing of a CPU. Finally, the method includes routing the operations for processing using GPU accelerated computing if the estimated time to complete processing of the operations using GPU accelerated computing is less than an estimated time to complete processing of the operations using CPU sequential computing, but otherwise routing the operations for processing using CPU sequential computing. | 04-30-2015 |
20150302547 | IMAGE PROCESSING APPARATUS, METHOD FOR PROCESSING IMAGE, AND COMPUTER READABLE RECORDING MEDIUM - An image processing apparatus may include a main memory configured to store an application for reproducing image content, and setting information corresponding to the stored application, a first ancillary memory configured to load and store the stored application from the main memory in response to operation of a signal processor, a second ancillary memory configured to, in response to the signal processor operating, temporarily store the signal-processed image content, and in response to the signal processor not operating, load and store the stored application from the main memory, and a controller configured to, in response to receiving an execution request with respect to the application for reproducing the image content, and the signal processor not operating, load and store the stored application from the main memory into the second ancillary memory based on the setting information corresponding to the application stored in the main memory, and execute the stored application. | 10-22-2015 |
20150310803 | DISPLAY DEVICE - The rate of reading from a memory for storing display irregularity correction data is lowered. At the time of display, calculation is carried out in a correction calculation section using an input signal and correction data in one or more memory units, and brightness inconsistency correction is carried out. The way in which correction calculation is carried out in the correction calculation section is changed for every frame. | 10-29-2015 |
20150356953 | DISPLAY CONTROLLER - A display controller comprises an input stage | 12-10-2015 |
20150379684 | TEXTURE PIPELINE WITH ONLINE VARIABLE RATE DICTIONARY COMPRESSION - A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data. | 12-31-2015 |
20160012565 | Secure Rendering of Display Surfaces | 01-14-2016 |
20160049137 | SYSTEM AND METHOD FOR DYNAMIC VIDEO MODE SWITCHING - The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. However, the video output system must often compete with other memory users in order to access a frame buffer in a shared memory system. When memory bandwidth resources are limited, the performance of a computer system will suffer. To reduce the performance drop, a dynamic color mode switching system has been introduced. The dynamic color mode switching system detects when memory bandwidth resources are limited and then instructs the video output system to switch to a color mode that reduces the amount of reads from the memory system without any user intervention. | 02-18-2016 |
20160055616 | Display apparatus and method for driving the same - A display apparatus according to the present invention includes: N driver ICs (first to third driver ICs); N or more bidirectional memories (first to third bidirectional memories) that simultaneously allow data writing and data reading; a phase locked loop that converts an input clock to an output clock; a write controller that writes data to the plurality of bidirectional memories in synchronization with the input clock; and a read controller that reads the data from the plurality of bidirectional memories and causes the data to be output to the plurality of driver ICs in synchronization with the output clock. A frequency of the output clock is smaller than a frequency of the input clock and is larger than 1/N times the frequency of the input clock. | 02-25-2016 |
20160063967 | MEASURING DEVICE WITH A DISPLAY MEMORY HAVING MEMORY CELLS WITH A REDUCED NUMBER OF BITS AND A CORRESPONDING METHOD - A method for reducing a number of bits used for a frequency value of a measuring signal stored in each memory cell of a display memory in a measuring device determines the frequency value in each memory cell by assigning the frequency of sampled values in several measuring portions of a measured signal within an update cycle of the display to a corresponding memory cell. It then displays each pixel of the display with a brightness or a color corresponding to the frequency value in the corresponding memory cell after each update cycle. The determined frequency value is a sum of a first frequency value, which is determined in a number of first measuring portions of the measured signal within the update cycle, and at least one compressed second frequency value, which is determined by compression of a corresponding compressed second frequency value with a compression factor. Each uncompressed second frequency value can be determined in a corresponding part of a number of second measuring portions of the measured signal within the update cycle. | 03-03-2016 |
20160071495 | DISPLAY CONTROLLER DEVICE HAVING A DEBUG INTERFACE - A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image. | 03-10-2016 |
20160078587 | SYSTEM-ON-CHIP (SOC) DEVICES, DISPLAY DRIVERS AND SOC SYSTEMS INCLUDING THE SAME - A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt. | 03-17-2016 |
20160093014 | DATA ALIGNMENT AND FORMATTING FOR GRAPHICS PROCESSING UNIT - A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data to a second plurality of data lines dependent upon the control information. A storage array may include multiple storage units, and each storage unit may be configured to receive data from one or more data lines of either the first or second plurality of data lines dependent upon the control information. | 03-31-2016 |
20160098813 | TRANSPARENT PIXEL FORMAT CONVERTER - A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor. | 04-07-2016 |
20160118024 | CACHE MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A cache memory apparatus including a cache memory including a bank, a partition configuration unit configured to divide the cache memory into partitions by allocating the bank to a texture among textures for rendering, and a controller configured to receive a partition ID, of texture data requested by a device that performs the rendering, determine whether the requested texture data is stored in a partition corresponding to the partition ID among the plurality of partitions, and output the requested texture data to the device based on a result of the determination. | 04-28-2016 |
20160125568 | MANAGEMENT OF MEMORY FOR STORING DISPLAY DATA - A method, at a display control device ( | 05-05-2016 |
20160133232 | Image processing method and display apparatus - A method and an apparatus for processing an image are provided. A buffer is provided and separated into a series of storage units. Each storage unit has a fixed size. The image is divided into pixel groups, and each pixel group corresponds to one storage unit. Each pixel group is compressed by one of candidate compression methods to obtain compressed data so that the compressed data of each pixel group fits the corresponding storage unit. | 05-12-2016 |
20160148339 | APPARATUS AND METHOD FOR EFFICIENT FRAME-TO-FRAME COHERENCY EXPLOITATION FOR SORT-LAST ARCHITECTURES - An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame. | 05-26-2016 |
20160163020 | IMAGE PROCESSOR, METHOD OF OPERATING THE SAME, AND APPLICATION PROCESSOR INCLUDING THE SAME - An image processor, an application processor, a method of operating an image processor, and a chips set of an image processor are provided. The image processor includes a scaler configured to perform scaling on an input image and generate a scaled input image; and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal. The application processor includes a memory configured to store an input image; and an image processor configured to scale the input image, wherein the image processor comprises a scaler configured to perform scaling on the input image and generate a scaled input image and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal. | 06-09-2016 |
20160171645 | DISPLAY CONTROLLER AND A METHOD THEREOF | 06-16-2016 |
20160180821 | DISTRIBUTED MEMORY PANEL | 06-23-2016 |
20170236496 | VEHICULAR DISPLAY DEVICE | 08-17-2017 |