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Graphic display memory controller

Subclass of:

345 - Computer graphics processing and selective visual display systems

345530000 - COMPUTER GRAPHICS DISPLAY MEMORY SYSTEM

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
345534000 Memory access timing signals 12
345532000 Plural memory controllers 5
20110032261METHOD OF IMPLEMENTING AN ACCELERATED GRAPHICS PORT FOR A MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM - An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.02-10-2011
20110074799SCAN-TYPE DISPLAY DEVICE CONTROL CIRCUIT - A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data.03-31-2011
20120162237Bundle-Based CPU/GPU Memory Controller Coordination Mechanism - A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.06-28-2012
20120075318DISPLAY DEVICE AND METHOD FOR TRANSFERRING IMAGE DATA - For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU 03-29-2012
20080198170SYSTEM AND METHOD FOR DMA CONTROLLED IMAGE PROCESSING - A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data.08-21-2008
345533000 Using different access modes 4
20090251475FRAMEWORK TO INTEGRATE AND ABSTRACT PROCESSING OF MULTIPLE HARDWARE DOMAINS, DATA TYPES AND FORMAT - A portable development and execution framework for processing media objects. The framework involves: accepting an instruction to perform a media processing function; accepting a media object to be associated with the media processing function; wrapping the media object with an attribute that specifies a type and format of the media object, and a hardware domain associated with the media object; and causing an execution domain to perform the media processing function on the media object. The instruction to perform the media processing function is expressed in a form that is independent of the hardware domain associated with the media object, and may also be independent of the type and format of the media object. The media object may be an image, and the media processing function may include an image processing function performed on a GPU.10-08-2009
20090079749EMITTING RASTER AND VECTOR CONTENT FROM A SINGLE SOFTWARE COMPONENT - Technologies are described herein for emitting raster and vector content from a single software component. An application program maintains an in-memory representation of a document in an intermediate format. When the application program needs to render the document, it determines whether the target device is a raster or a vector device. The application program then utilizes a single software component to render the document for the target device. The application program provides an instruction to the software component as to whether the in-memory representation should be rendered as vector content or as raster content. In response to receiving the instruction, the software component retrieves the in-memory representation and renders it according to the instruction received from the application program. The rendered content is then provided to the target device.03-26-2009
20080309673RASTERIZING DEVICE - A rasterizing device is provided with a first storage area capable of storing a downloaded DL object, and a rasterizer that creates bit-mapped data in band units by rasterizing data. With respect to a predetermined band in which a predetermined DL object is to be included, the rasterizer performs following processes:12-18-2008
20090244078METHOD AND APPARATUS FOR OBTAINING IMAGES BY RASTER SCANNING CHARGED PARTICLE BEAM OVER PATTERNED SUBSTRATE ON A CONTINUOUS MODE STAGE - A method of raster scanning a sample on a continuously moving stage for charged-particle beam imaging said sample is disclosed. The method includes line scanning a charged-particle beam across a surface of the sample repeatedly to form on the surface at least one 2-dimensional line array composed of scan lines lying adjacent to each other. When each line scan is to be performed, the charged-particle beam is shifted, along the stage-moving direction, by an extra predefined distance at least equal to a distance the stage has traveled during a time period from the beginning of the first line scan of the first formed line array to the beginning of the current line scan (to be performed) of the current line array (to be formed).10-01-2009
345535000 Memory arbitration 2
20110187729MEMORY ACCESS METHOD AND ACCESS CONTROLLER FOR A MEMORY - An access method and an access controller for a memory are described. The method includes the following steps: monitoring an actual value of a relevant parameter of a display bandwidth of data to be output by the memory; comparing the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets requirements; and selecting an access arbitration mode for the memory according to whether the requirements are met. The access controller includes: a monitoring and comparing unit, adapted to monitor an actual value of a relevant parameter of a display bandwidth of data to be output by the memory and compare the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets requirements; and an arbitration adjusting unit, adapted to select an access arbitration mode for the memory according to whether the requirements are met. Thus, it is ensured that the display image misalignment does not exist in a display system, and memory access power consumption of the display system is reduced.08-04-2011
20080252649Self-Automating Bandwidth Priority Memory Controller - A memory controller that includes a write first in first out (FIFO) region of the memory for receiving pixel data and a read FIFO region of the memory for accessing the pixel data received through the write FIFO is provided. The memory controller is configured to rearrange the pixel data received by the write FIFO for storage in the memory by writing data representing a first pixel and a second pixel across a plurality of registers in the memory, wherein corresponding bit locations for the data representing the first pixel and the data representing the second pixel are stored within a same one of the plurality of registers. The memory controller is configured to grant access to one of multiple requests for access to the memory based on corresponding bit locations associated with the multiple requests. A graphics controller and a method for prioritizing access to a memory are provided.10-16-2008
Entries
DocumentTitleDate
20120169751DISPLAY APPARATUS AND DISPLAY APPARATUS DRIVING METHOD - In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t07-05-2012
20080259088Display device - Disclosed herein is a display device in which input data is written to a RAM as current frame data and read from the RAM as preceding frame data. Then, the current frame data and the preceding frame data are added up in a correction circuit and the result is subjected to an overdriving processing. After this, the processed (over-driven) data is assumed as current frame corrected data, which is then written to the RAM. The written corrected data is read from the RAM and subjected to a double-speed driving processing.10-23-2008
20130033510Techniques for Controlling Power Consumption of a System - A chipset can detect whether a relevant portion of the system frame buffer has been updated and can send an interrupt to the display driver to invoke a registered hardware watchpoint routine to inform display driver of the updating. If the display is currently in display self refresh (DSR) state, display driver wakes up display controller components and requests to transmit a MIPI compatible DCS command to request copying of the updated data from system frame buffer into an on-panel frame buffer or a frame buffer associated with the display. The display driver can power-down graphics system components and enter DSR state again to save power.02-07-2013
20130069965TWO DIMENSIONAL MEMORY ACCESS CONTROLLER - A memory control device derives a two dimensional location on a graphic display surface from address signals of a graphics processing unit (GPU). The memory controller compares the derived two dimensional location to a two dimensional range of authorized locations corresponding to a subset of the display surface. The memory controller modifies the address signals of the graphics processing unit (GPU) if the address signals do not fall within the two-dimensional range of authorized locations corresponding to a subset of the display surface, and propagates the address signals unmodified to a display memory otherwise.03-21-2013
20090237412Data display system, data relay device, data relay method, data system, sink device, and data read method - A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.09-24-2009
20120229483PANEL DRIVING DEVICE AND DISPLAY DEVICE HAVING THE SAME - A panel driving device for driving a display panel including N data lines is disclosed. The panel driving device includes a memory array and a source driver. The memory array includes M memory blocks, a controller and an output unit. Each memory block includes N memory units. The controller is configured to divide serial image data into M groups of sub-image data and write each group of sub-image data into the corresponding memory block sequentially, wherein each group of sub-image data has N sub-image data. The output unit is configured to output the data in the M memory blocks sequentially in a time division manner in response to a selection signal. The source driver includes N driving units having the same configuration. After the driving unit receives the time-divided data output from the output unit, signal processing is performed to generate an image signal to be output to the corresponding data line.09-13-2012
20120236015IMAGE DISPLAY SYSTEMS AND METHODS OF PROCESSING IMAGE DATA - Image display systems include a first memory, a memory controller and a device driver. The controller is configured to generate an interrupt signal in response to a command to write first image data into a first range of addresses within the first memory, which at least partially overlaps with a reference range of addresses. The device driver is configured to read the first image data from the first memory in response to the interrupt signal.09-20-2012
20110298814SWITCHING VIDEO STREAMS FOR A DISPLAY WITHOUT A VISIBLE INTERRUPTION - The disclosed embodiments provide a system that facilitates driving a display in a computer system. During operation, the system receives an input video stream from a graphics source, wherein the input video stream comprises a sequence of video frames. Next, the system directs the input video stream through a set of two or more memory buffers including a front buffer and a back buffer to produce an output video stream, which is used to drive the display. While directing the input video stream through the set of memory buffers, the system writes a video frame from the input video stream into the back buffer, and concurrently drives the output video stream from a preceding video frame in the front buffer. When the writing of the video frame completes, the system switches buffers so that the back buffer becomes the front buffer, which drives the output video stream, and the front buffer becomes either a spare buffer or the back buffer, which receives a subsequent frame from the input video stream.12-08-2011
20090002383MEMORY FOR PROVIDING A GRAPHIC CONTENT - A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.01-01-2009
20090153574METHOD AND SYSTEM FOR UPDATING FIRMWARE - A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I06-18-2009
20110242121SLIDE PREPARATION - Presenting a slide. Anticipating a slide to be selected for display. Receiving data of the anticipated slide in an unconstructed format. Constructing the anticipated slide from the received data. Caching the constructed slide. Pre-drawing the constructed slide in construction memory. Receiving instructions to display a slide. In the event that the instructed slide is the cached and pre-drawn slide, rendering the pre-drawn slide to display memory.10-06-2011
20090309889Method and Apparatus for Contolling Writing of Data to Graphic Memory - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space.12-17-2009
20120293525INTEGRATED CIRCUIT DESIGN METHOD FOR IMPROVED TESTABILITY - A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing.11-22-2012
20130021354METHOD AND SYSTEM FOR DISPLAYING USING BUFFER SWAPPING - Methods and systems which may implement buffer swapping are provided. The methods include rendering, onto screen locations of a display screen, data from a memory having a first buffer and a second buffer, each buffer having respective buffer memory locations which correspond to the screen locations of the display screen. The methods can include: rendering first data from the first buffer onto the display screen; writing, to the second buffer, second data based on at least some of the first data from the first buffer by performing at least one of transforming at least some first data and changing corresponding screen locations of at least some first data from the first buffer, by writing at most once to each buffer memory location of the second buffer; and rendering the second data from the second buffer onto the display screen.01-24-2013
20090091580Integrated circuit device and electronic instrument - An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.04-09-2009
20090295813Integrated circuit design method for improved testability - A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing.12-03-2009
20100201697Die Customization using Programmable Resistance Memory Elements - A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.08-12-2010
20080303836VIDEO DISPLAY DRIVER WITH PARTIAL MEMORY CONTROL - Partial memory control for a video display driver in which data storage is provided for storing and providing a plurality of video pixel data having selectable ones of a plurality of pixel color depths to be displayed by a plurality of video displays having a plurality of mutually distinct dimensions.12-11-2008
20130215130DISPLAY APPARATUS AND DISPLAY CONTROL METHOD - A rendering control unit determines movie and graphic display modes with reference to a rendering processing command, and acquires maximum speed information indicating the maximum value of a read/write speed allowed for a memory. The rendering control unit decides a speed to be distributed to a read/write speed of the movie data and a speed to be distributed to a read/write speed of the graphic data with respect to the memory, of a maximum speed indicated by the maximum speed information, based on the determination result. The rendering control unit controls a read/write access of an image with respect to the memory based on the rendering processing command, in accordance with the decided speeds.08-22-2013
20130120419Memory Controller for Video Analytics and Encoding - Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.05-16-2013
20110267361SCANNING IMAGE DISPLAY APPARATUS - A scanning image display apparatus includes a light source unit (11-03-2011
20090160868INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a connector, a graphics controller, a management controller, and a power supply control module. The graphics controller controls output of video signals and audio signals from the connector. The management controller inputs/outputs the various commands via the connector. The power supply control module supplies power for operation to both of the graphics controller and the management controller during a power-off state, and supplies power for operation only to the management controller in a power-on state. Both of the graphics controller and the management controller include a function of acquiring identification information of the connection destination by means of the signal line. And, the management controller deactivates the function of acquiring identification information of the connection destination by means of the signal line during a power-on state.06-25-2009
20120069034QoS-aware scheduling - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.03-22-2012
20090201305ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY - An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.08-13-2009
20090096799DISPLAY APPARATUS - A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.04-16-2009
20090096800DISPLAY APPARATUS - A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.04-16-2009
20090244077SEMICONDUCTOR MEMORY DEVICE, IMAGE PROCESSING SYSTEM, AND IMAGE PROCESSING METHOD - A semiconductor memory device comprises: a memory cell group, the memory cell including a number of which is 2n, the n being a positive integer; and a first decoder provided with respect to each of the memory cell groups and a second decoder. The first decoder activates a word line by the memory cell group based upon a first address and an n bit in a second address and the second decoder activates a bit line based upon the second address.10-01-2009
20090315904Information Processing Apparatus - An information processing apparatus including: a display section; a memory section which memorizes a display configuration for displaying each processing condition of a job on the display section, the display configuration having been selected from a plurality of display configuration types and set by being correlated with the each processing condition; and a control section which controls to display a plurality of processing conditions on the display section by utilizing the display configuration having been correlated with the each processing condition and memorized in the memory section.12-24-2009
20090115790DISPLAY CONTROL DEVICE AND MOBILE ELECTRONIC APPARATUS - A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc.05-07-2009
20090115789METHODS, SYSTEMS AND APPARATUS FOR MAXIMUM FRAME SIZE - Apparatus, methods, and systems are disclosed for capturing video frames. The system determines a maximum memory size available for video capture. The system initiates video capture and acquires a frame. The system then analyzes the incoming frame and determines if the frame is larger than the maximum memory size. If the frame is larger than the maximum memory size and if a quality parameter is greater than zero, the quality parameter is lowered.05-07-2009
20090079748Apparatus, System, and Method For Graphics Memory Hub - A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.03-26-2009
20100177106ARBITRATION CIRCUIT TO ARBITRATE CONFLICT BETWEEN READ/WRITE COMMAND AND SCAN COMMAND AND DISPLAY DRIVER INTEGRATED CIRCUIT HAVING THE SAME - An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation.07-15-2010
20100188411Non-Graphics Use of Graphics Memory - Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.07-29-2010
20100295859VIRTUALIZATION OF GRAPHICS RESOURCES AND THREAD BLOCKING - Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.11-25-2010
20100207952MAGNETIC MEMORY DISPLAY DRIVER SYSTEM - In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.08-19-2010
20130127884DISPLAY CONTROL APPARATUS, DISPLAY CONTROL METHOD, AND PROGRAM - The present technology relates to a display control apparatus, a display control method and a program which can suppress, for example, distortion of an image caused when an image transmitted from a data transmission channel is displayed with a little delay. A write information measurement unit measures a write preparation time required to start writing a received image in a display buffer which temporarily holds the image, a write control unit controls the writing of the image according to whether or not the write preparation time is a threshold time or more which represents a write preparation time at which the writing of the image is finished at a display end time at which the image is displayed in synchronization with a display timing at which the image needs to be displayed, and a display control unit displays the image written in the display buffer under control of the write control unit in synchronization with the display timing by a write time at which the image can be displayed in synchronization with the display timing. The present technology is applicable to, for example, a display apparatus which displays image data to be transmitted with a little delay.05-23-2013
20100328329APPARATUS AND METHOD FOR PROCESSING DATA - Incoming video data is processed. According to an example embodiment, video data as presented in rows of pixels is stored in terms of blocks of pixels of corresponding images making up the video. When a particular pixel is read from memory, the block of pixels is retrieved (e.g., with a single read), facilitating (simultaneous) access to pixels in adjacent rows or columns, without necessarily accessing entire rows and columns to do so.12-30-2010
20110025699INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes a first pad group connected to a first memory pad group arranged along a first chip side of a chip of an image memory stacked on the integrated circuit device, a second pad group connected to a second memory pad group arranged along a third chip side, a control section which controls display of an electro-optical device, and a third pad group from which a data signal and a control signal for display control. The first pad group is arranged along a first side of the integrated circuit device, wherein the second pad group is arranged along a third side facing the first side, and wherein the third pad group is arranged along a second side which intersects with the first side and the third side.02-03-2011
20090066707SOURCE DRIVER FOR IMAGE SCROLLING - A source driver comprising a frame memory, a first line buffer, and a second line buffer. The frame memory stores bits of pixel values of an image. The first line buffer then sequentially latches the bits of the pixel values from the frame memory with a first address index. The second line buffer then sequentially latch the bits of the pixel values from the first line buffer with a second address index, which is different from the first address index, and writes the bits of the pixel values back to the frame memory, such that the image is scrolled. The present invention also provides a method of refreshing the frame memory in a source driver.03-12-2009
20090066708Hands-free, user-formatted instruction display system - An instruction display system includes memory for storing instruction information in a format specified by the user, a display, and a hands-free user-controlled processor. Hands-free user inputs define selected portions of the stored instruction information that are to be displayed. The memory, display and processor are coupled to the user by a mounting assembly that allows the user to readily view the display for a particular activity.03-12-2009
20110115803INTEGRATED CIRCUIT DEVICE AND ELECTRONIC DEVICE - An integrated circuit device includes: a memory controller; and a read-modify-write circuit, when the number of bits of each pixel of a first image data is N (N is a natural number), the number of rewrite unit bits of the first image data is M (M is a natural number of M≧N), and the number of bits for which the memory controller can access a image memory at one time is L (L is a natural number of two or more that fulfills L>M), the read-modify-write circuit rewrites pixel data of the first image data corresponding to active write enable signals, among L/M (L and M are each a natural number multiple of N) of write enable signals corresponding to the L bits, into corresponding pixel data of the second image data.05-19-2011
20110063314DISPLAY CONTROLLER SYSTEM - A display controller system with a memory controller and buffers is described. The system enables transferring data from the main memory of the CPU to the image memory without interfering the image updating. As a result, the present invention may allow continuously updating the display image and continuously writing new image data from CPU to the image memory which improves overall system performance.03-17-2011
20110063313MEMORY COHERENCY IN GRAPHICS COMMAND STREAMS AND SHADERS - One embodiment of the present invention sets forth a technique for performing a computer-implemented method that controls memory access operations. A stream of graphics commands includes at least one memory barrier command. Each memory barrier command in the stream of graphics command delays memory access operations scheduled for any command specified after the memory barrier command until all memory access operations scheduled for commands specified prior to the memory barrier command have completely executed.03-17-2011
20100053181METHOD AND DEVICE OF PROCESSING VIDEO - A memory controller is disclosed that allocates local memory space to a set of macroblocks of a picture being processed. Information associated with a specific macroblock of the set of macroblocks is written to non-local memory when it is no longer needed to complete processing of a current row of macroblocks. When information associated with the specific macroblock is later needed to process a different row of macroblocks, the memory controller allocates local memory space to the specific macroblock and stores the previously saved information from non-local memory to the local memory.03-04-2010
20100053180METHOD AND SYSTEM FOR CRYPTOGRAPHICALLY SECURING A GRAPHICS SYSTEM - A system and method for cryptographically securing a graphics system connectable via an external bus to a computing system, the graphics system including a graphics processor, a video memory and a memory controller for controlling the flow of data to and from the video memory. The graphics system further includes a copy engine for copying data between a system memory of the computing system and the video memory, where this copy engine acts independently of the graphics processor of the graphics system. The present invention enables the copy engine of the graphics system to decrypt encrypted data in the course of copying data from the system memory to the video memory and to encrypt unencrypted data in the course of copying data from the video memory to the system memory. Thus, cryptographic protection of secure content may be assured by the graphics system without the excessive usage of its primary resources for this non-graphical purpose.03-04-2010
20090027408DISPLAY APPARATUS, CONTROL METHOD THEREOF AND DISPLAY SYSTEM HAVING THE SAME - A display apparatus, a control method thereof and a display system having the same are provided. The display apparatus includes: a communication unit; a memory in which the same data as that of an external display apparatus is loaded in the same reference address as that of the external display apparatus; and a controller which controls to change data loaded in a reference address corresponding to address information from the external display apparatus based on data change information from the external display apparatus and to display the changed data if the address information and the data change information are received from the external display apparatus via the communication unit.01-29-2009
20120274647PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES - This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.11-01-2012
20110148891Method and Apparatus for Frame Buffer Management - Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively.06-23-2011
20100118040METHOD, SYSTEM AND COMPUTER-READABLE RECORDING MEDIUM FOR PROVIDING IMAGE DATA - The present disclosure relates to a method, system and computer-readable medium for providing image data. According to an exemplary embodiment, a method of providing image data includes storing a particular region on image data in association with a keyword, comparing conditional information with the keyword associated with the particular region, when receiving the conditional information from a user terminal unit, and controlling a display state of the image data to allow the particular region to be displayed on a screen of the user terminal unit. When a user inputs a keyword including content relating to a geographical feature or object, an actual shape of the geographical feature or object can be displayed on a screen of the user terminal unit.05-13-2010
20110037770Memory Address Re-mapping of Graphics Data - A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.02-17-2011
20100321397Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System - In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.12-23-2010
20080252648Method And Apparatus For Providing Bandwidth Priority - A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.10-16-2008
20080204464Image display system and method for preventing image tearing effect - An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation. If the writing and reading addresses are the same or if a difference between the start addresses for the writing and reading operations is less than the burst length, the tearing-protection bus arbiter outputs the reading address to the memory controller and holds the writing address.08-28-2008
2011026106410T SRAM FOR GRAPHICS PROCESSING - A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value.10-27-2011
20110134133IMAGE PROCESSING DEVICE - Provided is an image processing device with which processing performance can be improved at low cost. The image processing device (06-09-2011
20100026693DISPLAY DEVICE AND METHOD FOR UPDATING DATA IN DISPLAY DEVICE - Provided is an image display device. The image display device includes an interface, a memory, a controller, and a display unit. The interface supports communication with an external storage medium, and the memory stores data transmitted through the interface. The controller compares attribute information of data stored in the memory with that of data stored in the external storage medium when the external storage medium is connected through the interface and controls changing of a data name of data stored in the memory or a data name of data stored in the external storage medium depending on whether the attribute information is identical. The display unit displays whether a data name is changed in response to a control signal from the controller.02-04-2010
20110018885METHOD AND APPARATUS FOR MIRRORING FRAME - A method and an apparatus for mirroring a frame are provided. The method is suitable for a display device having a first storage unit and a second storage unit. In the present method, pixel values of a pixel row of the frame are read from the first storage unit and written into the second storage unit. Then, the pixel values of the pixel row of the frame are read from the second storage unit and written back to the first storage unit. When performing one of foregoing reading and writing steps, the pixel values of the pixel row are read or written in a reverse direction to mirror the pixel row. Finally, foregoing steps are repeated to mirror each pixel row of the frame, so as to mirror the entire frame.01-27-2011
20110050714Image processing device and imaging apparatus - An image processing device includes a memory interface to read out image data from a memory, and a memory access controller to control reading process of the memory interface so as to keep a number of pixels in a main scanning direction of the image data read out from the memory smaller than a number of pixels in a main scanning direction of a screen to which the image data is output.03-03-2011
20120098843APPARATUS FOR CONTROLLING MEMORY DEVICE AND RELATED METHOD - A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units.04-26-2012
20120007872Method And Computer Program For Operation Of A Multi-Buffer Graphics Memory Refresh, Multi-Buffer Graphics Memory Arrangement And Communication Apparatus - A method for refresh operation of a multi-buffer arrangement for a graphics memory having a first and a second operation mode is disclosed. The method comprises writing information to one of a first and second buffers of the multi-buffer arrangement; presetting the one of the buffers, when previous refresh operation was in the second operation mode, before the writing of information to the one of the buffers; dynamically selecting one of the first and the second operation mode; copying information, when in the first operation mode, between a first and a second buffer of the multi-buffer arrangement, before the writing of information to the one of the buffers; and providing information from the buffer arrangement to a display. Computer programs, multi-buffer arrangements and communication apparatuses comprising such multi-buffer arrangements are also disclosed.01-12-2012
20120013629Reading Compressed Anti-Aliased Images - Embodiments of the present invention enable the reduction of the memory bandwidth required for graphics rendering. According to an embodiment, a method to render a pixel from a compressed anti-aliased image includes: accessing metadata for the pixel, where the metadata includes entries for respective samples generated by multisampling the pixel; and retrieving a subset of said samples based upon the metadata, wherein the subset is stored in the compressed anti-aliased image stored in a memory.01-19-2012
20120013628INFORMATION PROCESSING APPARATUS, SCREEN DISPLAY CONTROL METHOD AND PROGRAM - An information processing apparatus includes memories 01-19-2012
20090135192PROGRAMMABLE DATA PROCESSING CIRCUIT - A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (05-28-2009
20110080419Methods of and apparatus for controlling the reading of arrays of data from memory - A display controller reads blocks of data from a frame buffer and stores them in a local memory buffer of the display controller before outputting the blocks of data to a display. The display controller uses similarity meta-data associated with the output frame in the frame buffer to determine whether a new block of data to be processed for display is similar to a block of data already stored in the local memory of the display controller or not. If it is determined that the data block to be processed is similar to a data block already stored in the local buffer of the display controller, the display controller does not read a new data block from the frame buffer but instead provides the existing data block in its buffer to the display.04-07-2011
20110102444INFORMATION DISPLAY DEVICE AND INFORMATION DISPLAY METHOD - The digital photo frame (05-05-2011
20120127185SYSTEM AND METHOD FOR AN OPTIMIZED ON-THE-FLY TABLE CREATION ALGORITHM - A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.05-24-2012
20120127186DISPLAY CONTROL APPARATUS, DISPLAY CONTROL METHOD, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM AND INTEGRATED CIRCUIT - A display control apparatus includes: an updating frequency calculator (05-24-2012
20120169750DISPLAY DEVICE AND DRIVE METHOD FOR DISPLAY DEVICE - Provided are a memory-type display device capable of improving image quality during a normal mode and a method for driving such a display device. Each memory circuit (MR07-05-2012
20100171747DDC COMMUNICATION MODULE - Provided is a display data channel (DDC) communication module reading and storing extended display identification data (EDID) of a display device and providing the stored EDID to a host device. The DDC communication module includes: a serial electrically erasable and programmable read only memory (EEPFROM) in which the EDID is stored; a comparator outputting logic data indicating that the comparator is connected to the display device or the host device; and a controller reading and storing EDID, or providing EDID stored in the serial EEPROM to the host device, according to the logic data output from the comparator.07-08-2010
20120176388LIQUID CRYSTAL DISPLAY DEVICE AND DRIVE METHOD THEREFOR - In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t07-12-2012
20100271378Rapid Activation Of A Device Having An Electrophoretic Display - A method for booting up a system includes detecting a reset condition, and in response to detecting the reset condition, driving a display device having display pixels that have multiple stable states with a reset drive scheme. The reset drive scheme is used to drive the display pixels to a known display state. The driving of the display device may be performed by a display controller. In addition, initialization instructions are executed to place at least one component of the system in an active state. The executing of initialization instructions may be performed by a host. The driving of the display device with the reset drive scheme and the executing of the initialization instructions are performed in parallel. The method may include driving the display device with a first drive scheme to display an initial start-up screen in parallel with the executing of the initialization instructions.10-28-2010
20100271377Electrophoretic Display Controller Providing PIP And Cursor Support - Data pixels defining first and second images are stored in first and second image buffers, respectively. A second image coordinate location within a display matrix of a display device having display pixels that have multiple stable states is stored in a memory. Data pixels of the first image are read from the first image buffer. If a data pixel read from the first image buffer is within the second image coordinate location, a data pixel from the second image buffer corresponding with the data pixel read from the first image buffer is read, and the data pixel read from the second image buffer is combined with the corresponding data pixel read from the first image buffer to generate a derived data pixel. Synthesized pixels corresponding with at least each of the data pixels of the second image are generated. The synthesized pixels respectively include the derived data pixels.10-28-2010
20120249565SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING METHOD, AND DISPLAY APPARATUS - A signal processing circuit includes: a memory storing an image signal; a write control unit generating a write control signal in synchronization with the input image signal and frame identification information, and storing the input image signal in the memory so that the input image signal corresponds to the frame identification information on the basis of the write control signal; and a read control unit generating a read control signal through obtaining a vertical synchronization signal supplied from outside based on a timing signal of an output horizontal frequency, and reading an image signal that corresponds to the frame identification information from the memory on the basis of the read control signal and the frame identification information supplied from outside.10-04-2012
20120256933FLOATING POINT COMPUTER SYSTEM WITH FLOATING POINT MEMORY - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.10-11-2012
20120256932FLOATING POINT COMPUTER SYSTEM ON A SINGLE CHIP - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.10-11-2012
20120327096IMAGE GENERATING DEVICE - There is provided with an image generating device in which the selecting unit selects a first buffer from frame buffers, the storage stores identification information of a frame buffer storing a latest image on an area-basis, the drawing unit draws and writes image data in the first buffer and specifies an update area including a written area, the updating unit updates the identification information to show that a latest image of the written area is stored i n the first b uffer, the modifying unit specifies an area storing an image that is not the latest in the update area and reads latest image data relating to the area from another frame buffer storing the latest image, and writes it in the area of the first buffer, the image generating unit reads image data of the update area in the first buffer, the communication unit transmits it to the display terminal.12-27-2012
20120081379IMAGE DISPLAY SYSTEM - A method of storing an image on a storage device in a tiled format is provided. The method includes formatting the storage device to include a block size such that a tile size is an integer multiple of the block size, and the tile size corresponds to a display output. The method further includes reading pixel data of a source image; and generating, from the read pixel data, a first tile and a second tile. The first tile and the second tile each have overlapping portions that overlap by an adjustable amount, and the overlapping portions include substantially identical pixel data. The method also includes storing the first tile and the second tile on the storage device; and repeating the reading, generating, and storing a plurality of times to store the image. The image is stored on the storage device as a contiguous string of data.04-05-2012
20110122141MAP DATA RECORDING DEVICE, MAP DISPLAY, MAP DATA RECORDING METHOD, MAP DISPLAY METHOD, MAP DATA RECORDING PROGRAM, MAP DISPLAY PROGRAM, AND RECORDING MEDIUM - In a map data recording device (05-26-2011
20100328330MEMORY CONTROLLER AND MEMORY SYSTEM USING THE SAME - According to an aspect of embodiment, a memory controller for controlling a memory having areas of data unit of K bits, includes a data mapping unit dividing N bits of data, where N is not a multiple of K, into K bits and (N−K) bits, and in regard to L pieces of the data, arranging L K-bit data into L data units, and arranging L (N−K)-bit data into M (M=L×(N−K)/K) data units by packing; and an access control unit access-controlling the memory to access the L K-bit data as L data units, and access-controlling the memory to access the packed L (N−K)-bit data as M data units.12-30-2010
20080291209Encoding Multi-media Signals - An aspect of the present invention mitigates bottlenecks in components such as buses in the path of a system memory and a GPU memory. In an embodiment, a graphics processing unit (GPU) receives digital values representing a multi-media signal from an external source, encodes the digital values, and stores the encoded values in a RAM. The RAM may also store instructions which are executed by a CPU. As the digital values are received by the GPU without being stored in the RAM, bottlenecks may be mitigated.11-27-2008
20120262467IMAGE PROCESSING APPARATUS THAT ENABLES TO REDUCE MEMORY CAPACITY AND MEMORY BANDWIDTH - An image processing apparatus includes a memory control circuit that stores pixel data in a frame memory, an image processing circuit that processes the pixel data stored in the frame memory, and an output circuit that outputs processed pixel data. The memory control circuit divides the pixel data into upper bit portions and lower bit portions, and a lower bit processing circuit stores the lower bit portions in the frame memory by one of (i) dividing lower bit portion of each of the pixel data into n unit portions and storing corresponding one of n unit portions in the frame memory during each of n successive frame periods, and (ii) dividing pixels constituting each of the frames into n groups and storing the lower bit portions of the pixel data of pixels in corresponding one of n groups in the frame memory during each of n successive frame periods.10-18-2012
20120320072Data Access Method and Electronic Apparatus for Accessing Data - A data access method applicable to a storage apparatus for reducing or eliminating an image tearing effect includes defining at least one write check point; comparing an actual write speed for writing data into the storage apparatus with a predetermined write speed at the write check point; and adjusting the actual write speed when a difference between the actual write speed and the predetermined write speed is larger than a predetermined value, for adaptively reducing the difference to be smaller than or equal to the predetermined value.12-20-2012
20120139931DISPLAY SYSTEM HAVING FLOATING POINT RASTERIZATION AND FLOATING POINT FRAMEBUFFERING - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.06-07-2012
20110157198Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.06-30-2011
20130021355METHOD AND SYSTEM FOR DISPLAYING PROIRITIZED LIVE THUMBNAIL OF PROCESS GRAPHIC VIEWS - The system for displaying prioritized live thumbnail of process graphic views includes at least one real time data source 01-24-2013
20130169655ELECTRONIC SYSTEM, CONTROL METHOD THEREOF, DISPLAY APPARATUS, UPGRADE APPARATUS, AND DATA INPUT/OUTPUT PROCESSING METHOD OF DISPLAY APPARATUS - An electronic system, a control method for the electronic system, a display apparatus, an upgrade apparatus, and a data input/output processing method of the display apparatus are provided. The electronic system includes a first system on chip (SOC) including a first functional block which performs a first function, a second functional block which performs a second function, and a first bus network which performs communication between the first functional block and the second functional block, a connection unit which connects a second SOC to the first SOC, wherein the second SOC comprises a third functional block configured to upgrade the first function and a second bus network, and a power supply unit which supplies power to the first SOC and the second SOC, wherein the power supply unit blocks power from being supplied to the first functional block if the second SOC is connected to the connection unit.07-04-2013
20120249566FLOATING POINT COMPUTER SYSTEM WITH FRAME BUFFER FOR STORING COLOR VALUES DURING OR AFTER RASTERIZATION - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.10-04-2012
20130100148DISPLAY CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME - A display controller includes a graphic memory, a graphic memory control unit and a scan control unit. The graphic memory has a storage capacity defined by a first directional size multiplied by a second directional size. The graphic memory control unit converts two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, converts the 1-D addresses to physical 2-D addresses based on the first directional size and controls the graphic memory to store the input data. The display panel has a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel. The scan control unit increases scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.04-25-2013
20130100149Portable Digital Display - A portable digital display assembly is disclosed. The portable digital display device is configured to be operated by a wired or wireless device. The portable digital display is battery powered and has arrays of LED's configured to creating a display.04-25-2013
20110242120DISPLAY APPARATUS AND DRIVIING DEVICE FOR DISPLAYING - The display unit can reduce the electric power consumed by the process of calculating an adjustment coefficient for display data, as typified by gradient control, and it can be readily adapted even to a display panel with a higher resolution. The display unit includes: a plurality of driving units arrayed in parallel and each operable to output a drive signal to a display panel; a plurality of first calculation units, and a plurality of display RAMs, each paired with one first calculation unit, the pairs of the first calculation units and display RAMs laid out along a direction of the parallel array of the driving units; and a second calculation unit which distributes display data supplied from outside to the display RAMs, receives display data from the display RAMs in parallel to analyze a histogram of tone distribution of pixel data corresponding to one screen, and calculates the adjustment coefficient based on a result of the analysis. In the display unit, the adjustment coefficient thus calculated is sent back to the first calculation units. The first calculation unit performs a calculation using display data read from the corresponding display RAM and the adjustment coefficient thereby to create drive data for the display panel.10-06-2011
20130155084Virtualization of Graphics Resources and Thread Blocking - Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.06-20-2013
20120019545DISPLAY DEVICE AND IMAGE DISPLAY METHOD - An image display device of the present invention comprises a first determination section for monitoring information respectively appended to a plurality of images, and detecting information that has been appended to the most images among the plurality of images as first information, a second determination section for detecting information other than the first information, among the information that has been respectively appended to the plurality of images, as auxiliary information, and a third determination section for detecting an image to which the first information has been appended, and which is an image having the auxiliary information, as a priority image.01-26-2012
20120019544IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING THE SAME - An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory.01-26-2012
20130194285STORAGE APPARATUS AND METHOD OF CONTROLLING THE SAME - There is provided a storage apparatus for providing an effective memory addressing method. The storage apparatus includes at least one memory and at least one controller coupled to the at least one memory to provide address information. Each of the controllers includes a first controller for providing on/off information of subfields included in one frame for driving pixels in a display panel, a third controller for horizontal position information corresponding to a selected scan line from scan lines of a display panel, and a second controller for providing vertical position information corresponding to a pixel on the selected scan line. On/off information of subfields for at least two pixels is stored in a cell located at the vertical position and the horizontal position in the at least one memory.08-01-2013
20130207985IMAGE PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An image processing apparatus involving various settings, that allows a user to easily restore setting values after changing the setting values. Extracted difference in setting value indicating a difference between setting information at the time of execution of n−108-15-2013

Patent applications in class Graphic display memory controller

Patent applications in all subclasses Graphic display memory controller