Class / Patent application number | Description | Number of patent applications / Date published |
341156000 | Coarse and fine conversions | 47 |
20080258959 | Integrating/SAR ADC and method with low integrator swing and low complexity - A reconfigurable circuit ( | 10-23-2008 |
20090073018 | High Speed High Resolution ADC Using Successive Approximation Technique - An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal. | 03-19-2009 |
20090109079 | SUCCESSIVE APPROXIMATION ANAGLOG-TO-DIGITAL CONVERTER WITH INBUILT REDUNDANCY - The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial. The plurality of conversion engines operate in a second phase of the conversion by inputting the produced M threshold voltages into the associated inputs of the M comparators such that the plurality of conversion engines operate independently so that fewer bits are determined from the sampled signal during each successive approximation trial then were determined during the first phase. A result obtained from at least one of the plurality of conversion engines is then outputted. | 04-30-2009 |
20090184857 | A/D CONVERTING APPARATUS - An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit. | 07-23-2009 |
20090195432 | Systems and Methods for Analog to Digital Conversion - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide partially clocked, multi-step analog to digital converters. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range. The clock circuit selectably asserts one of the first clock and the second clock based at least in part on an output of the second conversion stage. | 08-06-2009 |
20090212985 | SOLID-STATE IMAGING DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SIGNAL PROCESSING METHOD - A solid-state imaging device includes: pixel circuits arranged in a matrix which perform photoelectric conversion on received light; and an AD conversion unit converting the resultant signal voltage of the photoelectric conversion. The AD conversion unit includes: a reference voltage generation unit generating plural reference voltages which are different from each other within a possible range for a signal voltage; a most significant bit conversion unit that identifies a voltage section including the signal voltage from among the voltage sections each having a corresponding one of the reference voltages as a base point and determines the identified result as the value of the most significant bit of the digital signal; and a least significant bit conversion unit that converts, into the least significant bit of the digital signal, the difference voltage between the signal voltage and the reference voltage as the base point of the identified voltage section. | 08-27-2009 |
20100026545 | RAMP-BASED ANALOG TO DIGITAL CONVERTERS - The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator ( | 02-04-2010 |
20100039306 | ANALOG-TO-DIGITAL CONVERTER - A method of analog-to-digital conversion over n bits of an analog signal, including the steps of: comparing the amplitude of the analog signal with a threshold representing the amplitude of the full-scale analog signal divided by 2 | 02-18-2010 |
20100073215 | UNIFIED ARCHITECTURE FOR FOLDING ADC - A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array ( | 03-25-2010 |
20100109927 | RESIDUE GENERATORS FOR REDUCTION OF CHARGE INJECTION IN PIPELINED CONVERTER SYSTEMS - Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity. | 05-06-2010 |
20100123611 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD OF DRIVING THE SAME - A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved. | 05-20-2010 |
20100149016 | Pulse delay circuit and A/D converter including same - The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof. | 06-17-2010 |
20100171645 | N-BIT ADC READER - An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input pin. A second register stores a second group of bits representing the equivalent resistance. The second group of bits comprises the most significant bits of the value associated with the resistor divider. | 07-08-2010 |
20100182183 | Reference Pre-Charging for Two-Step Subranging ADC Architecture - A coarse reference ladder provides a plurality of coarse references. A coarse ADC receives an input voltage. The coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output. A switch matrix is configured to close a switch based on the coarse output. An input line corresponding to a coarse reference is coupled to the switch matrix. The input line is precharged to the input voltage. The input line settles from the precharged input voltage to the coarse reference. A fine reference ladder provides a plurality of fine references based on the coarse reference. A fine ADC receives the input voltage and performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output. Logic outputs a digital output for the input voltage based on the coarse output and the fine output. | 07-22-2010 |
20100309038 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage. | 12-09-2010 |
20100315278 | MOST SIGNIFICANT BITS ANALOG TO DIGITAL CONVERTER, AND AN ANALOG TO DIGITAL CONVERTER INCLUDING A MOST SIGNIFICANT BITS ANALOG TO DIGITAL CONVERTER - A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion. | 12-16-2010 |
20110084866 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD THEREOF - The configuration of a successive approximation analog to digital converter (ADC) and a method thereof are provided in the present invention. The proposed configuration includes a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal outputting a comparison result, a most significant bit ADC coupled to the non-inverting input terminal, and a least significant bit ADC coupled to the inverting input terminal. | 04-14-2011 |
20110102229 | ANALOG-TO-DIGITAL CONVERTER ON TWO BITS WITH SUCCESSIVE APPROXIMATIONS - The analog-to-digital converter comprises a first stage in which a voltage to be converted is applied to the input of a first comparator. The first comparator delivers a first digital result representative of the comparison between the voltage to be converted and the reference voltage on a first digital output. The first digital output is connected to means for calculating a first intermediate voltage. A second comparator compares the first intermediate voltage with the reference voltage and delivers a second digital result on a second digital output terminal. The digital output terminal is connected to second means for calculating a residual voltage according to the voltage to be converted, the first and second voltages and the first and second digital results. | 05-05-2011 |
20110181454 | FOLDING ANALOG-TO-DIGITAL CONVERTER - A folding analog-to-digital converter (ADC) is disclosed. The folding ADC includes a reference voltage generating unit generating a plurality of reference voltages, a low power analog pre-processing unit including a plurality of folders, each of which compares a voltage level of an analog input signal with a corresponding reference voltage of the plurality of reference voltages to generate a pair of differential folded outputs, a comparison unit that compares outputs of the low power analog pre-processing unit to output a digital signal, and an encoding unit that converts an output of the comparison unit into a binary code signal. | 07-28-2011 |
20120062406 | ANALOG DIGITAL CONVERTING DEVICE - Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal. | 03-15-2012 |
20120154193 | SUBRANGE ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC). | 06-21-2012 |
20120268300 | ANALOG-TO-DIGITAL CONVERTER AND SIGNAL PROCESSING SYSTEM - An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N−m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage. | 10-25-2012 |
20130057424 | ANALOG-DIGITAL CONVERTER AND CONVERTING METHOD USING CLOCK DELAY - The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal. | 03-07-2013 |
20130162456 | ANALOG TO DIGITAL CONVERTING APPARATUS AND METHOD THEREOF - An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result. | 06-27-2013 |
20130194120 | Robust Encoder for Folding Analog to Digital Converter - An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs. | 08-01-2013 |
20130207825 | SOLID-STATE IMAGE SENSING DEVICE - A solid-state image sensing device comprises a pixel which outputs a pixel signal, a first conversion unit which converts the pixel signal into a digital signal with a first bit length, and a second conversion unit which converts, into a digital signal with a second bit length, an analog signal obtained by subtracting, from the pixel signal, an analog signal corresponding to the digital signal with the first bit length. The second conversion unit comprises a current source, a first capacitance, and a switching unit for switching a supply destination of a current supplied from the current source to one of the first capacitance and a reference potential. The second conversion unit performs the conversion based on comparison between a reference voltage and the analog signal which is charged in the first capacitance and is obtained as a subtraction result. | 08-15-2013 |
20130314265 | Method for Reading out Multiple SRAM Blocks with Different Column Sizing in Stitched CMOS Image Sensor - A controlling console for moving elements such as trusses and winches. A console body has a display screen, and a processor which is programmed to produce an output screen on the display screen which accepts controls for controlling at least one movable device. The output screen includes a plurality of different logical blocks which are connected together. Values and conditions such as true, false, rising edge or error can be entered. The console arranges this into a flow arrangement. | 11-28-2013 |
20130321189 | AD CONVERTER CIRCUIT AND AD CONVERSION METHOD - A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit. | 12-05-2013 |
20140247177 | DATA CONVERSION WITH REDUNDANT SPLIT-CAPACITOR ARRANGEMENT - Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights. | 09-04-2014 |
20140266846 | METHOD AND APPARATUS FOR CONVERTING AN ANALOG SIGNAL TO A DIGITAL SIGNAL BASED ON REFERENCE VOLTAGES PROVIDED BY REFERENCE LADDERS - A circuit including first and second reference ladders, a selection circuit, first and second analog to digital converters (ADCs), and a summer. The first reference ladder is configured to provide first reference voltages via first taps. The selection circuit is configured to select one of the first reference voltages. The second reference ladder is configured to, based on the selected one of the first reference voltages, provide second reference voltages via second taps. The first ADC is configured to convert the first version of the analog input signal to a first digital signal. The second ADC is configured to, based on the second reference voltages, convert the second version of the analog input signal to a second digital signal. The summer is configured to generate a digital output signal based on the first and second digital signals. | 09-18-2014 |
20140292552 | TIME-TO-DIGITAL CONVERTER AND CONVERSION METHOD - The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit. | 10-02-2014 |
20140320328 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result. | 10-30-2014 |
20140368371 | AMPLIFIER USING MULTI INPUT DIFFERENTIAL PAIR, AND COMPARATOR AND ANALOG-TO-DIGITAL CONVERTING APPARATUS USING THE SAME - An amplifier includes a common load suitable for outputting an output signal, a coarse input differential stage, coupled to the common load, suitable for amplifying a difference between an input signal and a coarse ramping signal to output a coarse conversion signal as a first output signal, when the coarse ramping signal is lower than the input signal, and a fine input differential stage, coupled to the common load, suitable for amplifying a difference between a fine ramping signal and a bias signal and compensating the first output signal to output a fine conversion signal as the output signal, when a zero crossing occurs by the compensated first output signal. | 12-18-2014 |
20150022388 | DEVICE FOR CONVERTING ANALOGUE SIGNALS INTO DIGITAL SIGNALS - Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( | 01-22-2015 |
20150077280 | PIPELINED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - A multistage analog-to-digital data conversion, including: a first stage unit configured to process an analog input signal into a first number of most significant bits using a first reference signal, and to output a first stage residue signal; a second stage unit configured to receive and process the first stage residue signal into a second number of remaining least significant bits using a second reference signal; a sampling unit configured to sample the first stage residue signal received from the first stage unit onto the second stage unit with a passive element; and an output unit configured to output a digital value that is a combination of the first number of most significant bits and the second number of remaining least significant bits. | 03-19-2015 |
20150109160 | Analog to Digital Conversion Method and Related Analog to Digital Converter - An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal. | 04-23-2015 |
20150130648 | METHOD AND CIRCUIT FOR AN ANALOG DIGITAL CAPACITY CONVERTER - A method for converting a capacitance of a sensing capacitor ( | 05-14-2015 |
20150138007 | ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD - According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit. | 05-21-2015 |
20150303938 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS AND METHODS USING SHIFT VOLTAGE TO SUPPORT OVERSAMPLING - An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage. | 10-22-2015 |
20150311913 | DISTRIBUTED VIRTUAL-GROUND SWITCHING FOR SAR AND PIPELINED ADC - Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations. Based on the value of the signal representations, a state machine controls each of the switches to apply reference signals to the input buffers, during a second operation phase, and to iteratively generate additional signal representations and provide a digital signal that corresponds to the analog input signal. | 10-29-2015 |
20150381194 | SENSOR SYSTEM USING MULTIPLE MODES FOR ANALOG TO DIGITAL CONVERSION - A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode and a fine mode. The dual mode converter is configured to receive an input signal and convert the input signal to a digital output having a selected resolution. The control unit is coupled to the dual mode converter and is configured to operate the converter in the coarse mode until a coarse approximation is obtained and to operate the converter in the fine mode until a fine approximation is obtained having the selected resolution. The fine mode includes multi-bit incremental tracking. | 12-31-2015 |
20160065231 | EFFICIENT ANALOG TO DIGITAL CONVERTER - An efficient analog to digital converter is disclosed. The efficient analog to digital converter includes a coarse analog to digital converter coupled to an input analog signal. The coarse analog to digital converter is configured to provide an approximate digital representation of the input analog signal. The efficient analog to digital converter also includes a fine analog to digital converter coupled to the input analog signal. The output of the coarse analog to digital converter is coupled to the fine analog to digital converter. The fine analog to digital converter is configured to set input range of the fine analog to digital converter as a function of the output of the coarse analog to digital converter. | 03-03-2016 |
20160112058 | AD CONVERTER - A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator. | 04-21-2016 |
20160112059 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND CONVERSION METHOD THEREOF - A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors. | 04-21-2016 |
20160156365 | SENSOR SYSTEM USING MULTIPLE MODES FOR ANALOG TO DIGITAL CONVERSION | 06-02-2016 |
20160182071 | METHOD AND DEVICE FOR ANALOG-TO-DIGITAL CONVERSION OF SIGNALS, CORRESPONDING APPARATUS | 06-23-2016 |
20160204791 | HIGH SPEED DATA TRANSFER FOR ANALOG-TO-DIGITAL CONVERTERS | 07-14-2016 |