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Analog to digital conversion

Subclass of:

341 - Coded data generation or conversion

341126000 - ANALOG TO OR FROM DIGITAL CONVERSION

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
341158000 Analog input compared with static reference 146
341172000 Using charge transfer devices (e.g., charge coupled devices, charge transfer by switched capacitances) 58
341166000 Intermediate conversion to time interval 44
341156000 Coarse and fine conversions 26
341157000 Intermediate conversion to frequency or number of pulses 14
Entries
DocumentTitleDate
20130027239DATA CONVERSION METHOD BASED ON NEGATIVE beta-MAP - There is provided a data conversion method based on negative β-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on negative β-map includes a discrete time integrator 01-31-2013
20130044019SYSTEMS WITH BIAS OFFSET AND GAIN MISMATCH REMOVAL FROM PARALLEL TRANSMITTED SIGNALS - A system includes converters, first modules, second modules, and a multiplexer. The converters receive an analog signal and a respective one of multiple clock signals. Each of the converters samples the analog signal based on a respective clock signal to generate a respective digital signal. Each of the clock signals is out-of-phase with other ones of the clock signals. The first modules receive the digital signals generated by the converters, remove bias offsets from the digital signals to generate first output signals, and output each of the first output signals on a multiple channels. The second modules receive the first output signals, and based on the first output signals, remove or equalize gain mismatch between the channels to generate second output signals. The multiplexer receives the second output signals, and generates an output based on the second output signals. The output is a digital representation of the analog signal.02-21-2013
20120200443SIGNAL PROCESSING CIRCUIT - A signal processing circuit includes an encoder configured to encode a digital signal inputted thereto and output an encode signal, and a memory electrically connected to a first input terminal and the encoder. The memory is configured to store information based on the encode signal outputted from the encoder therein, based on a first write signal inputted via the first input terminal.08-09-2012
20130027238Systems, Methods, and Apparatus for Sensing AC Voltage - Certain embodiments of the invention may include systems, methods, and apparatus for sensing AC voltage. According to an example embodiment of the invention, a method is provided for sensing AC voltage. The method includes providing a voltage sensing circuit in communication with an AC power source; rectifying an AC signal from the AC power source with rectifier circuitry of the voltage sensing circuit; applying a first voltage to an analog-to-digital (A-to-D) converter circuit, wherein the first voltage is across a second resistive element of a first half cycle voltage divider comprising a first resistive element and the second resistive element and in communication with a positive DC output of the rectifier circuitry; and analyzing the first digital voltage value and the second digital voltage value by a processor to determine a voltage of the AC power source.01-31-2013
20080266157STAGGERED INTERLEAVED NYQUIST REGIONS AVOID GUARD BAND INDUCED HOLES WHEN SAMPLING A BAND LIMITED SIGNAL - Staggered interleaved Nyquist regions associated with differing ADC clock rates (F10-30-2008
20110181453COMPACT DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter is disclosed. An example digital-to-analog converter circuit includes a reference scaling circuit coupled to receive a first reference current. The reference scaling circuit is coupled to generate a second reference current in response to the first reference current. The digital-to-analog converter circuit also includes a first plurality of binary-weighted current sources coupled to a summing node. A current of a first one of the first plurality of binary-weighted current sources is proportional to the first reference current. The digital-to-analog converter circuit also includes a second plurality of binary-weighted current sources coupled to the summing node. A current of a first one of the second plurality of binary-weighted current sources is proportional to the second reference current.07-28-2011
20090195429TIME TO DIGITAL CONVERTING CIRCUIT AND RELATED METHOD - A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.08-06-2009
20090195428ANALOG-TO-DIGITAL CONVERTER WITH VARIABLE GAIN AND METHOD THEREOF - An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.08-06-2009
20090195427A/D converter - A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuit 08-06-2009
20090295614DIGITAL-TO-ANALOG CONVERTER CIRCUIT LAYOUT - A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.12-03-2009
20090027249A/D CONVERTERS BASED ON SIGMA DELTA MODULATORS AND ITERATIVE METHODS - A system and method is provided to improve the performance of the sigma delta analog to digital converter (ADC). An input signal analog signal received though an input device is passed to a sigma delta modulator (SDM). The output of the modulator is passed through a low pass filter. An iterative algorithm and acceleration algorithm are applied to process the filter output signals to shape the noise components and to improve the performance of the sigma delta ADC. A distortion operator such as G operator, comprising of sigma delta modulator and multistage low pass filter (LPF) is used to suppress the shaped quantization noise.01-29-2009
20080258958Signal processing device and method, signal processing program, and recording medium where the program is recorded - A signal processing device which outputs a discrete signal composed of a string of the sampling values and parameters m signal. The signal processing device includes a sampling circuit which samples an input signal and outputs a discrete signal, multiple function generators which generate multiple sampling functions with parameters m different from each other, plural inner product operating units for each of parameters m that take an inner product between the input signal and each of plural sampling functions and output an inner product operating value, and a judging unit which determines parameter m providing a minimum error out of multiple errors composed of differences between the sampling value and inner product operating values output from the multiple inner product operating units and outputs the parameters m signal.10-23-2008
20080258956Apparatus for Analog/Digital Conversion of a Measurement Voltage - apparatus for the analog/digital conversion of a measurement voltage with an analog/digital converter, which has an integrating component with an operational amplifier, a resistor and a capacitor in a feedback loop, wherein a reference voltage is applied to the inverting input of the operational amplifier and wherein the measurement voltage is applied to the non-inverting input of the operational amplifier The capacitor is charged during a charging phase of time length (t10-23-2008
20110193734SIGNAL CONVERTER, PARAMETER DECIDING DEVICE, PARAMETER DECIDING METHOD, PROGRAM, AND RECORDING MEDIUM - A signal converter and the like, which can more accurately and stably realize signal conversion between an analog signal and a digital signal are proposed. In a β-encoder, when a logic value generated by at least a quantizer 08-11-2011
20090121911COMPARATOR AND A-D CONVERTER - A comparator is provided that outputs a comparison result obtained by comparing two signals. The comparator includes a positive buffer that converts a positive comparison signal, which has a level according to a difference between the two signals, into a positive logic signal that indicates a logic level; a negative buffer that converts a negative comparison signal, which has a level that is inverted in relation to the positive comparison signal, into a negative logic signal that indicates a logic level that is inverted in relation to the positive logic signal; a latch core that, at a timing at which a latch period in which the comparison result is held begins, acquires the logic level of the positive logic signal and the logic level of the negative logic signal and holds the acquired logic levels; and a potential control section that, prior to a timing at which the latch period ends, sets an output end of the positive buffer to have a potential that is identical to that of an output end of the negative buffer.05-14-2009
20100073213SIGNAL PROCESSING DEVICE - A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.03-25-2010
20100073214DIFFERENTIAL OPERATIONAL AMPLIFIER CIRCUIT CORRECTING SETTLING ERROR FOR USE IN PIPELINED A/D CONVERTER - A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.03-25-2010
20100033361System, in particular for digitizing a time-continuous and value-continuous periodic signal with a firmly predefined number of samples per period - A system is disclosed, in particular for digitizing a time-continuous and value-continuous periodic signal with a respective firmly predefined number of samples per period. In at least one embodiment, the system includes an A/D converter for digitizing an analog AC signal applied to the input of the A/D converter, the converter including a single-bit modulator which converts the AC signal into a first data stream of temporally immediately successive single-bit data words at a predefined operating clock rate; and a downstream decimation filter which respectively aggregates a predefined number of temporally immediately successive single-bit data words in the first data stream into respective temporally immediately successive n-bit data words which form a second data stream which corresponds to a digitization of the AC signal at a sampling frequency which is derived from the operating clock rate and the predefined number by way of division. In order to achieve digitization with a respective firmly predefined number of samples per period with relatively little technical complexity, it is proposed in at least one embodiment that the operating clock rate be respectively generated by a digitally adjustable oscillator on the basis of a signal characteristic of the AC signal.02-11-2010
20130038482MIXED LINEAR/SQUARE-ROOT ENCODED SINGLE SLOPE RAMP PROVIDES A FAST, LOW NOISE ANALOG TO DIGITAL CONVERTER WITH VERY HIGH LINEARITY FOR FOCAL PLANE ARRAYS - An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.02-14-2013
20100045503Pulse phase difference detecting circuit and A/D converter using the same - Provided is a pulse phase difference detecting circuit including: a first delay circuit that receives a first pulse signal to output a signal obtained by delaying the first pulse signal as a second pulse signal and includes multiple serially-connected delay units having the same delay amount; a second delay circuit that receives the second pulse signal and includes multiple serially-connected delay units having the delay amount; a first delay adjustment circuit that adjusts a delay amount with respect to the second pulse signal and outputs the adjusted second pulse signal back to the first delay circuit as a third pulse signal; and a pulse arrival position detecting circuit that detects a pulse arrival position of the first pulse signal based on outputs of the delay units of the first and second delay circuits that are transmitted as the third and second pulse signals, respectively.02-25-2010
20100103017ANALOG-TO-DIGITAL CONVERTER, SOLID-STATE IMAGING DEVICE INCLUDING THE SAME, AND METHOD OF DIGITIZING ANALOG SIGNAL - An analog-to-digital converter receives first and second analog signal voltages, and first and second comparison voltages. The first and second comparison voltages decrease by the same fixed inclination from a first reference voltage to below the first signal voltage and from a second reference voltage to below the second signal voltage, respectively. The converter counts cumulatively over first periods to acquire a first result, counts cumulatively over second periods to acquire a second result, and outputs a difference between the first and second results as a digital quantity. Each first period is time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first signal voltage. Each second period is time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second signal voltage.04-29-2010
20090146857Maintaining A Reference Voltage Constant Against Load Variations - A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.06-11-2009
20090045994MULTIPLE MODE DIGITIZATION SYSTEM FOR A NON-DESTRUCTIVE INSPECTION INSTRUMENT - A multiple mode digitization system for a non-destructive inspection instrument which makes use of a multiplexing circuit and a single set of analog to digital converters to efficiently digitize analog test signals from a plurality of inputs. In the preferred embodiment, each of the analog to digital converters in the system is driven with an independent and separate clock signal, allowing for propagation delay compensation among the plurality of test signals as well as interleaved sampling such that custom sampling rates can be used for each input without the need for more than one clock frequency. In an alternate embodiment, phase adjustments on the sampling clocks are used only for interleave sampling, and digital filters are used to provide signal propagation delay compensation.02-19-2009
20130050005Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors - Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.02-28-2013
20130069810Variable Resolution Data Conversion in a Receiver - A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.03-21-2013
20130069809SYSTEMS AND METHODS FOR DESIGNING ADC BASED ON PROBABILISTIC SWITCHING OF MEMORIES - Certain aspects of the present disclosure provide a probabilistic analog to digital converter (ADC). The probabilistic ADC may be configured to convert an analog input to a variable-length or variable-amplitude pulse, apply the pulse to a plurality of memory elements as a switching pulse, and determine a digital value based on a number of memory elements that store a value after the switching pulse is applied.03-21-2013
20120218136ANALOG TO DIGITAL CONVERTER - An ADC includes an analog signal input port for receiving analog signals, a reference voltage generation circuit for producing a reference voltage, a controllable switch, a control unit including a counter, an integral circuit, and a comparison circuit. The control unit outputs an on or off signal to turn on or turn off the controllable switch, the counter starts to count when the control unit outputs the off signal. The integral circuit executes an integral action to integrate the reference voltage and output a voltage enhanced gradually when the controllable switch is turned off. The comparison circuit outputs an interrupt signal to cause the counter to stop counting when comparing the voltage output by the integral circuit is higher than the voltage of the analog signals. The control unit determines a digital value corresponding to the analog signals according to a count value of counted by the counter.08-30-2012
20130057423SYSTEMS, DEVICES, AND METHODS FOR CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING AND SIGNAL REPRESENTATION - Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.03-07-2013
20130057422COMPARATOR NOISE REDUCTION BY MEANS OF A PROGRAMMABLE BANDWIDTH - A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.03-07-2013
20090091487Spurious Free Dynamic Range Of An Analog To Digital Converter - Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved.04-09-2009
20110057826MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS), SYSTEMS, AND OPERATING METHODS THEREOF - A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC.03-10-2011
20090267819Systems and Methods for Reducing the Effects of ADC Mismatch - Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.10-29-2009
20100085230SIGMA DELTA MODULATOR AND SIGMA DELTA A/D CONVERTER USING THE SAME - A sigma-delta modulator is provided. The sigma-delta modulator includes a differential amplifier which outputs a difference signal indicating a difference between an input analog signal and a feedback input analog signal, an integrator which integrates the difference signal, a band pass filter unit connected to the integrator in parallel which performs band pass filtering with respect to the difference signal, an adder which adds the band-pass filtered signal to the integrated signal, a comparator which compares a signal output from the adder with a predetermined reference value, converts the comparison result into a digital signal, and outputs the digital signal; and a digital-to-analog (D/A) which converts the digital signal output from the comparator into an analog signal and feeds the analog signal back to the differential amplifier.04-08-2010
20100085231DATA PROCESSING DEVICE COMPRISING ADC UNIT04-08-2010
20120235845AD CONVERTING DEVICE, DIAL-TYPE INPUT DEVICE, AND RESISTANCE-VOLTAGE CONVERSION CIRCUIT - An AD converting device includes a resistance-voltage conversion circuit which changes a first integrated voltage in proportion to a product of a varied resistance of a variable resistance and an electrical current applied to the variable resistance and changes a second integrated voltage and a reference voltage in proportion to a product of a total resistance of the variable resistance and the electrical current.09-20-2012
20120235844Comparing Circuit and Parallel Analog-To-Digital Converter - First and second resistor series divide a predetermined voltage range to generate first reference voltages and second reference voltages, respectively. First and second switch controlling circuits select respective ones of the first reference voltages and the second reference voltages. A comparing unit generates a logical signal representing a logical value by comparing a combined transistor current based on the selected first and second reference voltages with a transistor current based on an input signal. The first switch controlling circuit specifies two adjacent first reference voltages where the logical value is inverted by sequentially selecting the first reference voltages, and determines to select one of the adjacent reference voltages. Te second switch controlling circuit specifies two adjacent second reference voltages where the logical value is inverted by sequentially selecting the second reference voltages, and determines to select one of the adjacent reference voltages.09-20-2012
20100060500Analog/Digital Converter Assembly and Corresponding Method - An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (03-11-2010
20120319882ANALOG-TO-DIGITAL CONVERTER (ADC) AND COMPARATOR UNIT THEREOF - An ADC with comparing circuit units is provided. Each comparing circuit unit comprises a first resistor, a second resistor, and a CMOS. The first and second resistors provide first and second level voltages, respectively. The base of the PMOS is electrically connected to the power source and the base of the NMOS is connected to the source of the NMOS. The signal input port is located at the gate of the CMOS and receives an analog signal. The first level port of the CMOS is located at the source of the NMOS and receives the first level voltage. The second level port of the CMOS is located at the source of the PMOS and receives the second level voltage. The signal output port of the CMOS is located at the drain and outputs a digital signal.12-20-2012
20110260900SECOND ORDER DYNAMIC ELEMENT ROTATION SCHEME - A sensor system for generating sample analog signals for processing by a signal processing circuit that utilizes non-constant weights includes a plurality of signal generating elements and a switching network having a plurality of switches operably coupled to the plurality of signal generating elements. The switching network is configured to switch the plurality of signal generating elements between a plurality of different configurations. The system includes a dynamic element matching (DEM) control system for controlling the switch network to implement a second order DEM rotation scheme in which the plurality of signal generating elements are switched to each configuration in the plurality of configurations in a first sequence and then switched to each configuration in the plurality in a second sequence, the second sequence being the reverse of the first sequence.10-27-2011
20120286986A/D CONVERSION CIRCUIT - Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.11-15-2012
20100026542ADAPTIVE BIAS CURRENT GENERATION FOR SWITCHED-CAPACITOR CIRCUITS - Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ΣΔ ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.02-04-2010
20100214145SPUR CANCELLATION - A technique to mitigate in-band spurs introduced into a signal due to various board/SiP layout issues at a receiver is disclosed. The spurs can be approximated as sinusoids at different known frequencies with unknown amplitudes and phases. The technique is applicable to both single and multiple spur cancellation.08-26-2010
20080231490Fault detection apparatus for detecting failure of A/D converter due to loss of externally supplied clock signal - An A/D converter performs successive A/D conversion operations that are synchronized with respective periods of an externally supplied clock signal. A set of output digital data produced from the A/D converter, following each A/D conversion, is acquired a plurality of times in succession within an interval that extends to the start of the next A/D conversion operation. If identical sets of data are not obtained in the successive acquisitions, then it is determined that there is failure of the A/D converter due to loss of the external clock signal.09-25-2008
20090096652ANALOG-TO-DIGITAL CONVERTER (ADC) USING TUNNELING EFFECT OF PROBES - An analog-to-digital converter (ADC) is provided to determine a digital output value according to whether electric current flows between a plurality of probes, to which an input voltage is applied, and a plurality of electrodes. Therefore, high resolution and high speed operation is possible, but with lower power consumption.04-16-2009
20110285567METHOD AND CIRCUIT FOR ENCODING AND TRANSMITTING NUMERICAL VALUES FROM AN ANALOG-TO-DIGITAL CONVERSION PROCESS - An analog-to-digital converter system and methodology comprising an analog-to-digital converter circuit configured to provide sequentially a plurality of codes designating a numerical value in a first number system. The analog-to-digital converter system further comprising an encoder interface circuit configured to receive the plurality of codes and to derive a redundant digital representation. A portion of the redundant digital representation is transmitted during the conversion period. The encoder interface circuit may be configured to use a numerical successive-approximation algorithm to derive the redundant digital representation. A substantial portion of the redundant digital representation may be transmitted via a serial interface during the conversion period to reduce an overall latency.11-24-2011
20110298644SWITCHED-CAPACITOR AMPLIFIER AND ANALOG FRONT-END CIRCUIT - In a first period, a first and a second feedback capacitors each store an electric charge dependent on a voltage level of an input signal. In a second period, a first and a second output voltages are fed back respectively through the first and the second feedback capacitors respectively to a first and a second input terminals of a differential amplifier, and a first and a second sampling capacitors respectively store a positive charge dependent on a difference between the voltage level of the input signal and the first output voltage, and a negative charge dependent on a difference between the voltage level of the input signal and the second output voltage. In a third period, the positive and the negative charges respectively stored in the first and the second sampling capacitors are respectively transferred to the first and the second input terminals of the differential amplifier.12-08-2011
20110298643ADAPTIVE BIAS CURRENT GENERATOR METHODS AND APPARATUS - In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.12-08-2011
20120013497A/D conversion circuit and test method - An electric device includes first, second and third selectors. A first node connects to a first input of the first selector, a second node connects to a first input of the second selector, a third node connects to a second input of the first selector, and a fourth node connects to a second input of the second selector. A first switch connects to the first node, and a second switch connects to the second node. A first capacitor connects between the first switch and the third node, and a second capacitor connects between the second switch and the fourth node. A fifth node connects between an output of the first selector and a first input of the third selector, and a sixth node connects between an output of the second selector and a second input of the third selector. An A/D converter connects to an output of the third selector.01-19-2012
20110291872MULTI-GIGABIT ANALOG TO DIGITAL CONVERTER - An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.12-01-2011
20110291871CURRENT-MODE DUAL-SLOPE TEMPERATURE-DIGITAL CONVERSION DEVICE - A current mode dual-slope temperature-to-digital conversion device is disclosed. The conversion device comprises a temperature dependent current source and a reference current source. Firstly, a capacitor is charged by the temperature dependent current source. Next, the capacitor is discharged by the reference current source. The capacitor is coupled to at least one trigger, and the trigger sends out a first digital signal to a logic controller by the voltage of the capacitor. Then, the logic controller sends out a second digital signal to a time-to-digital converter according to the first digital signal. When the capacitor is discharged by the reference current source and before the first digital signal is varied, the converter receives the second digital signal and a clock signal to generate a corresponding digital output value. The present invention achieves the requirement of the high linearity resolution with the dual-slope architecture lest the curvature effect resulted from the time-domain circuit be occurred.12-01-2011
20110291870ANALOG-TO-DIGITAL CONVERTING CIRCUIT - The present invention relates to an analog-to-digital converting circuit, which comprises an integrating circuit, a reference signal generating circuit, a comparator, and a first counting circuit. The integrating circuit integrates an input signal for producing an integration signal. The reference signal generating circuit produces a plurality of reference signals. The comparator receives the integration signal and the plurality of reference signals, and compares the integration signal to the plurality of reference signals sequentially for producing a plurality of comparison signals. The first counting circuit receives the plurality of comparison signals produced by the comparator, and starts to count the plurality of comparison signals for producing a reset signal and resetting the integrating circuit. Because the integrating circuit is not reset once until the comparator produces the plurality of comparison signals, the number of times of resetting the integrating circuit can be reduced, and hence reducing the integral nonlinearity effect. Accordingly, the accuracy of the analog-to-digital converting circuit is enhanced.12-01-2011
20110032136REDUCTION IN KICKBACK EFFECT IN COMPARATORS - The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.02-10-2011
20090273500IMAGE SENSORS AND DUAL RAMP ANALOG-TO-DIGITAL CONVERTERS AND METHODS - Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.11-05-2009
20090002213Method and Apparatus for a High Bandwidth Oscilloscope Utilizing Multiple Channel Digital Bandwidth Interleaving - A method of digitizing an analog signal is provided, comprising the steps of separating the analog signal spanning a frequency range into a plurality of frequency bands, each frequency band spanning a corresponding predefined frequency range, at least a portion of each of the plurality of corresponding frequency ranges not overlapping any other of the plurality of corresponding predefined frequency ranges and then translating at least one of the signals in the plurality of frequency bands to a lower frequency band in accordance with a local oscillator and digitizing the at least one translated signal with digitizing elements having a frequency range less than the analog signal frequency range. A fixed relationship of the phase of the local oscillator and a repetitive signal generated in accordance with a writing to a circular buffer of the digitized representation of the at least one of the plurality of frequency bands is then defined. Signals corresponding to the other of the plurality of frequency bands are digitized and written to corresponding circular buffers in accordance with one or more corresponding local oscillators. Finally, a digital representation of the analog signal is formed from the digitized signals, the digital representation substantially spanning the frequency range of the analog signal, and the digital representation is stored in a computer readable medium.01-01-2009
20130214956VIRTUAL ANALOG TO DIGITAL CONVERTER - The disclosure relates to analog to digital converters, in particular to logical circuit blocks, a system and a method, which provide functionality of an additional analog to digital converter. In accordance with an aspect of the disclosure, there is provided a logical circuit block, which is configured to be connected to a plurality of ADCs each including a plurality of input pins connected to a plurality of analog input channels. The logical circuit block is further configured to cause one ADC of the plurality of ADCs to perform an ADC conversion of an analog input signal received via a particular analog input channel of the plurality of analog input channels to which an input pin of the one ADC is connected.08-22-2013
20100265114Analog-to-digital conversion and implementations thereof - In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages.10-21-2010
20100033359NONLINEAR COMPENSATION IN ANALOG TO DIGITAL CONVERTERS - An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.02-11-2010
20110215958METHOD AND SYSTEM FOR VARIABLE RESOLUTION DATA CONVERSION IN A RECEIVER - A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.09-08-2011
20110215957PIPELINE ANALOG TO DIGITAL CONVERTER AND A RESIDUE AMPLIFIER FOR A PIPELINE ANALOG TO DIGITAL CONVERTER - A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.09-08-2011
20090109078Quantization Error Reduction in PWM Full-MASH Converters - Techniques for reducing quantization error in electronic components are described herein.04-30-2009
20090167585ANALOG REFERENCE VOLTAGE GENERATOR, METHOD THEREOF, ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME, AND IMAGE SENSOR INCLUDING THE SAME - An analog reference voltage generator for generating a monotonously increasing or decreasing analog reference voltage includes a plurality of dump cells in front of an operational amplifier and controls the dump cells using a plurality of clock signals, respectively, which do not overlap each other in time, thereby increasing a ramping speed. The analog reference voltage generator including the plurality of dump cells controls the generation of an analog reference voltage using the plurality of clock signals obtained by dividing a master clock signal, thereby preventing the voltage level of the reference signal from decreasing due to an increase of the load.07-02-2009
20100097259SYSTEM FOR PROCESSING PATIENT MONITORING SIGNALS - A patient monitoring signal processing system adaptively varies medical signal data rate. The system uses an analog to digital converter for digitizing an analog cyclically varying input signal derived from a patient in response to a sampling clock input. The sampling clock determines frequency of analog to digital sampling of the analog input signal by the analog to digital converter. A detector detects first and second different signal portions within a cycle of the cyclically varying input signal. A control processor coupled to the analog to digital converter and the detector, provides the sampling clock and adaptively determines first and second different frequencies of the sampling clock to be used in sampling within detected corresponding first and second different signal portions of the cyclically varying input signal in response to predetermined information indicating a frequency of a signal component of the cyclically varying input signal in the first signal portion is higher than a frequency of a signal component of the cyclically varying input signal in the second signal portion. Also the first frequency is higher than the second frequency of the first and second different frequencies.04-22-2010
20090153385Method and System for a Configurable Communications Interface - An electronic device having a receiver generating an analog signal from collected image data, a digitizer generating a digital signal from the analog signal and a micro-controller receiving the analog signal and the digital signal and generating a corrected digital signal, wherein the device outputs one of the digital signal and the corrected digital signal.06-18-2009
20090153384METHOD AND SYSTEM FOR VARIABLE RESOLUTION DATA CONVERSION IN A RECEIVER - Aspects of a method and system for variable resolution data conversion in a receiver are provided. In this regard, an analog received signal may be converted to a corresponding digital signal, wherein a resolution of the corresponding digital signal may be varied (e.g., by configuring one or more switching elements) for the conversion based on one or more determined characteristics of said received signal. The resolution of the conversion may be determined based on characteristics of in-band and/or out-of-band signals. The resolution may be increased when received signal strength is below a threshold and may be decreased when received signal strength is above a threshold. Similarly, the resolution may be increased when interference is above a threshold and may be decreased when interference is below a threshold. The resolution may be increased when error rates are above a threshold and decreased when error rates are below a threshold.06-18-2009
20090146858Method for operating a sensor system and sensor system - A method is provided for operating a sensor system having a sensor, an analog-to-digital converter and a digital signal-processing device, an analog signal from the sensor being transmitted to the analog-to-digital converter, the analog signal being converted to a digital signal by the analog-to-digital converter with a sampling frequency, the digital signal being transmitted to the digital signal-processing device, and the analog signal further being transmitted to a clock generator, the sampling frequency of the analog-to-digital converter being controlled by the clock generator as a function of the analog signal.06-11-2009
20080284630READ SIGNAL PROCESSING CIRCUIT, READ SIGNAL PROCESSING METHOD, AND OPTICAL DISC DRIVE - The present invention provides a read channel and a drive capable of suppressing deterioration in performance of a PLL and a Viterbi decoder by using a DC component eliminating means capable of higher-speed operation than hitherto. The location of an edge is determined by using differential of a read signal, and a DC component is detected from the midpoint level of the edge. Detection of a pseudo-edge due to a long mark or space signal is prevented by limiting the absolute value of a maximum or minimum of a differential coefficient when the location of the edge is determined from the differential coefficient of the read signal. Internal operation of a DC component detector is controlled according to the state of the PLL and the magnitude of the DC component.11-20-2008
20080266160SELECTING AN ACCESS POINT ACCORDING TO A MEASURE OF RECEIVED SIGNAL QUALITY - A method, an apparatus for inclusion in a wireless station, and a computer readable storage medium for operation in a wireless station. The method includes received data from at least one remote station and determining an EVM measure from samples of the received data. If the remote station(s) is/are access point(s), the station selects an access point for association according to criteria that include the measure of the EVM from the remote station.10-30-2008
20080266159SOLID-STATE IMAGING DEVICE, AD CONVERTER, AND AD CONVERTING METHOD - The present invention provides a solid-state imaging device which can output a digital signal at a high speed without using a high-speed clock. The solid-state imaging device includes light receiving elements provided in an array and generating signal voltages based on light intensity of received light and AD converters each of which is provided in each of columns in the array. Each of the AD converters includes: a reference voltage generating unit (10-30-2008
20080266158Analog-to-digital converter - An analog-digital (A-D) converter for outputting a digital signal corresponding to an analog input signal includes: an upper bit A-D converting section for conducting A-D conversion of the analog input signal and outputting an upper bit portion of the digital signal; a lower bit A-D converting section for conducting A-D conversion of the analog input signal and outputting a lower bit portion of the digital signal; and a majority circuit for sampling an A-D conversion result of the lower bit A-D converting section a plurality of times and determining a value of each of the lower bits by majority operation.10-30-2008
20100117882SEMICONDUCTOR DEVICE - A semiconductor device includes a first switching device including a first electrode coupled with a first node, a second electrode coupled with a second node, and a first control electrode controlling connection between the first and second electrodes; a second switching device including a third electrode coupled with the second node, a fourth electrode coupled with the second node, and a second control electrode controlling the connection between the third electrode and the fourth electrode; and a first control circuit controlling a substrate voltage of the second switching device.05-13-2010
20100085229ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER - Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.04-08-2010
20090207064MEASUREMENT AMPLIFICATION DEVICE AND METHOD - Measurement amplification methods and devices for detecting the detuning of a measurement bridge (08-20-2009
20080278363Data processing method, data processing apparatus, solid-state image pickup apparatus, image pickup apparatus and electronic apparatus - Disclosed herein is a data processing method wherein an analog processing object signal is compared with a reference signal and used to convert the processing object signal into digital data and a counting process is carried out and then a count value at a point of time at which the counting process is completed is retailed to acquire digital data of N bits of the processing object signal, including the steps of: carrying out counting operations using the first and second count clocks, whose frequencies are different by an amount corresponding to a weight of the bits from each other, independently of each other; and compensating for an excess or deficiency of data of the higher order N-M bits counted using the second count clock with respect to the count value counted using the first count clock within the counting operation enabled period.11-13-2008
20090295613PERFORMING ANALOG-TO-DIGITAL CONVERSION BY COMPUTING DELAY TIME BETWEEN TRAVELING WAVES IN TRANSMISSION LINES - A method and device for converting an analog input electrical signal to a digital signal. A plurality of integrated active and/or passive transmission lines may be implemented with signal-dependant propagation velocities. The delay differences of pulses traveling through these transmission lines are compared, and the collective results are used to evaluate and subsequently quantize the input signal.12-03-2009
20100220000METHOD TO REDUCE ERROR IN TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS ARISING DUE TO APERTURE DELAY MISMATCH - A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.09-02-2010
20100127908SELF-TIMED CLOCKED ANALOG TO DIGITAL CONVERTER - An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.05-27-2010
20130099952Analog-Digital Conversion System Comprising a Double Automatic Gain Control Loop - An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g04-25-2013
20110205098SWITCHED CAPACITOR AMPLIFIER - A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.08-25-2011
20110199249METHOD FOR DIGITIZING AN ANALOGUE SIGNAL WITH AN ANALOGUE-DIGITAL CONVERTER OF DETERMINED SHANNON FREQUENCY - A method for forming a global spectrum (Sg) of an analogue signal (A) to be digitized, in which: 08-18-2011
20100103016SAMPLE ERROR MINIMIZATION FOR HIGH DYNAMIC RANGE DIGITIZATION SYSTEMS - A blending circuit is disclosed to be operable to combine plurality of digital outputs received from an analog to digital conversion system to create a composite digital signal. The analog to digital conversion system receives analog signals originated from multiple but substantially the same source signals, wherein the source signals being scaled to different degrees. A blending circuit deploys a blending factor to combine the digital outputs in a manner which blends and/or adjusts portion of each digital output being used to avoid over-flown portion of the digital outputs and to minimize phase and/or amplitude discontinuity of the composite digital signal.04-29-2010
20080238752Analog-to-digital (AD) converter and analog-to-digital conversion method - An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK.10-02-2008
20080238749METHOD OF COMPRESSING WAVEFORM DATA WITH DIFFERENTIAL ENTROPY BASED COMPRESSION - Waveforms are digitally sampled and compressed for storage in memory. The compression of the data includes generating a truncated entropy encoding map and using the values within the map to obtain good compression. An encoder further sub-selects values to be encoded and values to remain unencoded to provide an overall compression of the data.10-02-2008
20100201559Continuous synchronization for multiple ADCs - A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.08-12-2010
20100201558ANALOG TO DIGITAL CONVERSION USING IRREGULAR SAMPLING - This disclosure relates to analog to digital conversion using irregular sampling.08-12-2010
20100271247Signal generator and method for generating signals for reducing noise in signals - A CMOS image sensor may include an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array. A method of operating such an CMOS image sensor may involve generating a varying reference signal that mirrors noise external to the active pixel sensor array, outputting the varying reference signal to the noise canceller array, and using the varying reference signal in the noise canceller array to cancel noise both internal to and external to the active pixel sensor array.10-28-2010
20080291071System and Method for Analyzing Dynamic CPU Voltage - Systems and methods are disclosed for monitoring a voltage supplied by a voltage regulation module to a processor in response to a dynamic VID generated by the processor. In one embodiment, a voltage monitoring system monitors the voltage generated by the voltage regulation module to ensure the supplied voltage is within regulation thresholds. The voltage monitoring system acquires an analog reading of the supplied voltage and converts it to a digital value. If the VID changes during the conversion, the result of the A/D conversion is discarded. If the VID does not change, the voltage monitoring system accepts the result of the A/D conversion and compares the supplied voltage to the voltage expected in response to the VID. The voltage monitoring system may compute the error between the actual and expected voltage for each accepted A/D conversion. These errors may be accumulated and averaged. The accumulated error may be compared with regulation thresholds, such as a predefined allowable margin of error. If the accumulated error exceeds regulation thresholds, an alert may be generated and action may be taken depending on the degree and severity of the accumulated error.11-27-2008
20090033536Method and Apparatus for Digital to Analog Conversion - The apparatus described is a multi-core processor 02-05-2009
20080309539Quantizing circuits with variable reference signals - Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a delta-sigma modulator coupled to the electrical conductor, a counter coupled to an output of the delta-sigma modulator, and an interfuser coupled to an output of the counter. In some embodiments, the interfuser is configured to receive two or more counts from the counter and read data conveyed by the data location based on the two or more counts.12-18-2008
20080309540Integrators for delta-sigma modulators - Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.12-18-2008
20080238750Intelligent Power Control Peripheral - An intelligent power control peripheral (IPCP) may facilitate communications among individual peripherals independent from a digital processor. The IPCP is a “Meta-Peripheral” that may incorporate a configurable inter-peripheral module communications network with digital pulse width modulation (PWM) generators and timing logic therefore, at least one ADC, analog comparators and at least one DAC that may be configured to provide an automatic power control structure that may also provide automatic digital processor/DSP task and workload scheduling for applications such as switch mode power supply (SMPS), brushed motor, etc. This Meta-Peripheral may further use a configurable control fabric in combination with the aforementioned specialized peripherals for the utmost in control configuration flexibility.10-02-2008
20080246644SYSTEM HAVING A SIGNAL CONVERTER - A system having a signal converter device, and a method for operating a system having a signal converter device is disclosed. One embodiment provides loading a capacitive device to a preparation voltage in a first operating phase, and loading the capacitive device to a measuring voltage in a second operating phase after the first operating phase.10-09-2008
20080204298AD CONVERTER AND RADIO RECEIVER - Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.08-28-2008
20110267214ATTENUATOR CIRCUIT - An attenuator circuit includes a high-frequency circuit path to produce an attenuated first signal; a low-frequency circuit path to produce an attenuated second signal, where the attenuated first signal has a higher frequency than the attenuated second signal; and a transistor that includes a control input. The control input is configured to receive the attenuated second signal to bias the transistor for passage of the attenuated first signal and the attenuated second signal.11-03-2011
20130214957ANALOG-TO-DIGITAL CONVERSION DEVICE - An analog-to-digital conversion device has: an analog-to-digital converter configured to receive an input signal via an input signal node, and convert the input signal to a digital signal; and a control circuit configured to receive the digital signal when the input signal is set to have a fixed value, and change, when a deviation amount of the digital signal with the respect to an expected value is equal to or larger than a threshold value, a value of a capacitor between a power supply potential node and a reference potential node of the analog-to-digital converter and/or values of resistors connected to the power supply potential node and the reference potential node of the analog-to-digital converter.08-22-2013
20130214955ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES - A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.08-22-2013
20090179787COMPARATOR AND A/D CONVERTER - A comparator used in a parallel-type A/D converter, wherein a comparator 07-16-2009
20090179786DIRECT RF COMPLEX ANALOG TO DIGITAL CONVERTER - An analog to digital converter device including: an input to receive a radio frequency (RF) signal; a plurality of delay elements coupled in series to the input, wherein each element has an output configured to provide the RF signal with a temporal delay corresponding to a different number of the delay elements; a sample rate reduction system having a plurality of inputs each being coupled to a corresponding one of the delay element outputs, and configured to sample the delayed RF signals and provide M-sample outputs, each of the M-sample outputs being sampled at a reduced sampling rate equal to the sampling rate divided by M, M being an integer sample rate reduction value; and an N07-16-2009
20090160693A/D CONVERSION CIRCUIT AND ELECTRONIC INSTRUMENT - An A/D conversion circuit includes a continuous-time filter that performs a filtering process on an input signal, an SCF that is provided in a subsequent stage of the continuous-time filter and performs a filtering process utilizing the continuous-time filter as a prefilter, a cut-off frequency of the SCF being variably set corresponding to a frequency band of the input signal, an A/D converter that is provided in a subsequent stage of the SCF and performs an A/D conversion operation utilizing the continuous-time filter and the SCF as prefilters, and a digital filter that is provided in a subsequent stage of the A/D converter and performs a digital filtering process utilizing the continuous-time filter and the SCF as prefilters, a cut-off frequency of the digital filter being variably set corresponding to the frequency band of the input signal.06-25-2009
20090160692A/D CONVERSION CIRCUIT AND ELECTRONIC INSTRUMENT - An A/D conversion circuit includes an amplifier circuit that includes a plurality of amplifiers that are cascaded, a selector that selects one of output signals output from the plurality of amplifiers and outputs the selected output signal as a selector output signal, an A/D converter that A/D-converts the selector output signal output from the selector, a determination circuit that determines whether or not a voltage of the output signal output from each of the plurality of amplifiers is within a determination voltage range specified by a high-potential-side determination voltage and a low-potential-side determination voltage, and a control circuit that instructs the selector to select one of the output signals output from the plurality of amplifiers based on the determination result of the determination circuit.06-25-2009
20090128388FILTER WITH CAPACITIVE FORWARD COUPLING - This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.05-21-2009
20110128176ANALOG TO DIGITAL CONVERSION CIRCUIT AND METHOD - Disclosed is a circuit for converting an analog input signal (06-02-2011
20090251348INTERMEDIATE FREQUENCY RECEIVING CIRCUIT AND INTERMEDIATE FREQUENCY RECEIVING METHOD - An intermediate frequency receiving circuit and an intermediate frequency receiving method are provided. The intermediate frequency receiving circuit includes an inductor-capacitor (LC) resonance circuit whose primary resonance frequency is a central frequency of received signals. The LC resonance circuit receives intermediate frequency signals and suppresses transmitted signals and control signals. A band-pass filter connected to the LC resonance circuit filters the transmitted signals and control signals. An automatic gain control circuit connected to the band-pass filter compensates the attenuation of an intermediate frequency cable. A low-pass filter connected to the automatic gain control circuit compensates an in-band flatness. An analog-to-digital converter connected to the low-pass filter performs a sampling and digital demodulation on the received signals.10-08-2009
20100277357ANALOG-TO-DIGITAL CONVERTER - Provided is an analog-to-digital converter. The analog-to-digital converter includes a resistor string for generating a plurality of reference voltages; a plurality of differential difference amplifiers for detecting zero-crossing points according to interpolation by using the plurality of reference voltages and input signals; and a plurality of comparators for receiving outputs of the plurality of differential difference amplifiers, detecting zero-crossing points according to 4X interpolation, and generating a digital code corresponding to the input signals.11-04-2010
20090051578Method and System for Correcting Switched Input A/D Converters - A system is described for correcting a switched input A/D converter circuit that performs a plurality of A/D conversions. The system includes an oversampling circuit, a switched input controller, separation circuitry, and a signal processing subsystem. The oversampling circuit is configured to convert one or more input analog signals into oversampled output signals. The switched input controller is configured to switch a separate calibration signal into the oversampling circuit, as a replacement for the input analog signal, for at least some of the A/D conversions. The separation circuitry is configured to separate the oversampled output signal from the calibration signal. The signal processing subsystem is configured to synchronously and separately process the oversampled output signal and the calibration signal so as to substantially reduce unwanted correlated response of the switched input A/D converter circuit. 02-26-2009
20110140945GAIN CIRCUIT - A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit , and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (V06-16-2011
20110140947ANALOG-TO-DIGITAL CONVERSION UNIT AND ANALOG-TO-DIGITAL CONVERTING METHOD THEREOF - An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.06-16-2011
20110140946DATA CONVERTER SYSTEM THAT AVOIDS INTERLEAVE IMAGES AND DISTORTION PRODUCTS - A data converter system provides an output signal having reduced spurious tones by confining an input signal to a specified frequency band and over-sampling so that the converted input signal “straddles” or “avoids” spurious tones. The spurious tones may then be filtered away, providing an output signal having a much cleaner spurious free dynamic range than a conventional data converter. For example, in one embodiment, an interleaved data converter system converts an input signal that is confined to the second Nyquist zone of one of the interleaved data converters into an interleaved signal, and then filters the interleaved signal with a filter having a pass-band that transmits the converted input frequencies and a stop-band that attenuates the spurious tones. The resulting output signal has a bandwidth that is the same as could be achieved using a single data converter, but is not impaired by interleave images or certain distortion products.06-16-2011
20090201188Semiconductor chip with a number of A/D converters that include a group of redundant A/D converters - The manufacturing yield of an A/D converter semiconductor chip is significantly increased by utilizing a number of A/D converter circuits that include a group of redundant A/D converter circuits. As a result, the semiconductor chip can be wired to form a “good” A/D converter semiconductor chip as long as the number of “bad” A/D converter circuits does not exceed the number of redundant A/D converter circuits.08-13-2009
20090096653RF CHIP INCLUDING SHARED CONVERTER AND TRANSCEIVER INCLUDING THE RF CHIP - The invention generally relates to a radio frequency (RF) chip and/or a baseband chip for use in a wireless transmitter and/or receiver. Embodiments of the invention solve a problem caused by a mismatch in amplitude and/or phase between in-phase (I) and quadrature (Q) signals in such communication devices. According to an aspect of the invention, there is provided a communication device including: a baseband signal processing unit configured to output a plurality of analog baseband signals through a corresponding plurality of channels; and a radio frequency (RF) processing unit coupled to the plurality of channels, the RF processing unit configured to convert the plurality of analog baseband signals into a plurality of digital signals using a shared analog-to-digital converter (ADC), the RF processing unit further configured to generate an RF signal based on the plurality of digital signals.04-16-2009
20090096650Methods and systems for continuous-time digital modulation - Methods and systems for modulating (04-16-2009
20110227773CONFIGURABLE ANALOG INPUT CHANNEL WITH GALVANIC ISOLATION - Embodiments of the invention relate generally to a configurable analog input channel with galvanic isolation. In one embodiment, the invention provides a configurable input channel for selectively receiving one of a plurality of different analog sensor inputs. The input channel includes an interface for implementing switch settings for a selected type of input signal; a set of input terminals, wherein at least two of the set of input terminals are selectively utilized to correspond with the selected type of input signal; an analog-to-digital converter for converting the input signal into a digital output, wherein an operation of the analog-to-digital converter is determined based on the switch settings; and an isolation barrier for isolating the configurable input channel.09-22-2011
20090021412TIME-INTERLEAVED ANALOG-TO-DIGITAL-CONVERTER - A method for operating a time-interleaved analog-to-digital converter for converting an analog input to a digital output using a time-interleaved analog-to-digital converter, wherein the time-interleaved analog-to-digital converter comprises an array of M sub ADCs (ADC01-22-2009
20090231177Method and Arrangement for the Digital Transmission of an Analogue Measuring Signal - The invention relates to a method for the digital transmission of an analogue measuring signal (M), comprising the following steps: 09-17-2009
20110221621A/D CONVERSION CIRCUIT - An A/D conversion circuit includes a pulse transit circuit, first and second pulse transit position detection circuits, and a digital signal generation circuit. The first pulse transit position detection circuit detects a transit position of the pulse signal output from the pulse transit circuit and generates a logical signal according to the transit position. The second pulse transit position detection circuit detects the circling number of the pulse signal output from the pulse transit circuit and generates a logical signal according to the circling number. The digital signal generation circuit synthesizes the logical signals output from the first and second pulse transit position detection circuits and generates a digital signal according to a size of an analog signal VA. The pulse transit circuit is configured so that a sum of the number of the inverting circuits that the pulse signal transits in an N-th period (N denotes a natural number) and the number of the inverting circuits that the pulse signal transits in an (N+1)-th period is a power of 2.09-15-2011
20130214958INTERLEAVED ANALOG TO DIGITAL CONVERTER WITH REDUCED NUMBER OF MULTIPLIERS FOR DIGITAL EQUALIZATION - A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.08-22-2013
20090195431SINGLE SLOPE ANALOG-TO-DIGITAL CONVERTER - A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.08-06-2009
20090195430ANALOG-TO-DIGITAL CONVERTING APPARATUS WITH LOWER TEMPERATURE DEPENDENCE - In an A/D converting apparatus, a converting unit has an input terminal and an input-output characteristic. The input-output characteristic has temperature dependence, and the converting unit carries out a process of converting an input voltage signal to digital data. A temperature determining unit has information representing a relationship between a variable of an output of the converting unit and a variable of a temperature around the converting unit according to the temperature dependence of the input-output characteristic of the converting unit. When the specified voltage is applied to the input terminal of the converting unit, the temperature determining unit determines a value of the temperature around the converting unit based on the information and the specified voltage. A reducing unit reduces temperature dependence of the process of converting an input voltage signal to digital data based on the determined value of the temperature around the converting unit.08-06-2009
20090243906DIFFERENTIAL COMPARATOR, AND PIPELINE TYPE A/D CONVERTER EQUIPPED WITH THE SAME - In some examples, a differential comparator includes a differential amplifier configured to output differential output signals, a first switch portion configured to input the differential output signals from the differential amplifier and output the differential output signals from output terminals while alternatively changing over the output terminals, a latch portion configured to update and latch the differential output signals from the output terminals of the first switch portion, and a second switch portion configured to input output signals from the latch portion and output the latched output signals. The first switch portion and the second switch portion are changed over complementarily so that the differential output signals from the differential amplifier are always outputted from the same first and second output terminals of the second switch portion respectively.10-01-2009
20090096651ANALOG-TO-DIGITAL (AD) CONVERTER USING RESONANCE FREQUENCY SHIFTING AND VOLTAGE DETECTING DEVICE THEREOF - An analog-to-digital (AD) converter and a voltage detecting device thereof are provided. The AD converter includes at least one voltage detecting device which outputs a signal of a frequency determined based on a magnitude of an input voltage using a resonance frequency of a resonator. The AD converter determines a digital output value depending on the output signal from the voltage detecting device. Therefore, the AD converter can achieve a high resolution and a high speed with far less power consumption.04-16-2009
20090256734TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERSION APPARATUS - A time-interleaved analog-to-digital conversion apparatus is disclosed. The time-interleaved analog-to-digital conversion apparatus is applied for a television system and includes an input multiplexing module, a gain multiplexer and an analog-to-digital converter. The input multiplexing module receives a plurality of image signals, and samples the image signals according to a clock signal to generate a sample multiplexing signal. The gain multiplexer receives a plurality of gain signals and selectively transmits one of the gain signals corresponding to the sample multiplexing signal according to the clock signal, so as to generate a gain multiplexing signal. The analog-to-digital converter receives the sample multiplexing signal, the gain multiplexing signal and the clock signal. The analog-to-digital converter amplifies and converts the sample multiplexing signal to a digital signal according to the gain multiplexing signal and the clock signal.10-15-2009
20090273499SYSTEM AND METHOD FOR IMPROVING LINEARITY OF ELECTRONIC CIRCUITS WITH MECHANICAL OSCILLATORS - A system converts an analog input signal to an output signal in a very linear manner using very low chip area and very low power consumption. The system includes a micro electromechanical oscillating signal source for generating a linearly varying oscillating signal, an analog signal generator coupled to the micro electromechanical oscillating signal source, the analog signal generator being configured to convert the linearly varying oscillating signal to an electrical analog signal, a minimum transistor circuit having an input for receiving an analog signal, a switch that selectively couples the electrical analog signal to the input of the minimum transistor circuit, the minimum transistor circuit being configured to process the electrical analog signal and generate digital output values, an error detection circuit coupled to the minimum transistor circuit to detect non-linearity errors in the digital output values, and a linearity correction circuit coupled to the error detection circuit, the linearity correction circuit being configured to compensate for the non-linearity errors detected by the error detection circuit.11-05-2009
20100156690DIGITAL DIRECT CONVERSION RECEIVING APPARATUS AND METHOD - A digital direct conversion receiving apparatus, including: a phase conversion unit to down-convert a Radio Frequency (RF) signal into a plurality of sample signals, and generate a certain phase difference among the plurality of sample signals when the RF signal is down-converted; and a variable complex gain unit to remove an image component from the plurality of sample signals using the generated phase difference.06-24-2010
20100176979ANALOG TO DIGITAL CONVERTER - An analog to digital converter comprising an Nth analog to digital converter and an N+1th analog to digital converter arranged in series such that a residue signal from the Nth analog to digital converter is provided as an input to the N+1th analog to digital converter, characterised in that a bandwidth control means is provided in a signal path for the residue signal and the bandwidth control means is controlled so as to have a first bandwidth during a first period following generation of a conversion result from the Nth analog to digital converter, and a second bandwidth less than the first bandwidth in a second period following the first period.07-15-2010
20090079611ADC USE WITH MULTIPLE SIGNAL MODES - A signal is received and whether a signal mode of the signal is a first signal mode or a second signal mode is determined. A gain of a variable gain amplifier is adjusted to a first gain value if the signal mode of the signal is determined to be the first signal mode or a second gain value if the signal mode of the signal is determined to be the second signal mode. The signal is amplified with the variable gain amplifier by the first gain value or the second gain value. The signal is converted to a digital signal with an analog to digital converter after the signal is amplified with the variable gain amplifier by the first gain value or the second gain value.03-26-2009
20100176982QUANTIZER, ANALOGUE-TO-DIGITAL CONVERTER COMPRISING SUCH A QUANTIZER, AND ULTRA-WIDE BAND RECEIVER INTEGRATING SUCH A CONVERTER - The invention relates to an N-bit asynchronous Quantizer including a 207-15-2010
20100176981SPLIT ANALOG/DIGITAL POLYNOMIAL NONLINEAR TERM GENERATOR WITH REDUCED NUMBER OF ANALOG-TO-DIGITAL CONVERTERS - A polynomial nonlinear term generator is configured to receive an RF signal. An analog cubic term generator generates an analog cubic term signal and an analog square term generator generates an analog square term signal, both derived from the RF signal. A cubic term mixer assembly mixes a local oscillator (LO) signal with the cubic term signal to generate a synthetic IM3 signal. A square term ADC provides a digital square term signal and a cubic term ADC provides a digital cubic term signal. At least one digital multiplier has a first multiplier input terminal configured to receive a selected one of the digital square term signal and the digital cubic term signal, and a second multiplier input terminal configured to receive the digital square term signal. The multiplier provides as output a digital IMn product where n is greater than 3. A corresponding method is also described.07-15-2010
20100259434LINE NOISE ANALYSIS AND DETECTION AND MEASUREMENT ERROR REDUCTION - A method includes sensing a process parameter to generate a sensor signal that includes a process signal and line noise components, digitizing the sensor signal at a sample rate, detecting line noise zero crossings in the sensor signal, determining a line noise frequency as a function of the detected line noise zero crossings, and adjusting the sample rate as a function of the line noise frequency to reduce an impact of line noise on the digitized sensor signal.10-14-2010
20100001891A/D CONVERTER - In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.01-07-2010
20100013690A-D CONVERT APPARATUS - Provided is a successive approximation AD conversion apparatus that outputs digital output data corresponding to an analog input signal, including a bit selecting section that selects a conversion target bit sequentially from a highest bit of the output data; a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected; a DA conversing section that outputs an analog comparison signal corresponding to the comparison data; a comparing section that outputs a comparison result between the input signal and the comparison signal, upon the output of the comparison signal by the DA converting section, and that is reset after outputting the comparison result; a completion detecting section that, upon detecting that the comparing section has output the comparison result, outputs a completion signal causing the bit selecting section to select a next conversion target bit, prior to the comparing section being reset; and an output section that outputs output data in which a value of each bit is based on the comparison result by the comparing section.01-21-2010
20100176980ANALOG TO DIGITAL CONVERSION SYSTEM - The system converts an analog input signal into a digital output signal while avoiding interference, such as clipping. The system derives two signal components having differing signal magnitude levels from the analog input signal. The signal components are subjected to independent analog to digital conversion, such as through low resolution analog to digital converters. The system determines weighting factors for the two signal components based on at least one property of at least one of the signal components, such as the level of at least one of the signal components. The signal components are weighted. The weighted signal components are merged.07-15-2010
20100207799ANALOG-TO-DIGITAL CONVERTER AND ANALOG TO-DIGITAL CONVERSION METHOD - An analog-to-digital converter is disclosed. An input signal processor sets a voltage of an input signal as an initial value of a signal voltage Vin, subtracts ½08-19-2010
20100207797DIGITALLY ADJUSTABLE QUANTIZATION CIRCUIT - Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.08-19-2010
20100245146INTELLIGENT ANALOG-DIGITAL CONVERTER CHIP - The present invention discloses an intelligent analog-digital converter chip. It mainly comprises an amplifier, a filter, an analog/digital converter and a central processing unit. The main feature of the present invention is that it can directly connect to the micro-controller and computer, and possess the advantages of lower power consumption, chip area reduction and stability enhancement. It plays a key component for the application of computer, communication and consumer electronic products.09-30-2010
20120194375ANALOG SIGNAL CONVERSION - An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).08-02-2012
20100013691ANALOGUE TO DIGITAL CONVERTERS - An analogue to digital converter (ADC) is provided which comprises an signal sampling device, a signal comparison device, and a digital signal generator. An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal.01-21-2010
20080316079MULTIPLEXED SIGNAL CONDITIONER - A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal. Mechanical angle of the input signal can be determined based upon the sign of the sine and cosine product vector averages.12-25-2008
20090073017ANALOGUE-DIGITAL CONVERTER USING JOSEPHSON DAC AND METHOD THEREOF - The present invention relates to an analog-to-digital converter (ADC) and an analog-to-digital conversion method employing a Josephson digital-to-analog converter (DAC) into an extremely accurate ADC of a physical metrology grade. The ADC includes: a front end ADC for converting an analog input signal into digital data; the Josephson DAC for receiving the digital data from the front end ADC and converting the received digital data into reference analog voltage; a differential ADC for extracting a difference voltage between a reference analog voltage of the Josephson DAC and an unknown input signal; and a data processor for summing output data of the differential ADC and output data of the front end ADC and outputting the summed result. The present invention enables to realize a highly stable Josephson ADC with little time and low cost, which is more accurate in a long-term as compared to any existing semiconductor measurement unit and has a performance that is rarely changed during a lifespan, by combining a programmable array and an existing semiconductor ADC.03-19-2009
20090073016PIPELINED ANALOG-TO-DIGITAL CONVERTER - One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.03-19-2009
20130187805PIPELINED ANALOG-TO-DIGITAL CONVERTER HAVING REDUCED POWER CONSUMPTION - A pipelined analog-to-digital converter is provided that has advantages of both a high input sample rate as well as low power consumption due to having all but the first pipeline stage operate at a frequency that is a fraction of the input sample rate. The first stage of the pipelined ADC has an internal operating frequency that is the full ADC sample rate, and samples the input signal on the same clock edge for each sample. Subsequent pipeline stages have parallel input sampling circuitry that samples provided input signals at a reduced rate. Since the input sampling circuitry operates at a reduced frequency, power consumption is reduced by those stages. Further, by virtue of sampling the input signal on the same clock edge for each sample, frequency response image generation issues associated with ADC architectures that sample the input signal on more than one clock edge are avoided.07-25-2013
20090315750Signal Processors, Signal Processing Methods, and Digital Filter Configuration Methods - Signal processors, signal processing methods, and digital filter configuration methods are discussed. In one arrangement, a signal processor includes a common node; a plurality of channels, each channel of the plurality comprising an analog filter, a sampler, and a digital filter and each channel of the plurality being configured to generate an intermediate digital signal using an analog signal presented at the common node; and processing circuitry configured form a digital signal representing the analog signal from the intermediate digital signals.12-24-2009
20110032137HIGH-SPEED ANALOG-DIGITAL CONVERTER HAVING A SIGNAL FOLDING STRUCTURE IMPROVED BY REDUCING THE NUMBER OF ELEMENTARY CELLS - The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.02-10-2011
20080284631DIGITIZER FOR A DIGITAL RECEIVER SYSTEM - A digitizer for a digital receiver system includes an input terminal to receive a modulated analog input voltage signal, and an output terminal to provide an output voltage signal being a digital conversion of the input voltage signal. A comparator circuit has an output coupled to the output terminal and includes an operational amplifier having a first input terminal coupled to the input terminal. A threshold generator circuit is between the input terminal and a second input terminal of the at least one operational amplifier, to provide a tunable voltage reference signal thereto. The threshold generator circuit includes a thresholding circuit to determine a threshold voltage value of the modulated analog input voltage signal, and a tunable voltage reference circuit coupled to the thresholding circuit to generate the tunable voltage reference signal as a function of the threshold voltage value of the modulated analog input voltage signal.11-20-2008
20080231488BANDWIDTH MULTIPLICATION FOR A TEST AND MEASUREMENT INSTRUMENT USING NON-PERIODIC FUNCTIONS FOR MIXING - An acquisition apparatus for a test and measurement instrument including a splitter configured to split an input signal into a plurality of split signals, a plurality of oscillators, each oscillator configured to generate a periodic signal, a plurality of combiners, each combiner configured to combine an associated plurality of the periodic signals into an associated signal combination where at least one of the signal combinations is substantially non-periodic. The apparatus also includes a plurality of mixers, each mixer configured to mix an associated split signal and an associated signal combination into an associated mixed signal, a first digitizer configured to digitize an associated split signal, and a plurality of second digitizers, each second digitizer configured to digitize an associated mixed signal.09-25-2008
20110128175Sampling Method For Time-Interleaved Data Converters In Frequency-Multiplexed Communications Systems - A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS06-02-2011
20100302086COMPRESSIVE SENSOR ARRAY SYSTEM AND METHOD - A compressive sensor array (CSA) system and method uses compressive sampling techniques to acquire sensor data from an array of sensors without independently sampling each of the sensor signals. In general, the CSA system and method uses the compressive sampling techniques to combine the analog sensor signals from the array of sensors into a composite sensor signal and to sample the composite sensor signal at a sub-Nyquist sampling rate. At least one embodiment of the CSA system and method allows a single analog-to-digital converter (ADC) and single RF demodulation chain to be used for an arbitrary number of sensors, thereby providing scalability and eliminating redundant data acquisition hardware. By reducing the number of samples, the CSA system and method also facilitates the processing, storage and transmission of the sensor data.12-02-2010
20110001648FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER - A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (01-06-2011
20110001649Differential chopper comparator and A/D converter including the same - A differential chopper comparator compares an input signal voltage and a first voltage, and includes a first capacitor, a second capacitor, and a differential amplification unit including a differential amplification circuit. Either the input signal voltage or the first voltage is applied to one end of the first capacitor via a first switch unit. A fixed voltage is applied to one end of the second capacitor via a second switch unit. Either a non-inverting input terminal or an inverting input terminal of the differential amplification circuit is connected to the other end of the first capacitor, and the other terminal is connected to the other end of the second capacitor. An impedance of the first switch unit side viewed from one end of the first capacitor and an impedance of the second switch unit side viewed from one end of the second capacitor are substantially same.01-06-2011
20090066553INTERFACE FOR MULTIPLE RECEIVERS AND A RESISTOR LADDER - An apparatus is provided for a switching interface for a first receiver, a second receiver, and a resistor ladder. A first terminal is coupled to a first resistor of the resistor ladder. A second terminal is coupled to the first resistor. A third terminal is coupled to a reference voltage. A switch has a first state coupling the first terminal to the third terminal and a second state coupling the second terminal to the third terminal. A first analog-to-digital (A/D) converter is coupled to the resistor ladder and the first receiver. The first A/D is configured to compare a first voltage with a second voltage to determine if the switch is positioned in the first state or the second state. A second analog-to-digital (A/D) converter is coupled to the resistor ladder and the second receiver and also configured to perform a voltage comparison.03-12-2009
20090066554PSEUDO-MULTIPLE SAMPLING METHODS, SYSTEMS AND DEVICES FOR ANALOG-TO-DIGITAL CONVERSION - An analog signal is converted to a digital value having a given number of bits that define given quantization levels, by repeatedly sampling the analog signal at a resolution that is less than that which is defined by the given number of bits. Lower resolution sampling results are thereby obtained. The lower resolution sampling results are summed to obtain the digital value having the given number of bits.03-12-2009
20110025541UNFOLDING VCO-BASED QUANTIZATION CIRCUIT - Apparatus and methods are provided for a voltage-controlled oscillator (VCO) quantization circuit. A quantization circuit comprises an input node for an input signal, a VCO quantizer coupled to the input node, and an output generation module coupled to the VCO quantizer. The VCO quantizer is configured to generate a digital code that is representative of the input signal, wherein the digital code has a first code range. The output generation module generates a digital output value based on the digital code, wherein the digital output value has a second code range being greater than the first code range.02-03-2011
20110115660Method and System Having Adjustable Analog-To-Digital Conversion Levels - An adaptive Analog to Digital Converter (ADC) that adjusts the representation levels used in the conversion process so as to optimize system performance. By establishing system performance criteria by which to select or adjust the signal value range associated with each digital representation and/or the digital representation, substantially fewer bits may be used in the ADC. The systems and methods described herein enable lower-power, smaller form-factor designs as well as very high-speed operation. In particular, this technology may be beneficial for use in communications systems because it enables ADC's to operate at speeds where traditional ADC designs simply cannot.05-19-2011
20100149015FAST, EFFICIENT REFERENCE NETWORKS FOR PROVIDING LOW-IMPEDANCE REFERENCE SIGNALS TO SIGNAL PROCESSING SYSTEMS - Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage.06-17-2010
20100123610DEVICES INCLUDING ANALOG-TO-DIGITAL CONVERTERS FOR INTERNAL DATA STORAGE LOCATIONS - A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.05-20-2010
20100238060HYBRID CONTROL CIRCUIT AND METHOD - A hybrid control circuit and method combine analog circuit and digital circuit to generate digital PWM signals for a multiphase DC-DC converter to generate an output voltage. For current balance control, analog current error signals are generated by the analog circuit from analog phase current signals of the multiphase DC-DC converter and then converted into digital current error signals for calculating the duties of each phase of the multiphase DC-DC converter. Therefore, fewer bit devices can be used to achieve precise current balance control and the size and cost of the circuit can be reduced.09-23-2010
20090219186FILTER CIRCUIT, RECEIVER USING THE SAME, AND FILTERING METHOD USING THE SAME - According to an aspect of the present invention, there is provided a filter circuit including: an ADC that converts a first analog signal into a first digital signal; a digital filter that extracts an interference component from the first digital signal and generates a second digital signal; a DAC that converts the second digital signal into a second analog signal; a delayer that delays the first analog signal based on a delay caused in the second analog signal and generates a delayed first analog signal; a subtractor that subtracts the second analog signal from the delayed first analog signal and generates an output signal; and a controller that controls the digital filter based on a remaining interference component that is remaining in the output signal.09-03-2009
20100182182Pipeline Analog-To-Digital Converter - Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.07-22-2010
20090322578APPARATUS AND METHODS FOR DIRECT QUADRATURE SAMPLING - Methods and apparatuses are provided for performing direct quadrature sampling. One method for sampling quadrature baseband components of a bandpass signal includes receiving a bandpass signal, sampling the bandpass signal using a first sampling clock and a second sampling clock, where the first and the second sampling clocks have the same frequency and are offset by a predetermined phase, and aligning the sampled signals temporally to produce in-phase and quadrature samples corresponding to baseband in-phase and quadrature components. An apparatus for directly sampling baseband quadrature components of a bandpass signal is also presented, which includes a first analog-to-digital converter (ADC) configured to receive a bandpass signal, a second ADC configured to receive the bandpass signal, where the second ADC has a clock having a phase offset with respect to clock signal of the first ADC, and an interpolator coupled to the first ADC configured provide coincident samples.12-31-2009
20100039305COMPARATOR CIRCUIT AND ANALOG DIGITAL CONVERTER HAVING THE SAME - A comparator circuit includes a first comparator comparing an input signal to a first comparison value and generating a first determination signal, a second comparator comparing the input signal to a second comparison value different from the first comparison value and generating a second determination signal, and an output selecting circuit selecting a signal generated first from the first determination signal and the second determination signal, and outputting the selected signal as a determination signal.02-18-2010
20120242525DIFFERENTIAL AMPLIFIER AND ANALOG/DIGITAL CONVERTER - Disclosed herein is a differential amplifier including: an input terminal configured to receive an input signal; an output terminal configured to output an output signal obtained as a result of amplifying the input signal; an amplification part configured to amplify the input signal to generate the output signal; a load circuit which is connected between the amplification part and a power-supply terminal, and is provided with a first-conduction transistor, and a changeover switch configured to switch a connection between a gate electrode of the first-conduction transistor and a drain electrode of the first-conduction transistor to a connection between the gate electrode and the output terminal or vice versa; and a leak cancel switch configured to generate a leak cancel current for reducing an off leak current flowing through the changeover switch.09-27-2012
20100052967Analog to digital converter (ADC) with extended dynamic input rang - A method and apparatus is disclosed to extend a dynamic input range of an analog to digital converter (ADC). A composite ADC may include one or more ADCs. The one or more ADCs compare a signal metric of an analog input signal to quantization levels to produce intermediate digital output signals using one or more non-clipping input values. The composite ADC may select among the one or more intermediate digital output signals based on the signal metric of the analog input signal to produce a final digital output.03-04-2010
20110102228BACKGROUND CALIBRATION OF OFFSETS IN INTERLEAVED ANALOG TO DIGITAL CONVERTERS - A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.05-05-2011
20110095926ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS - An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 04-28-2011
20110074616AMPLIFIER - Briefly, one or more embodiments of an amplifier, including example applications, are described.03-31-2011
20110068965DIGITAL CONTROL SWITCHING POWER SUPPLY UNIT - A digital control switching power supply unit converts an input voltage into a desired output voltage using a digitally controlled pulse width modulation (PWM) signal according to a switching cycle. The power supply unit includes an analog-to-digital converter (ADC). The ADC converts a result of a comparison between an output voltage and a reference voltage to a digital signal during a conversion cycle. The ADC includes a circuit for outputting a phase difference between a switching cycle and the conversion cycle, and a delay circuit. The delay circuit generates a delay output current based on a result of the comparison and the phase difference and determines the conversion time delay according to the delay output current. The delay circuit also generates a delay reference current based on the reference voltage and the phase difference and determining the duration of the conversion cycle according to the delay reference current.03-24-2011
20080246643Technique For Efficient Video Re-Sampling - Efficient re-sampling within a memory occurs by first generating an address request that contains a first portion that identifies a selected data string of interest, and a second portion that identifies a particular group of data values within the selected string. The first portion of the address request is applied to the memory to obtain the selected string of values during a single read operation. The second portion of the read address serves to mask the selected string of values to obtain the particular group of values of interest within the string.10-09-2008
20080246645Folding Circuit - A switchable folding circuit for an analog-to-digital converter is provided. The switchable folding circuit comprises a plurality of circuit stages wherein each of the circuit stages comprises a differential pair, a current source and a switching unit. The differential pair is connected to the current source via the switching unit and the circuit stages are inversely connected to one another.10-09-2008
20080238751DIGITAL RADIO SYSTEM AND METHOD OF OPERATION - A digital radio system comprises a mixer and an analog-to-digital converter communicative coupled to the mixer. The mixer generates an intermediate frequency signal based at least in part upon a radio frequency signal and a local oscillator signal, wherein the intermediate frequency signal comprises a signal of interest having a particular bandwidth. The analog-to-digital converter generates a digital signal by quantizing the intermediate frequency signal using a sampling frequency that is greater than twice the bandwidth of the signal of interest and less than the frequency of the intermediate frequency signal.10-02-2008
20090027250ANALOG TO DIGITAL CONVERSION SYSTEM - While combining AD converters that one is wide band but narrow dynamic range and the other is narrow band but wide dynamic range, it allows settings to provide a common intermediate frequency signal to the AD converters. A first BPF 01-29-2009
20080252506POWER-TO-DIGITAL CONVERTER - A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.10-16-2008
20100321226ANALOG TO DIGITAL CONVERTER WITH AMPLIFIER - An analog to digital converter has an input circuit, a computation circuit, an initialization circuit, and an output circuit. The input circuit is for receiving an analog signal and has a pair of outputs. A computation circuit has a pair of inputs coupled to the pair of outputs. The computation circuit has an amplifier having a pair of complementary outputs (Outp, Outn). The initialization circuit is coupled to the complementary outputs and is for biasing the complementary outputs at a time prior to the computation circuit beginning a computation on the analog signal. The output circuit is coupled to the pair of complementary outputs and provides a digital signal.12-23-2010
20100321225Photo-detector filter having a cascaded low noise amplifier - Method and systems related to obstructing a first predefined portion of at least one defined wavelength of light incident upon a first photo-detector array; and detecting the at least one defined wavelength of light with a photo-detector in a second photo-detector array.12-23-2010
20100321224CIRCUIT CONFIGURATION FOR OBTAINING A BINARY OUTPUT SIGNAL - A circuit configuration for obtaining a binary output signal from a current signal delivered by a magnetic-field sensor comprises a magnetic-field sensor (12-23-2010
20080204294Analog-to-digital converter apparatus, systems, and methods - Various embodiments disclose apparatus, systems, and methods operating with a first circuit branch with transistors coupled in series between first and second supply nodes, and a second circuit branch with second transistors coupled in series between the first and second supply nodes. The second circuit branch may include a resistive unit coupled in series with the second transistors. The first and second circuit branches may receive analog information and to provide digital output information. The digital output information may include output values based on a relationship between a voltage across the first resistive unit and a voltage difference between first and second components of the analog input information. Other embodiments disclose additional apparatus, systems, and methods.08-28-2008
20080204297Analog front-end circuit and electronic instrument - An analog front-end circuit includes an analog processing circuit, an A/D converter, a target register in which a lower limit target value of an input image signal is set, and a calculation circuit. The analog processing circuit includes an offset control circuit which performs offset control based on an offset control value set in an offset control register. The calculation circuit monitors the A/D-converted value in a lower limit value output period when the A/D-converted value corresponding to a lower limit value of an input range is output from the AID converter, and sets the offset control value that causes the A/D-converted value to become closer to the lower limit target value set in the target register in the offset control register.08-28-2008
20080204295Method for Operating a Digital Sensor - The sensor has only a first contact (08-28-2008
20100283652SEMICONDUCTOR DEVICE AND DIFFERENTIAL AMPLIFIER CIRCUIT THEREFOR - A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit. The switching network is further arranged to operate in second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the sampled input voltage signals, and the second pair of capacitors are operably coupled in parallel between the outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.11-11-2010
20110115661ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) system and method. The ADC system includes a digital control circuit, an amplifier, a capacitor, and an evaluation circuit. The digital control circuit is configured to sequentially configure the ADC system in a first configuration and a second configuration to derive a digital representation of an analog signal value. The amplifier circuit includes an amplifier input terminal and an amplifier output terminal. The capacitor has a first capacitor terminal coupled to the amplifier input terminal in the first and second configurations of the ADC system. The capacitor further has a second capacitor terminal coupled to the amplifier output terminal in the first configuration of the ADC system. The evaluation circuit is configured to provide a first digital code to represent a first voltage level at the amplifier output terminal in the first configuration of the ADC system. The second capacitor terminal in the second configuration of the ADC system is coupled to a reference voltage potential selected according to the first digital code.05-19-2011
20110133971ANALOG-TO-DIGITAL CONVERTER - An SAR ADC includes a digital-to-analog converter, a first comparator that compares an input analog signal with a reference analog signal, a second comparator that compares an input analog signal with a reference analog signal, a selection circuit that selects one of comparison results of the first comparator and the second comparator, and a control circuit that changes the multibit digital signal sequentially based on the selected comparison result in a plurality of steps so that the reference analog signal becomes closer to the input analog signal, and the control circuit controls the selection circuit to select the comparison result of the first comparator up to an intermediate step on the way of the plurality of steps and to select the comparison result of the second comparator after the intermediate step, and changes the bit value of the multibit digital signal according to the non-binary algorithm.06-09-2011
20110133972GAMMA VOLTAGE GENERATOR AND DAC HAVING GAMMA VOLTAGE GENERATOR - A gamma voltage generator includes an RGB common gamma voltage generation section configured to generate RGB common gamma voltages using corresponding gamma reference voltages among a plurality of gamma reference voltages; and at least two of an RG gamma voltage generation section configured to generate RG gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, an R gamma voltage generation section configured to generate R gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, a G gamma voltage generation section configured to generate G gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, and a B gamma voltage generation section configured to generate B gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages.06-09-2011
20110133970MULTIPATH AMPLIFIER - Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths.06-09-2011
20100214146ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD - The A/D conversion apparatus includes an A/D converter for converting a potential difference between a reference voltage input and a voltage input to be measured to a digital signal and outputting the digital signal; a first switch connected between a voltage source to be measured and the voltage input to be measured; a first sampling capacitor having a first end connected to the voltage input to be measured and to a first end of the first switch, and having a second end connected to a reference power source; a second switch connected between a reference voltage source and the reference voltage input; a second sampling capacitor having a first end connected to the reference voltage input and to a first end of the second switch, and having a second end connected to the reference power source; and an impedance adjusting circuit, which is connected between the reference voltage source and a second end of the second switch, for changing, in stepwise fashion, impedance between the reference voltage source and the second end of the second switch.08-26-2010
20100214144ERROR CORRECTION METHOD AND APPARATUS - A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.08-26-2010
20080218395ANALOG-DIGITAL CONVERTING APPARATUS AND RADIO COMMUNICATION TERMINAL - An analog-digital converting apparatus includes: an analog-digital converting unit that performs a conversion from an analog input signal into a digital output signal; a buffer unit that temporary stores the digital output signal for a plurality of samples and outputs the samples in time-series; a clipping detecting unit that detects a first sample having a signal value corresponding to a clipping level of the analog-digital converting unit from among the samples of the digital output signal; and an interpolating unit that rewrites the signal value of the first sample stored in the buffer unit into an estimated signal value that is obtained by estimating a signal value at a time corresponding to a time of the first sample by an interpolation using at least one of (1) a set of second and third samples that are samples previous to the first sample and (2) a set of fourth and fifth samples that are samples subsequent to the first sample.09-11-2008
20100066580Nonlinear Mapping in Digital-to-Analog and Analog-to-Digital Converters - In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.03-18-2010
20100194616Systems and Methods for Synchronous, Retimed Analog to Digital Conversion - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.08-05-2010
20100194615Apparatus For Converting MEMS Inductive Capacitance - An apparatus for converting MEMS inductive capacitance to digital is provided, for converting the induced analog voltage of MEMS element into digital signal. The apparatus includes an ADC, a reference voltage circuit and a controller. With the integral circuit and the comparator of the ADC and the reference voltages generated by the reference voltage circuit, the apparatus of the present invention uses the switch signals generated by the controller to generate digital signals. The present invention can also be integrated with MEMS element into a single chip to achieve single-chip MEMS.08-05-2010
20110187573TIME-MULTIPLEXED RESIDUE AMPLIFIER - A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.08-04-2011
20100026544A-D CONVERTER - Provided is an AD converter that converts an input analog signal into a digital signal, comprising an integrator that sequentially integrates signal levels of the analog signal to obtain an integrated waveform, and outputs the integrated waveform; a digital converting section that detects, with prescribed units of temporal resolution, a transition timing, which is a timing at which a magnitude relationship between a signal level of the integrated waveform and a prescribed reference value transitions to a predetermined state; a feedback section that controls the signal level of the integrated waveform with a control period longer than a unit of temporal resolution, according to a result of the detection by the digital converting section; and a signal processing section that generates the digital signal based on the detection result by the digital converting section.02-04-2010
20100026543ANALOG TO DIGITAL CONVERTER - An analog to digital converter having an input stage amplifier array, an input stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies the difference between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The input stage voltage divider array averages every two adjacent amplified differences to generate a plurality of average signals. The comparator array compares the average signals with a threshold value and outputs the compared results to the encoder for digital data representing the value of the input signal.02-04-2010
20090174588FOCAL PLANE ARRAY WITH SERIAL, VARIABLE BIT WIDTH ANALOG TO DIGITAL CONVERTER - A method and apparatus for a focal plane array with serial, variable bit width analog to digital converter. The focal plane array includes a plurality of pixels and a dynamically reconfigurable analog to digital converter. The controller determines a number of digital output bits required to generate digital output at a selected conversion resolution. A sample and hold circuit holds an analog voltage from a pixel to form a captured analog signal. A one-bit converter stage processes an instance of a captured analog signal to generate an output bit. The controller iteratively processes a residue voltage through the one-bit converter stage a number of times required to generate the number of digital output bits to form a digital output with the user defined conversion resolution.07-09-2009
20100066579GRAY CODE CURRENT MODE ANALOG-TO-DIGITAL CONVERTER - One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply.03-18-2010
20120098690HIGH FREQUENCY SIGNAL COMPARATOR FOR SHA-LESS ANALOG-TO-DIGITAL CONVERTERS - A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.04-26-2012
20110148682PREDICTIVE ANALOG-TO-DIGITAL CONVERTER AND METHODS THEREOF - Predictive Analog-to-Digital Converter system in one embodiment includes a sampling section producing a sampled analog input signal with a first summer section combining the sampled analog input signal and an analog prediction signal to produce an analog prediction error signal. There is at least one error analog-to-digital convertor digitizing the analog prediction error signal, wherein a digital error signal output from the error analog-to-digital convertor is one of a full bitwidth error signal during an over-range condition else a lower bitwidth error signal. A second summer is coupled to the digital error signal output and a digital prediction signal, and generates a full bitwidth digital output signal. A feedback section is coupled to the digital output signal and providing the digital prediction signal and the analog prediction signal.06-23-2011
20120306679N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT - The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DAC12-06-2012
20100033360A LOW COST ANALOG TO DIGITAL CONVERTER AND A METHOD FOR CONVERTING AN ANALOG SIGNAL TO A DIGITAL SIGNAL - The present invention relates to a low cost analog to digital converter (ADC) and a method for converting an analog signal to a digital signal. The method includes the steps of: outputting a pulse modulation signal according to a digital value; performing a low-pass filtering to the pulse modulation signal to obtain a pulse averaged voltage; mixing a first proportion of the pulse averaged voltage and a second proportion of a voltage under test to obtain a composite voltage; comparing the composite voltage with a threshold voltage and adjusting the first digital value such that the composite voltage approaches the threshold voltage; and performing a complement operation to the digital value to obtain an analog to digital value corresponding to the voltage under test.02-11-2010
20120068870Systems and Methods for Semi-Independent Loop Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.03-22-2012
20110050476INTEGRATOR, RESONATOR, AND OVERSAMPLING A/D CONVERTER - An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.03-03-2011
20110050475ANALOG TO DIGITAL CONVERTER WITH DIGITAL FILTER - Disclosed herein are devices, methods, and techniques including analog to digital converters having at least one digital filter.03-03-2011
20090315749FREQUENCY COUNTER BASED ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) is provided. The ADC includes a variable oscillator, a frequency divider, a clock circuit, and a counter. The variable oscillator is coupled to a sensor and configured to generate an oscillating signal based on a measurement generated by the sensor. The frequency divider is coupled to the variable oscillator and configured to divide a frequency of the oscillating signal. The clock circuit is configured to generate a clock signal at a defined frequency. The counter is coupled to the frequency divider and to the clock and is configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.12-24-2009
20100127909COMMUNICATION DRIVER - A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.05-27-2010
20100097258APPARATUS COMPRISING FREQUENCY SELECTIVE CIRCUIT AND METHOD - An apparatus, having as an input an analog signal, is provided. The apparatus comprises a first circuit comprising an impedance transferring circuit configured to band pass filter the input signal, obtaining a filtered signal; the impedance transferring circuit comprising: a transconductance amplifier (04-22-2010
20120001786DEVICE FOR THE ANALOG/DIGITAL CONVERSION OF SIGNALS IN A LARGE DYNAMIC RANGE - A device for expanding the dynamic range of a broadband analog/digital converter is provided. The device comprises a splitter module configured to split an analog input signal into a first analog signal output on a first signal branch, and a second analog signal output on a second signal branch. The device further comprises a first analog/digital converter configured to digitize the first analog signal into a first digital signal, a second analog/digital converter configured to digitize the second analog signal into a second digital signal, and a first switching module configured to switch one of the first signal branch and the second signal branch to an output of the apparatus. The device further comprises a first regulating module, disposed between the second analog/digital converter and the first switching module, wherein the first regulating module is configured to adaptively match amplitudes of the second digital signal to amplitudes of the first digital signal. The device further comprises a delay module, disposed between the first analog/digital converter and the first switching module, wherein the delay module is configured to delay the first digital signal by a time corresponding to a processing time of the first regulating module, and wherein the delay module provides the delayed first digital signal as a reference signal to the first regulating module. The first regulating module comprises an adaptive filter configured to filter the second digital signal, wherein filter coefficients of the adaptive filter are configured to be matched in a cyclical manner by the reference signal, such that the filtered second digital signal corresponds to the reference signal in phase and amplitude.01-05-2012
20080204296Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS - In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital controllers.08-28-2008
20120007761ANALOG-TO-DIGITAL CONVERSION APPARATUS, ANALOG-TO-DIGITAL CONVERSION METHOD, AND ELECTRONIC DEVICE - An AD conversion apparatus includes a shift signal generating portion configured to generate n shift signals (n is a natural number greater than one) of which amplitudes are different from each other; a shift signal controlling portion configured to control the shift signal generating portion; a compounding portion configured to compound input analog signal and the n shift signals sequentially into n first signals; an AD converting portion configured to execute AD conversion to convert the n first signals into n second signals; and a signal processing portion configured to calculate an average of the n second signals to generate output digital signal.01-12-2012
20080198057Analog-to-digital converting circuit - Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.08-21-2008
20100194617TRANSIMPEDANCE AMPLIFIER AND ANALOG-DIGITAL CONVERTER CIRCUIT - A transimpedance amplifier according to an exemplary aspect of the present invention includes a first terminal supplied with a first power supply voltage, and a second terminal supplied with a second power supply voltage having a potential lower than that of the first power supply voltage. The transimpedance amplifier outputs a voltage signal that is converted into a binary signal of one of the first power supply voltage and the second power supply voltage, based on an input analog current signal. This makes it possible to reduce a conversion error.08-05-2010
20120206286ADC WITH ENHANCED AND/OR ADJUSTABLE ACCURACY - An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.08-16-2012
20120206285HALF-BANDWIDTH BASED QUADRATURE ANALOG-TO-DIGITAL CONVERTER - A half-bandwidth based quadrature analog-to-digital converter (ADC), which includes in-phase circuitry, quadrature-phase circuitry, and digital complex processing circuitry is disclosed. The in-phase circuitry includes an in-phase pair of ADCs, which provide an in-phase pair of sub-quadrature output signals, based on an analog in-phase input signal. Similarly, the quadrature-phase circuitry includes a quadrature-phase pair of ADCs, which provide a quadrature-phase pair of sub-quadrature output signals based on an analog quadrature-phase input signal. The digital complex processing circuitry combines, filters, and restructures the in-phase pair of sub-quadrature output signals and the quadrature-phase pair of sub-quadrature output signals to provide a digital in-phase output signal and a digital quadrature-phase output signal. Each of the in-phase pair of ADCs has about an ADC bandwidth. The in-phase circuitry has an input bandwidth, which is about equal to two times the ADC bandwidth in one embodiment of the in-phase circuitry.08-16-2012
20120105262MULTICHANNEL DIGITIZER AND METHOD OF DIGITIZING - A multichannel digitizer and method of digitizing are provided. One digitizer includes an analog to digital convertor (ADC) having a plurality of channels receiving input analog signals; an operational amplifier in each channel and a comparator connected to the operational amplifier. The ADC further includes a logic circuit in each channel connected to the comparator and configured to generate an output based on a comparator signal received from the comparator. The ADC also includes a ramp generator connected to the plurality of channels and configured to provide a time varying reference signal.05-03-2012
20120154192VOLTAGE CONTROLLED OSCILLATOR (VCO) BASED ANALOG-DIGITAL CONVERTER - A signal receiver contains a VCO-based Analog-to-Digital Converter. As a result, some building blocks can be migrated into the digital domain.06-21-2012
20120105263ANALOG TO DIGITAL CONVERTER - An analog to digital converter includes a dielectric substrate, an analog input wire, and digital output wires, with a metal insulator extending over the digital output wires. The analog input wire can be in proximity to the dielectric substrate and can generate heat when an electric current flows through the analog input wire. The digital output wires can also be in proximity to the dielectric substrate. The metal insulator can have a phase transition temperature above which the metal insulator is electrically conductive to short circuit at least one of the digital output wires in contact with a metal insulator portion above the phase transition temperature. The digital output wires can be arranged at predetermined distances from the analog input wire such that output wires have varying short circuit thresholds.05-03-2012
20110090107TIME-INTERLEAVED-DUAL CHANNEL ADC WITH MISMATCH COMPENSATION - Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital converters (ADCs) for intermediate frequency architectures and dual channel ADCs for direct conversion architectures. Here, similarities between TI ADCs and dual channel ADC were recognized, and an ADC that has the capability of operating as a TI ADCs and dual channel ADC is provided. This allows designer to have greatly increased flexibility during the design process which can greatly reduce design costs, while also allowing the manufacturer of the ADC to realize a reduction in its operating costs.04-21-2011
20090021411A/D CONVERTER - An A/D converter comprises a ramp voltage generation circuit, a voltage comparison circuit comprising an arithmetic unit comparing an analog voltage to be converted with a reference voltage showing the voltage change of a ramp voltage, and changing an output when the reference voltage equals the analog voltage, a counter counting and outputting a digital value corresponding to the reference voltage, a latch circuit latching and outputting the digital value when the output of the voltage comparison circuit changes, an averaging process circuit to obtain an average noise voltage, a target noise voltage setting circuit setting a target noise voltage, and a control circuit adjusting at least one of a counting start timing of the counter with respect to a control reference timing, or the criterion level of the reference voltage at the counting start timing, based on a difference between the average noise voltage and the target noise voltage.01-22-2009
20100245147Delta-sigma A/D converter - An object of the present invention is to provide a highly accurate delta sigma A/D converter. Disclosed is a delta sigma A/D converter including: a first integration circuit to generate a first signal on the basis of an input signal and a first feedback signal from an output side; a first signal conversion circuit to convert the first signal into a first converted signal; a loop delay compensation circuit to generate a compensation signal and then to output the compensation signal in response to a second feedback signal fed back from the output side at a timing earlier than that of the first feedback signal; an adder circuit to add the first converted signal and the compensation signal; and a comparator to generate a digital signal on the basis of an output signal from the adder circuit. The loop delay compensation circuit includes a compensation signal conversion circuit to generate the compensation signal. The compensation signal conversion circuit and the first signal conversion circuit have the approximately same rate of change in conversion coefficient depending on a temperature.09-30-2010
20100245149COMPARISON CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION DEVICE - A comparison circuit comprising: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.09-30-2010
20100245148ANALOG-DIGITAL CONVERTER AND CORRESPONDING SYSTEM AND METHOD - An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.09-30-2010
20120313802SIGNAL CONVERSION - An approach to signal conversion adapts the signal conversion process, for example, by adapting or configuring signal conversion circuitry, according to inferred characteristics (e.g., probability distribution of value) of a signal being converted. As an example, an analog-to-digital converter (ADC) may be adapted so that its accuracy varies across the range of possible input signal values in such a way that on average the digital signal provides a higher accuracy than had the accuracy remained fixed. In another example, models (and corresponding inference circuitry) of both an input signal process and of a quantization process are used to improve signal conversion accuracy.12-13-2012
20120313801AD CONVERTER - To provide a highly accurate and small AD converter. The AD converter converts an analog voltage Vin into a digital code DC of N-bit, and includes memory blocks MB12-13-2012
20100271248RAMP WAVE OUTPUT CIRCUIT, ANALOG/DIGITAL CONVERSION CIRCUIT, AND CAMERA - A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.10-28-2010
20100207800Analog-to-Digital Conversion Method Using RC Time Constant Calibrator and Analog-to-Digital Converter Therefor - An analog-to-digital conversion method using an RC time constant calibrator is provided. The method includes the operations of comparing a crossing time point at which a first reference signal and a second reference signal cross each other with a target time point and calibrating an RC time constant according to a result of the comparison. A length of time until the crossing time point at which a first analog signal and a second analog signal cross each other is counted based on a calibrated RC time constant. The counted value is output.08-19-2010
20100079326Method and Circuit for Digitizing with Improved Resolution - Embodiments of the invention relate to a method and a corresponding circuit for digitizing an analog signal. Applying a nonlinear function to the signal, digitizing the signal and applying the inverse of the nonlinear function to the digital samples improve the digital samples.04-01-2010
20120212362SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP08-23-2012
20120161999COMPLEX SECOND-ORDER INTEGRATOR AND OVERSAMPLING A/D CONVERTER HAVING THE SAME - An oversampling A/D converter with a few operational amplifiers is configured using a complex second-order integrator including first and second second-order integrators and first and second coupling circuits configured to couple these integrators together. Each of the second-order integrators includes an operational amplifier, four resistance elements, and three capacitance elements. The first coupling circuit cross-couples one of two serially-connected capacitance elements inserted between the inverted input terminal and output terminal of the operational amplifier in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements. The second coupling circuit cross-couples the other capacitance element in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements.06-28-2012
20120161998RAMP SIGNAL GENERATOR, ANALOG TO DIGITAL CONVERTER, AND IMAGE SENSOR - Provided is an analog-to-digital (A/D) converter that may be used in an image sensor and a ramp signal generator that is used in an A/D converter. The ramp signal generator may generate a ramp signal and a reference voltage signal that include noise that has same noise characteristics that are input into the ramp signal, such that the signal to noise ratio (SNR) is improved and the image quality is also improved.06-28-2012
20090058706Digital Radio System and Method of Operation - A digital radio system comprises a mixer and an analog-to-digital converter communicative coupled to the mixer. The mixer generates an intermediate frequency signal based at least in part upon a radio frequency signal and a local oscillator signal, wherein the intermediate frequency signal comprises a signal of interest having a particular bandwidth. The analog-to-digital converter generates a digital signal by quantizing the intermediate frequency signal using a sampling frequency that is greater than twice the bandwidth of the signal of interest and less than the frequency of the intermediate frequency signal.03-05-2009
20090058705Satellite Radio Navigation Receiver - In a satellite radio navigation receiver receiving a transmitted radio navigation signal, a method of removing I/Q-mismatches in the received signal, comprising: resolving the received signal into I and Q signal component, and providing them as inputs to a demixing stage which removes unwanted signals, the demixing stage including first and second cross-coupled adaptive filters, whose coefficients are updated by the outputs of the demixing stage, the outputs of the demixing stage representing an IQ mismatch corrected signal. The coefficients are updated only by the polarity values of the outputs, resulting in great simplification. The receiver may be a zero-IF or low-IF receiver, and may operate on time domain or frequency domain signals.03-05-2009
20090102692Clock Generator - The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the “clock-to-Q period”) is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal. The present invention provides a data capture circuit with matched latch to address this issue, particularly a first latch having an input for receiving a data input signal; a first sense amplifier having an input coupled to an output of the first latch; a second latch having an input coupled to the output of the first sense amplifier and an output providing a first data output; and a clock generator, the clock generator comprising: a third latch having an input for receiving a first clock signal; a second sense amplifier having an input coupled to an output of said third latch; and a fourth latch having an input coupled to an output of said second sense amplifier and an output providing a first adjusted clock signal, wherein said first and third latches are substantially the same, the first and second sense amplifier are substantially the same and the second and fourth latches are substantially the same.04-23-2009
20120075136A/D CONVERSION DEVICE - An A/D conversion device has first to third pulse delay circuits, first to third pulse passage stage detection circuits, a time output circuit, and an output circuit. Each of the first to third pulse delay circuit has multiple stages of delay units which are connected together and delay a first to a third pulse signals, respectively. Each of the first to third pulse passage stage detection circuit detects a first to a third number of stages, respectively. The time output circuit outputs a time signal. The output circuit outputs the digital value corresponding to the third number of stages.03-29-2012
20120075135Analog-Digital Conversion - In one embodiment, a method includes receiving a first analog signal at a first input; receiving a second analog signal at a second input; mixing the first analog signal with a first oscillator signal having a first frequency; mixing the second analog signal with a second oscillator signal having a second frequency; converting a sum signal to a digital signal; generating a first control signal based on a first digital value of a first function and the digital signal; and generating a second control signal based on a second digital value of a second function and the digital signal.03-29-2012
20120075134System and Method for Compressive Sensing - The present invention provides a system for use with an input signal and a clock signal. The system includes a physical random interval generator, a sampling analog-to-digital converter (ADC), a timing signal generator and a reconstructor. The physical random interval generator can generate a random output signal. The ADC can output a sampled output signal based on the input signal and the random output signal. The timing signal generator can output a timing signal based on the clock signal and the random output signal. The reconstructor can reconstruct an information signal based on the sampled output signal and the timing signal.03-29-2012
20120182167BUFFER TO DRIVE REFERENCE VOLTAGE - Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.07-19-2012
20120182169DATA CONVERTER - A data converter includes a signal input port, a processing unit, and an output port. The signal input port includes a number of ports for connecting to corresponding ports of an electronic device and receiving waveform signals from the electronic device. The processing unit includes a port detection module for detecting which port of the signal input port is receiving the waveform signals and a data conversion module including a number of conversion sub-modules, each conversion sub-module corresponds to one port of the signal input port. When the port detection module detects the port receiving the waveform signals, the conversion sub-module corresponding to the detected port is enabled and converts the waveform signals to digital data. Then the output port outputs the digital data to a computer, and the communication state of the port of the electronic device is analyzed via the computer based on the digital data.07-19-2012
20120182168ACTIVE RC RESONATORS WITH ENHANCED Q FACTOR - An active RC resonator includes a first operational amplifier having first and second inputs and first and second outputs, a second operational amplifier having first and second inputs and first and second outputs, a first resistor coupled between the first input of the first operational amplifier and the second output of the second operational amplifier, a second resistor coupled between the second input of the first operational amplifier and the first output of the second operational amplifier, a third resistor coupled between the first output of the first operational amplifier and the first input of the second input of the second operational amplifier, a fourth resistor coupled between the second output of the first operational amplifier and the second input of the second operational amplifier, and at least one of 1) a first capacitor coupled between the first input of the first operational amplifier and the first output of the second operational amplifier, and a second capacitor coupled between the second input of the first operational amplifier and the second output of the second operational amplifier, 3) a third capacitor coupled between the second output of the first operational amplifier and the first input of the second operational amplifier, and a fourth capacitor coupled between the first output of the first operational amplifier and the second input of the second operational amplifier.07-19-2012
20100259433Signal Processing System - A digital signal processor that is required to process a large number of narrowband analog input or output signals. Analog processing is performed to combine multiple analog signals together (with non-overlapping frequency bands) into a composite signal which is fed to a single analog to digital converter. These signals come from different sources and would in a conventional implementation use individual converters. Analog signal processing is used outside of the digital signal processor and digital processing is used inside to enable the original analog signals to be reconstructed in the digital domain in the same format as if individual converters have been used. A similar technique can be applied to digital to analog conversion interfaces where a digital combining operation is performed to combine digital sub-band signals into a single composite signal, prior to input to a single digital-to-analog (DAC) converter for conversion to the analog domain and subsequently to an analog splitter device for separation into a plurality of analog signals. Hence, the technique can be implemented in both transmitter and receiver systems.10-14-2010
20120229319A/D CONVERTER, A/D CONVERSION METHOD, AND PROGRAM - An A/D converter switches resolution of m bits to resolution of n bits smaller than the m bits at a predetermined time.09-13-2012
20120229318DEVICES AND BANDPASS FILTERS THEREIN HAVING AT LEAST THREE TRANSMISSION ZEROES - A bandpass filter comprises a first capacitor, a second capacitor, a third capacitor and at least two resonators. The first and second capacitors are coupled in parallel with each other, and each of the first and second capacitors includes an input. The third capacitor is coupled between the first capacitor and the second capacitor at their respective inputs. The at least two resonators are coupled in parallel with the first capacitor and the second capacitor and are positioned adjacent to each other at a distance such that the at least one component of the resonators are electromagnetically coupled together to provide three (3) transmission zeros.09-13-2012
20080297391Optical quantizing unit and optical a/d converter - An optical quantizing unit includes an optical divider dividing 1st optical pulses to be quantized and sending the divided 1st optical pulses into a plurality of paths; a plurality of optical filters passing with different transmittances the divided 1st optical pulses; and an optical threshold filter sequentially receiving the 1st optical pulses, and sending 2nd optical pulses when light intensities of the 1st optical pulses are above a preset threshold value.12-04-2008
20080297392SIGNAL PROCESSING METHOD AND DEVICE, AND ANALOG/DIGITAL CONVERTING DEVICE - The first and second time-domain signals are received, and a difference between the pulse width of the first time-domain signal and the pulse width of the second time-domain signal within a unit time for carrying one item of analog signal information is obtained. The obtained difference is treated as positive information if the pulse width of the first time-domain signal is greater than the pulse width of the second time-domain signal, or as negative information if the pulse width of the first time-domain signal is smaller than the pulse width of the second time-domain signal.12-04-2008
20120262322DIGITAL READOUT METHOD AND APPARATUS - Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.10-18-2012
20120319885SYSTEM FOR PROCESSING DATA STREAMS - A system for processing data streams or signals includes a wave-front multiplexer configured to process first and second input signals into first and second output signals each carrying information associated with the first and second input signals, a first processing unit configured to process a third input signal carrying information associated with the first output signal into a third output signal, a second processing unit configured to process a fourth input signal carrying information associated with the second output signal into a fourth output signal, and a wave-front demultiplexer configured to process fifth and sixth input signals into fifth and sixth output signals each carrying information associated with the fifth and sixth input signals. The fifth input signal carries information associated with the third output signal, and the sixth input signal carries information associated with the fourth output signal.12-20-2012
20120319884CONVERTING AND TRANSMITTING A MAGNETIC RESONANCE DETECTION SIGNAL - A system and method for converting an analog detection signal of a magnetic resonance detection coil into a digital detection signal and for transmitting the detection signal to an evaluating device. In an embodiment, the detection signal is digitized by an analog-to-digital converter, decimated by a decimation filter, transmitted through a transmission route, then equalized by an equalizing filter.12-20-2012
20110037634Device and Method for Scanning Multiple ADC Channels - An analog to digital converter has an input for coupling to multiple channels having analog signals. The analog to digital converter converts the analog signals on such channels to provide a digital output. A memory device has an enable bit for each of the multiple channels and a current channel register. An interface coupled to the memory device and current channel register selects a next channel for converting by the analog to digital converter, skipping channels that are not enabled.02-17-2011
20120319883TIME-TO-DIGITAL CONVERTER - Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.12-20-2012
20120268299ROBUST GAIN AND PHASE CALIBRATION METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.10-25-2012
20120081246COMPLEX ANALOG TO DIGITAL CONVERTER (CADC) SYSTEM ON CHIP DOUBLE RATE ARCHITECTURE - A Complex Analog to Digital Converter System on Chip (CADC SoC) implemented into a microcircuit system is provided. A series of stagger clock signals can be fixed on either a rising or falling edge of the system clock and a plurality of A/D converters can be grouped by sets (i.e. odd and even) and assigned to odd or even stager clocks. A complex I&Q data manager is provided for controlling the system. A clock management system is responsive to an external signal to select from a set of stagger clock settings, thereby improving anti-alias performance.04-05-2012
20100231430AMPLIFIER AND ANALOG/DIGITAL CONVERTER - An amplifier that is operated between first and second power supplies includes a transistor pair having control terminals to which input signals are input, a load resistor pair that is provided between each transistor of the transistor pair and the first power supply, a constant current source that is provided between the second power supply and the transistor pair, and a first switch that is connected with the constant current source in series between the second power supply and the transistor pair, the first switch being turned on or off in accordance with a clock signal.09-16-2010
20120092202ANALOG TO DIGITAL CONVERTER - An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.04-19-2012
20090096654Intelligent Electronic Device Having Circuitry for Noise Reduction for Analog-to-Digital Converters - An intelligent electronic device (IED), e.g., an electrical power meter, having circuitry for an input structure of an analog-to-digital converter (ADC) that reduces noise of a signal from a sensor in the device, resulting in a highly accurate power measurement, is provided. The circuitry includes a first single-ended analog-to-digital converter with an input from a voltage signal and a second single-ended analog-to-digital converter with an input that is the reference voltage used by the voltage signal. A programmable device subtracts the digital output of the second single-ended analog-to-digital converter from the digital output of the first single-ended analog-to-digital converter to produce a digital result of the voltage signal that is free from common-mode noise.04-16-2009
20120326908COMMUNICATION SYSTEM FOR FREQUENCY SHIFT KEYING SIGNAL - A communication system includes a time-to-digital converter, a digital low-pass filter, and a digital signal processor. The time-to-digital converter receives an in-phase signal of a frequency-shift keying signal and to generate a digital signal according to the in-phase signal. The digital low-pass filter receives the digital signal and to generate a filtered signal including N continuous words according to the digital signal. The digital signal processor divides up the N continuous words into N/2 word sets in order, wherein each of the N/2 word sets includes a first word and a second word, and if a difference between the first word and the second word meets a predetermined condition, the digital signal processor generates an output data and an output clock according to all the first words and the second words that have difference which meets the predetermined condition.12-27-2012
20120139771DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.06-07-2012
20120139770CURRENT SENSING CIRCUIT - A current sensing circuit including a current sensing unit, a feedback control unit, and a digital output unit is provided. The current sensing unit senses a current and generates a pulse signal according to at least one reference signal and at least one feedback signal. The feedback control unit is coupled to the current sensing unit and generates the at least one feedback signal according to a clock signal and the pulse signal. The digital output unit is coupled to the current sensing unit and outputs a digital signal according to the pulse signal. The digital output unit counts an amount of pulses of the pulse signal in a predetermined time period to output the digital signal, wherein the amount of pulses is positively correlated with a value of the current.06-07-2012
20130009800DUAL-MODE COMPARATOR AND ANALOG TO DIGITAL CONVERTER HAVING THE SAME - A dual-mode comparator may include an object voltage input unit that generates a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage, a current mirror unit that performs a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal, a bias unit that generates a bias current corresponding to a sum of the first current and the second current, and a mode switching unit that controls the current mirror unit to have a first structure in an auto-zero mode and that controls the current mirror unit to have a second structure in a comparison mode.01-10-2013
20130021187Systems and Methods for ADC Based Timing and Gain Control - Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing circuit is discussed that includes: an analog to digital converter circuit, a target response circuit, and a timing circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples synchronous to a sampling phase. The sampling phase corresponds to a phase feedback. The target response circuit is operable to provide an expected output corresponding to a known input. The timing circuit is operable to generate the phase feedback based at least in part on values derived from the expected output.01-24-2013
20080238753PIPELINED ANALOG-TO-DIGITAL CONVERTER HAVING A POWER OPTIMIZED PROGRAMMABLE DATA RATE - The present invention is related to a pipelined analog-to-digital converter (ADC) utilizing a power distribution scheme selectively delivering both constant and variable reference currents in selected proportions to a plurality of stages and operational transconductive amplifiers (OTAs). This permits the ADC to maintain an optimized speed over power consumption ratio over a wide data rate range. Since the invention is capable of supporting a large operating range while maintaining very low power consumption relative to the data rate, the pipelined ADC in accordance with the present invention is particularly adaptable to a large number of applications.10-02-2008
20080231489Analog-to-digital converter system with increased sampling frequency - The present invention is an improvement in sampling a high frequency input analog signal and converting it to a digital output signal. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier.09-25-2008
20130169463INTERLEAVED ANALOG TO DIGITAL CONVERTER WITH DIGITAL EQUALIZATION - An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer. A residual distortions calculator of the residual distortions reduction unit, is responsive to measured frequency responses from the composite ADC and a current set of equalizer coefficients applied to the equalizer, to calculate residual frequency distortions that should have been expected to appear in the output signal of the ADC system if the current equalizer coefficients remain applied to the equalizer.07-04-2013
20080224913DATA PROCESSING METHOD, DATA PROCESSING DEVICE, SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND ELECTRONIC DEVICE - A data processing device includes a comparing unit that compares a reference signal and respective processing object signals, a count-period control unit that determines a count period to perform count processing, a count unit that performs the count processing in the count period designated by the count-period control unit, stores a count value, applies the count processing to both a subtraction element and an addition element in an identical mode of any one of an up-count mode and a down-count mode, and starts the count processing for a following processing object signal using a count value for a preceding processing object signal as an initial value, and a correcting unit that corrects digital data of a multiply-accumulate result of the plural processing object signals to digital data in which a count value is corrected.09-18-2008
20080224912Median and mean coherent filter and method for eliminating noise in touch screen controller - A touch screen system includes a touch screen assembly (09-18-2008
20110260901Variable Gain Amplifier - A variable gain amplifier includes an integrator having an input, an output and a feedback loop connected between the input and output, a plurality of input chains connected in parallel between the amplifier input and the input of the integrator, each input chain including a resistor and a first switch and a plurality of second switches, each second switch connected between an intermediate node between the resistor and first switch of a respective input chain and the feedback loop of the integrator, wherein the resistance of the resistors in the input chains is scaled by a scaling factor with respect to one another and the on-resistances of the first and second switches connected to each intermediate node are scaled by the corresponding scaling factor.10-27-2011
20110273318Analog to digital converter (ADC) with comparator function for analog signals - This disclosure relates to analog to digital converter (ADC) component with a comparator function for analog signals.11-10-2011
20130176156COMPAPATOR AND ANALOG-TO-DIGITAL CONVERTOR - A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.07-11-2013
20130176157METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD - The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-07-11-2013
20080252507Integrating Analog to Digital Converter - An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (10-16-2008
20080198056Analog to digital converter - An analog to digital converter is provided in which the outputs of first and second digital to analog converters DAC08-21-2008
20080198055Pipeline type analog-digital converter having redundant comparator - A pipeline type analog-digital converter includes a first to an N-th (N is an integer of not less than 2) stages (08-21-2008
20080258957High Bandwidth Oscilloscope - A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.10-23-2008
20130147646COMPRESSIVE SENSE BASED RECONSTRUCTION IN THE PRESENCE OF FREQUENCY OFFSET - A calibration method to compensate for a sparsifying basis mismatch is provided. An analog signal is converted to a first digital signal at a sampling frequency that is less than a Nyquist frequency for the analog signal to generate a first digital signal. Each of a plurality of spectral terms is iteratively isolated from the first digital signal, and the offset for each of the plurality of spectral terms is iteratively determined. A dictionary is then constructed using the offset for each of the plurality of spectral terms, where the dictionary compensates for mismatch from a sparsifying basis.06-13-2013
20130147648ASYNCHRONOUS DIGITISATION OF TRANSIENT SIGNALS FROM RADIATION DETECTORS - A device for sampling or digitising a detection signal from an X- or gamma-ray detector wherein, during a sampling time, estimations of a feedback signal are made at times when the signal injected to the inverting input of a comparator is equal to the detection signal at the non-inverting input of said comparator.06-13-2013
20130147647SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.06-13-2013
20100295716INTERFERENCE REDUCTION DEVICE - An interference reduction device includes an analog to digital converter, a serial to parallel converter, a first FIR filter, a second FIR filters, a flip-flop, a decision unit, and a selector. The analog to digital converter performs A/D conversion. The serial to parallel converter performs a session of distribution processing in which a digital signal obtained by the A/D conversion. The first FIR outputs the signal after a filer operation at the desired output frequency. The second FIR filters each perform a filter operation, also each output the generated signals at the desired output frequency. The flip-flop samples the inputted digital signal. The decision unit decides which one of the FIR filters has the smallest influence of interference of the input digital signal. The selector outputs one of the signals outputted by the FIR filters.11-25-2010
20100309037SAMPLING COMPARATORS - An improved regenerative clocked sampling circuit is described which uses a single clocking signal to switch the circuit between a tracking phase in which the state tracks the input signal, and a bistable phase during which the state rapidly approaches one of two states dependant on the input signal. The same clock signal also isolates the bistable circuit from the input signal source. In a preferred embodiment, these two actions are performed by the same transmission gate or gates connecting the input to the potentially bistable circuit.12-09-2010
20110234439TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERSION CIRCUIT HAVING POLYPHASE CORRECTION FILTER - Time-interleaved analog-to-digital (AD) conversion circuit, which includes first and second AD converters that generate first and second digital signal sequences by converting an analog input signal into first and second digital signals with a first frequency at first and second timings mutually different with each other is disclosed. The AD conversion circuit further includes a FIFO that receives the first and second digital signal sequences, and a correction filter including first and second portions that are supplied with a common clock signal. The correction filter generates a first corrected digital signal sequence by adding the first synchronized digital signal sequence and the second synchronized digital signal sequence passed through the first portion of the correction filter, and a second corrected digital signal sequence by passing the second synchronized digital signal sequence through the second portion of the correction filter.09-29-2011
20130120178SEMICONDUCTOR DEVICE AND SENSOR SYSTEM - A semiconductor device includes an analog front-end unit that performs analog front-end processing of a measurement signal input from a sensor, where circuit configuration and circuit characteristics for performing the analog front-end processing are changeable, and an MCU unit that converts the measurement signal after the analog front-end processing from analog to digital and sets circuit configuration and circuit characteristics to the analog front-end unit.05-16-2013
20130120179SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.05-16-2013
20110309962Analog-to-Digital Converter Timing Circuits - An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are also disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.12-22-2011
20130194118CORRELATED DOUBLE-SAMPLE DIFFERENCING WITHIN AN ADC - A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.08-01-2013
20090322577LOW-POWER COLUMN PARALLEL CYCLIC ANALOG-TO-DIGITAL CONVERTER - A low-power column parallel cyclic analog-to-digital converter and an imaging device using the same. The analog-to-digital converter comprises one stage and is optimized to reduce power, noise and capacitor settling time. The one stage analog-to-digital converter comprises a multiplying circuit for performing a multiplication operation during conversion phases and a sub-analog-to-digital converter connected to receive analog output signals from the multiplying circuit. The sub-analog-to-digital converter converts, during the conversion phases, the analog output signals into portions of an N-bit digital code. The multiplying circuit switches configurations between conversion phases and uses the portions of the digital code during the conversion phases to generate new analog output signals for subseQuent conversion by the sub-analog-to-digital converter.12-31-2009
20090179788Analog-to-Digital Converter with a Balanced Output - An Analog-to-Digital Converter (ADC) includes analog to digital conversion circuitry configured to receive an analog signal and output a digital representation of the analog signal on a plurality of data lines; a balancing circuit configured to encode the digital representation of the analog signal on the data lines such that a total number of 1's and 0's transmitted on any given data line is the same.07-16-2009
20130194119ANALOG-TO-DIGITAL CONVERSION DEVICE AND METHOD THEREOF - An analog-to-digital conversion device and a method thereof are provided. The analog-to-digital conversion device includes a first level adjustment unit, an analog-to-digital converter (ADC), and a linear range detection unit. The ADC converts a test signal or a first input signal to generate a test data stream or a first output data stream. In an adjustment mode, the linear range detection unit obtains a conversion curve of the ADC by using the test data stream and determines whether to adjust offset control information according to a linear range of the conversion curve. In an operation mode, the linear range detection unit continues outputting the offset control information. Additionally, before transmitting the first input signal, the first level adjustment unit adjusts a direct-current level of the first input signal according to the offset control information to allow the first input signal to be within the linear range of the conversion curve.08-01-2013
20130201047ZERO-CROSSING-BASED ANALOG-TO-DIGITAL CONVERTER HAVING CURRENT MISMATCH CORRECTION CAPABILITY - A zero-crossing-based analog-to-digital converter having current mismatch correction capability, that can raise resolution, energy efficiency, and sampling rate of a fully differential zero-crossing circuit, is realized through a 90 nm CMOS technology. The circuit is used mainly to correct offset error, to use a current supply separation technology and a digital correction mechanism to correct mismatch among a plurality of current supplies.08-08-2013
20130207824TIME DOMAIN SWITCHED ANALOG-TO-DIGITAL CONVERTER APPARATUS AND METHODS - A time domain switching analog-to-digital converter apparatus and methods of utilizing the same. In one implementation, the converter apparatus comprises a carrier signal source, and at least one reference source. The carrier signal is summed with the input signal and the summed modulated signal is fed to a comparator circuit. The comparator is configured detects crossings of the reference level by the modulated waveform thereby generating trigger events. The time period between consecutive trigger events is used to obtain modulated signal deviation due to the input signal thus enabling input signal measurement. Control of the carrier oscillation amplitude and frequency enables real time adjustment of the converter dynamic range and resolution. The use of additional reference signal levels increases sensor frequency response and accuracy. A dual channel converter apparatus enables estimation and removal of common mode noise, thereby improving signal conversion accuracy.08-15-2013

Patent applications in class Analog to digital conversion

Patent applications in all subclasses Analog to digital conversion