Class / Patent application number | Description | Number of patent applications / Date published |
341123000 | Having variable sampling rate | 7 |
20080231484 | Variable sized aperture window of an analog-to-digital converter - An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems. | 09-25-2008 |
20080284625 | REDUCING POWER CONSUMPTION IN THE EARLY STAGES OF A PIPELINE SUB-ADC USED IN A TIME-INTERLEAVED ADC - A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC. | 11-20-2008 |
20090174585 | System and method for converting analog values into digital form - A method for converting analog values into digital form comprises comparing a current analog sample value with an analog input value to produce an outcome, generating a count value based on the outcome, the count value increasing upon successive like outcomes and being reset to an initial count value upon successive unlike outcomes, adding or subtracting the count value to/from a current digital sample value to generate a next digital sample value, the adding or subtracting being based on the outcome, and converting the next digital sample value to the current analog sample value. | 07-09-2009 |
20120176261 | SEMICONDUCTOR INTEGRATED DEVICE AND OPERATION METHOD THEREOF - In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit. | 07-12-2012 |
20140152478 | RANDOMIZED TIME-INTERLEAVED SAMPLE-AND-HOLD SYSTEM - A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs. | 06-05-2014 |
20150381195 | EFFICIENT TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N. | 12-31-2015 |
20160094240 | SAMPLE RATE CONVERTER, AN ANALOG TO DIGITAL CONVERTER INCLUDING A SAMPLE RATE CONVERTER AND A METHOD OF CONVERTING A DATA STREAM FROM ONE DATA RATE TO ANOTHER DATA RATE - It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate F | 03-31-2016 |