Entries |
Document | Title | Date |
20080198049 | A/D CONVERTER - An A/D converter compares one or more analog voltages to be converted with a reference voltage given by a voltage change value of ramp voltage whose voltage value changes monotonically for a certain period or a voltage proportional to the voltage change value, converts each analog voltage to a digital value corresponding to the reference voltage, and outputs it, the A/D converter comprising an arithmetic unit for comparison between the analog voltage and reference voltage with respect to each analog voltage, the arithmetic unit having a first power supply line for receiving a power supply voltage, wherein the first power supply line is provided as another power supply line not affected by voltage fluctuation of a second power supply line for supplying a system power supply voltage by providing a MOS transistor whose gate terminal is connected to a stabilized voltage source between the first and second power supply lines. | 08-21-2008 |
20080278358 | REFERENCE CIRCUITS FOR SAMPLED-DATA CIRCUITS - A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level. | 11-13-2008 |
20090009372 | PHOTOELECTRIC CONVERSION APPARATUS - Providing a configuration that, when an AD converter is provided for each of pixel columns, enables each of the elements to be arranged without increasing the element arrangement pitch. A photoelectric conversion apparatus according to the present invention includes a plurality of AD converters. The AD converter includes: an arithmetic operation amplifying circuit unit, a comparator circuit unit for comparing, with a reference signal, an output from the arithmetic operation amplifying circuit unit; a DA converted circuit unit for DA converting a signal based on a signal from the comparator circuit unit; and a sampling and holding unit arranged at an input section of the arithmetic operation amplifying circuit unit. The DA converted circuit unit is arranged between the comparator circuit unit and the arithmetic operation amplifying circuit unit. | 01-08-2009 |
20090015450 | D/A CONVERSION CIRCUIT AND A/D CONVERSION CIRCUIT - A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes. | 01-15-2009 |
20090015451 | FLASH A/D CONVERTER - A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a differential pair formed of a plurality of sets of cascode-connected transistors, and has a first switch for short-circuiting respective cascode connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair. The first switch and the second switch are controlled to open and close by a control clock of a predetermined period. | 01-15-2009 |
20090021407 | Analog to digital converter with a series of delay units - An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data. | 01-22-2009 |
20090033530 | METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME - Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC. | 02-05-2009 |
20090040084 | DIRECTLY SAMPLING RADIO FREQUENCY SIGNALS - The present disclosure is directed to a system and method for directly sampling RF signals. In some implementations, an RF reader includes a clock generator and an Analog-to-Digital Converter (ADC). The clock generator is configured to generate a sample clock signal based, at least in part, on an input signal associated with transmitting RF signals. The ADC is configured to directly sample RF signals in a receive path of the reader using the sample clock signal to generate a digital signal. Mixing of the RF signal and the sample clock, through the sampling process in the ADC, reduces phase noise associated with the transmission signal in the receive path. | 02-12-2009 |
20090058700 | Analog to digital converter with dynamic power configuration - In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption. | 03-05-2009 |
20090079603 | CONSTANT CURRENT SOURCE, RAMP VOLTAGE GENERATION CIRCUIT, AND A/D CONVERTER - A ramp voltage generation circuit suitable for an A/D converter preventing a variation in a digital value obtained by an A/D conversion operation. The circuit comprises a stabilization voltage source Vref, an operation amplifier AMP | 03-26-2009 |
20090096646 | METHOD OF ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION AND ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER - Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit. | 04-16-2009 |
20090096647 | Analog-to-digital converter - A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers. | 04-16-2009 |
20090109073 | PIPELINED ANALOG TO DIGITAL CONVERTER WITHOUT INPUT SAMPLE/HOLD - The first stage of a plurality of stages in a pipelined analog to digital converter couples its input analog signal to both a first and second sample and hold (S/H). The first S/H output is coupled to the input of a multiplying digital to analog converter (MDAC) of the first stage, and the second S/H output is coupled to a flash ADC of the first stage. The delay of the second S/H is longer than the delay of the first S/H, and the clock edge of the second S/H is delayed an adjustable amount with respect to the clock edge of the first S/H, so as to minimize the difference in held voltages at the outputs of the two S/Hs in the presence of an input signal having high slew rate. The residue voltage of the first stage is amplified in the MDAC by 2̂(n−2) where n is the number of bits in the stage. The second stage flash ADC has a range of normal threshold voltage levels substantially half that of the first stage, and a plurality of added threshold voltage levels and corresponding comparators above and below the normal highest and lowest threshold voltages, thereby increasing dynamic range and providing over range and under range indications facilitating adjustment of the delay of the clock edge of the first stage second S/H. | 04-30-2009 |
20090231174 | PIPELINED ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter including a first stage and a second stage. The first stage receives a first reference voltage and a first analog input voltage, generates a first digital signal by quantizing the first analog input voltage, and generates a first analog output voltage based on the first digital signal and the first analog input voltage. The second stage receives a second reference voltage and the first analog output voltage, in which the second reference voltage is lower than the first reference voltage. The second stage further generates a second digital signal by quantizing the first analog output voltage, and generates a second analog output voltage based on the second digital signal and the first analog output voltage. | 09-17-2009 |
20090237281 | A/D CONVERTER - An A/D converter includes: a plurality of A/D conversion circuits ( | 09-24-2009 |
20090243902 | SWITCHED-CAPACITOR CIRCUIT - In a switched-capacitor circuit such as a DAC, charges are accumulated by a plurality of sampling capacitors in dependence upon input digital data during a sampling phase; then, during a sharing phase these charges are shared with a holding capacitor which is connected across an opamp. In the so-called bipolar charging type switched-capacitor DAC, the signal provided by the sampling capacitors is doubled by connecting their opposite sides to positive and negative reference voltages during the sampling phase. However, parasitic capacitances associated with the sampling capacitors then cause a disturbance to the input of the operational amplifier during the sharing phase. By equalising the input sides of the sampling capacitors to a reference voltage, prior to the sharing phase, this disturbance is avoided thereby allowing a low-power opamp to be employed in the DAC. This equalising can be achieved by adding a short equalising clock phase between the usual sampling and sharing clock phases of the DAC. | 10-01-2009 |
20090251344 | Successive Approximation Analog To Digital Converter - A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles. | 10-08-2009 |
20090289822 | AD CONVERTER AND DATA PROCESSING UNIT - An AD converter includes an input circuit, an operation circuit and a bus interface. The input circuit is provided with a pull-down circuit, which is capable of pulling down an analog signal input side of a sample-hold circuit whether an analog signal is inputted or not. The operation circuit is provided with a reference voltage conversion result storing register, which is capable of storing a conversion result of an analog reference voltage inputted periodically separately from a conversion result of the analog signal inputted through the sample-hold circuit. The operation circuit is further provided with a check register, which is capable of writing in and reading out data for checking operation of a signal transfer system including a bus interface through the bus interface. Thus, it is made possible to confirm normality of an external part and an internal part of the AD converter. | 11-26-2009 |
20090295609 | SYSTEM AND METHOD FOR REDUCING POWER DISSIPATION IN AN ANALOG TO DIGITAL CONVERTER - A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs. | 12-03-2009 |
20090295610 | A/D converter having arbitration circuit which arbitrates operations of sample-and-hold circuit and comparator - When an A/D conversion start request for a potential supplied to an analog input terminal is generated during a conversion operation for converting a potential supplied to an analog input terminal into a digital value being executed, an A/D converter makes a sample-and-hold (SH) circuit execute a sampling operation for sampling the potential supplied to the analog input terminal and a holding operation for holding it as an analog value. At this time, the conversion operation is suspended. Consequently, the A/D converter can avoid the influence of power supply noise arising from the sampling operation in the SH circuit. | 12-03-2009 |
20090315747 | Method and Apparatus for Delay and Combining Circuitry - A system for signal processing is provided. A sampling delay system generates a plurality of sampling delay values. A plurality of programmable delays each receives one of the sample delay values. A plurality of sample and hold units, each coupled to one of the programmable delays, generates a sample of a received signal in response to an input from the programmable delay. | 12-24-2009 |
20100001889 | Current-Time Digital-to-Analog Converter - A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2 | 01-07-2010 |
20100013686 | Sample and hold circuit and digital-to-analog converter circuit - Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal. The sampling voltage supply circuit delivers a sampling voltage to the one end of at least one of the first and second capacitance elements. | 01-21-2010 |
20100026536 | SAMPLE-HOLD CIRCUIT HAVING SPREADING SWITCH AND ANALOG-DIGITAL CONVERTER USING SAME - A sample-hold circuit includes a voltage-current converter, having a first input terminal pair to which an input differential signal is input and a first output terminal pair which outputs current according to the voltage of the input differential signal, a spreading switch having a switch group which switches the first output terminal pair to inverting or non-inverting states, and an integrator having a second input terminal pair coupled to the first output terminal pair via the spreading switch, an output amplifier which outputs to a second output terminal pair an output differential signal amplified according to the differential signal at the second input terminal pair, a capacitor pair which is provided respectively between the second input terminal pair and second output terminal pair, and which is charged or discharged by current input to the second input terminal pair, and a reset circuit which resets charge states of the capacitor pair. | 02-04-2010 |
20100052957 | Charge Domain Successive Approximation Analog-to-Digital Converter - An analog to digital conversion circuit and method is presented. The analog to digital circuit ( | 03-04-2010 |
20100073209 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal. | 03-25-2010 |
20100103009 | A/D CONVERTER AND RANDOM-NOISE REDUCING METHOD FOR A/D CONVERTERS - An A/D converter includes a sample/hold unit that samples an input analog signal at a predetermined timing to hold m (m≧2) equal analog values and successively outputs the m held equal analog values in time series; an A/D converting unit that converts the m equal analog values successively input in time series from the sample/hold unit to m digital signals in time series; a data-alignment adjusting circuit that adjusts timings of the m digital signals successively input in time series from the A/D converting unit to parallelize the m digital signals; and an averaging circuit that outputs an average value of the m digital signals input in parallel from the data-alignment adjusting circuit as a final A/D conversion result. | 04-29-2010 |
20100117879 | A/D CONVERTER AND A/D CONVERSION METHOD - An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters ( | 05-13-2010 |
20100141493 | DIGITAL-TO-ANALOG CONVERSION CIRCUIT AND COLUMN DRIVER INCLUDING THE SAME - A digital-to-analog conversion circuit includes a digital-to-analog converter and a buffer amplifier. The digital-to-analog converter receives upper bits of digital data and a plurality of analog voltages and is configured to output two adjacent analog voltages of the plurality of analog voltages based on the upper bits. The buffer amplifier includes two input terminals. One of the input terminals receives one of the two adjacent analog voltages and the other input terminal receives the other adjacent analog voltage. The buffer amplifier is configured to generate a current offset by controlling a current flowing into each of the two input terminals based on lower bits of the digital bits. | 06-10-2010 |
20100149010 | PIPELINED AD CONVERTER - A pipelined AD converter ( | 06-17-2010 |
20100156683 | AMPLIFIER CIRCUIT AND A/D CONVERTER - An amplifier circuit includes a current source that is connected between a power supply voltage and an output node and that is turned on when a switching control signal takes a first value and is turned off when the switching control signal takes a second value; a grounded voltage control current source whose amount of current is controlled by an input voltage; a cascode transistor connected between the voltage control current source and the output node; a boost amplifier connected between a gate electrode and a source electrode of the cascode transistor; and a switch that is connected between an output node of the boost amplifier and a bias voltage and that is turned on for a predetermined period of time when a value of the switching control signal is switched from the second value to the first value, to forcefully rise the boost amplifier. | 06-24-2010 |
20100176977 | Area-Efficient Analog-to-Digital Converter - The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations. | 07-15-2010 |
20100182176 | CONVERTER CIRCUIT, ANALOG/DIGITAL CONVERTER, AND METHOD FOR GENERATING DIGITAL SIGNALS CORRESPONDING TO ANALOG SIGNALS - A charge corresponding to an analog signal V | 07-22-2010 |
20100182177 | METHOD AND SYSTEM FOR ANALOG-TO-DIGITAL CONVERSION - Method and system for analog-to-digital conversion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a different operational amplifier, which includes a first output, a second output, a first input, and a second input. The operational amplifier is associated with an amplification factor. The integrated circuit also includes a first voltage input. The first voltage input can be characterized by a first voltage. Additionally, the integrated circuit includes a second voltage input. The second voltage input can be characterized by a second voltage. Furthermore, the integrated circuit includes a first voltage source configured to provide a first reference voltage. In addition, the integrated circuit includes a second voltage source configured to provide a second reference voltage. Furthermore, the integrated circuit includes a first capacitor being electrically coupled to the first input and disengageably coupled to the first voltage input. | 07-22-2010 |
20100182178 | Two-Step Subranging ADC Architecture - First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output. | 07-22-2010 |
20100207792 | SIGNAL SAMPLING CIRCUIT - A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. The holding time period comprises a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal. | 08-19-2010 |
20100225514 | ANALOG/DIGITAL CONVERSION DEVICE - An disclosed analog/digital conversion apparatus for converting an analog signal into digital data by cycling the analog signal through a fully differential amplifier circuit includes a polarity switching unit configured to switch connection polarities of the fully differential amplifier circuit; and a control unit configured to control the polarity switching unit in such a manner that the connection polarities of the fully differential amplifier circuit are switched between a first signal cycle and second and subsequent signal cycles. | 09-09-2010 |
20100225515 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal. | 09-09-2010 |
20100231428 | TRACK-AND-HOLD CIRCUIT AND A/D CONVERTER - A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit. | 09-16-2010 |
20100245141 | Disconnection detecting circuit and disconnection detecting method by using capacitor - A disconnection detecting method includes charging a capacitor by connecting a node of the capacitor to a first power source line supplied with a first power source potential, connecting the node of the capacitor to an input terminal, after the node of the capacitor is disconnected from the first power source line, and converting a first value on the node to a first digital data. The method further includes discharging the capacitor by connecting the node of the capacitor to a first power source line supplied with a second power source potential, after the node is disconnected from the input terminal, connecting the node of the capacitor to the input terminal, after the node of the capacitor is disconnected from the second power source line, and converting a second value on the node to a second digital data. The method further includes comparing the first digital data with the second digital data to determine whether a difference between the first and second digital data exists, and determining that the input terminal is abnormal when the difference exists. | 09-30-2010 |
20100259430 | POWER-SUPPLY-NOISE CANCELLING CIRCUIT AND SOLID-STATE IMAGING DEVICE - A reference voltage generation circuit generates a reference voltage and outputs it to an amplifier reference voltage line. A power-supply-noise adding circuit adds power supply noise superimposed on a power supply to the reference voltage generated by the reference voltage generation circuit. A differential amplifier amplifies a difference between a voltage of a vertical signal line and a voltage of an amplifier reference voltage line and outputs the amplified voltage. | 10-14-2010 |
20100283643 | SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER - The invention is a novel scheme of performing an analog to digital conversion of simultaneous sampled analog inputs using multiple sample and hold circuits and a single successive approximation analog to digital converter (“SAR ADC”). Each of the analog inputs are stored on capacitors in the sample and hold circuits, and the sample and holds are sequentially connected to the capacitor DAC. After the digital conversion of the of the input signals stored on a sample and hold, the connected sample and hold is disconnected and the charge on the DAC is reset before the next sample and hold circuit is connected. The process is repeated until all analog inputs have been converted. | 11-11-2010 |
20100283644 | A/D conversion circute and test method - An A/D conversion circuit includes a plurality of transmission paths that transmit signal voltages and reference voltages, and an A/D conversion unit that A/D converts voltages output from the transmission paths. Each of the plurality of transmission paths includes a first switch that selectively outputs one of the signal voltage and the reference voltage, an S/H circuit that holds output voltage from the first switch, and a second switch that selectively outputs one of the output voltage from the first switch and output voltage from the S/H circuit. | 11-11-2010 |
20100283645 | A/D CONVERSION CIRCUIT, ELECTRONIC APPARATUS, AND A/D CONVERSION METHOD - An A/D conversion circuit includes: a sample-and-hold circuit adapted to sample and hold an input signal to output a sampled signal; a control circuit adapted to output successive approximation data; a first D/A conversion circuit adapted to perform D/A conversion on the successive approximation data to output a first D/A output signal; a second D/A conversion circuit adapted to perform D/A conversion on time-varying code data to output a second D/A output signal; and a comparison circuit adapted to perform a process of comparing the first D/A output signal, and an addition signal of the sampled signal and the second D/A output signal, and to output a comparison result signal, wherein the control circuit has a successive approximation register to which register values are set in accordance with the comparison result signal, outputs successive approximation result data after all of the register values of the successive approximation register have been determined, and subtracts the code data from the successive approximation result data to output the result as A/D conversion data of the input signal. | 11-11-2010 |
20100289681 | A/D CONVERSION DEVICE - An exemplary embodiment of the present invention is an A/D conversion device including: a sample-and-hold circuit that holds an analog input voltage; a sequential conversion register that stores a digital value corresponding to a threshold; a D/A converter that generates an analog voltage corresponding to the digital value stored in the sequential conversion register; a comparator that compares an analog voltage output from the sample-and-hold circuit with an analog voltage obtained from the D/A converter, and outputs a comparison result; a comparison result counter that outputs a determination result according to a count number counted based on the comparison result; and a control circuit that performs control for switching from the comparator function to the A/D conversion function, based on the determination result. During operation of the A/D conversion function, the sequential conversion register sequentially converts the analog voltage held in the sample-and-hold circuit into a digital value. | 11-18-2010 |
20100328122 | ANALOG TO DIGITAL CONVERTERS - In one embodiment, an analog to digital converter (ADC) for converting an analog signal to a digital signal includes an input channel for receiving the analog signal, and includes a first and second sampling-integrating units. The first sampling-integrating unit receives the analog signal, samples the analog signal, integrates a superposition of a first feedback signal and a sampled signal of the analog signal, and generates a first output signal. The second sampling-integrating unit receives the first output signal, samples the first output signal, integrates a superposition of a second feedback signal and a sampled signal of the first output signal, and generates a second output signal. The ADC includes a feedback circuit for generating the digital signal according to the second output signal and for providing the first and second feedback signals indicative of the digital signal to the first and second sampling-integrating units respectively. | 12-30-2010 |
20110012764 | MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE - An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch. | 01-20-2011 |
20110018751 | FOLDING ANALOG-TO-DIGITAL CONVERTER - A folding analog-to-digital converter including: a reference voltage generator, a track-and-hold circuit and a first pre-amplification circuit. The reference voltage generator generates a plurality of reference voltages. The track-and-hold circuit generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than a level of a power supply voltage, and samples and holds an input voltage signal in response to the generated sampling control signal to generate a sampled signal. The first pre-amplification circuit amplifies each of voltage differences between the sampled signal and each of the plurality of reference voltages. | 01-27-2011 |
20110032129 | INTEGRATED CIRCUITS, LIQUID CRYSTAL DISPLAY (LCD) DRIVERS, AND SYSTEMS - An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel. | 02-10-2011 |
20110032130 | AM chirp LADAR readout circuit and module - A readout circuit is disclosed for use in an AM chirp LADAR system. The circuit comprises a photodetector such as a metal-semiconductor-metal detector coupled to a passive electronic filter. The filter output coupled to a capacitive-coupled transimpedance amplifier with an output coupled to an analog storage register. The analog storage register output is coupled to a sample-and-hold circuit which in turn is coupled to a sample and hold circuit. The output of the sample and hold circuit is digitized by an analog-to-digital converter circuit for further processing. The circuit may be used as a cell for the readout of an individual pixel on a photodetector or a plurality of cells used in a stack of integrated circuit chips for the read out of a plurality of pixels in a photodetector array. | 02-10-2011 |
20110032131 | Analog To Digital Converter with Dynamic Power Configuration - In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption. | 02-10-2011 |
20110050469 | LINE OF PROPAGATION DIGITIZING DEVICE - An electric signal digitizing device includes a line of propagation through which the signal travels and a plurality of samplers ( | 03-03-2011 |
20110063150 | METHOD FOR DETECTING AND CORRECTING PHASE SHIFT BETWEEN I DATA CLOCK AND Q DATA CLOCK IN QUADRATURE MODULATOR OR QUADRATURE DEMODULATOR - A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock. | 03-17-2011 |
20110063151 | Systems, Circuits, and Methods for Pipelined Folding and Interpolating ADC Architecture - A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply. | 03-17-2011 |
20110074612 | A/D converter and open detection method thereof - An A/D converter includes a sampling capacitor that accumulates a charge according to an input voltage, a first initialization switch that initializes the sampling capacitor, a sample hold switch that switches a connection state of an external input terminal and the sampling capacitor, and a second initialization switch that initializes a charge accumulated in an input node via a resistor, the input node connecting the external input terminal and the sample hold switch. | 03-31-2011 |
20110084862 | Semiconductor Integrated Circuit Device - A high-precision A/D conversion is realized while the number of external terminals used for an A/D converter is reduced. At the time of sampling, first to fifth switches are turned on and a sixth switch is turned off. Since a first resistor is set to a resistance value optimum for sampling, an impedance in the direction from a node A to the left side and an impedance in the direction from a node B to the left side almost match, and a large noise-cancelling effect is obtained. At the time of successive approximation, the first, second, third, and fifth switches are turned off and the fourth and sixth switches are turned on. Since a second resistor is set to a resistance value optimum for the successive approximation, the impedance in the direction from the node A to the left side and the impedance in the direction from the node B to the left side almost match, and a large noise-cancelling effect is obtained also at the time of successive approximation. | 04-14-2011 |
20110090105 | Fast Readout Method and Switched Capacitor Array Circuitry for Waveform Digitizing - A method relates to a technique for reducing the readout time of switched capacitor array circuitries. An implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register. The write signal for the sampling cells is generated by a chain of inverters. The domino wave runs continuously until stopped. A read shift register clocks the contents of the sampling cells to outputs, where it can be digitized. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV makes this chip suited for low power, high speed, high precision waveform digitizing. | 04-21-2011 |
20110102218 | Dedicated Sample and Hold Modules - A method and system for sampling values. Multiple values are sampled concurrently. One of the values is stored while another one of the values is converted to a corresponding digital value by an analog-to-digital converter (ADC). Subsequently, the stored value is made available to the ADC. | 05-05-2011 |
20110102219 | SUCCESSIVE APPROXIMATION ANALOG/DIGITAL CONVERTER AND TIME-INTERLEAVED SUCCESSIVE APPROXIMATION ANALOG/DIGITAL CONVERTER - A successive approximation analog/digital converter includes a sample & hold part sampling and holding an intensity of an analog input signal using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of an MSB of a digital value to be converted according to the comparison result of the second comparator and values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the comparison voltages using the estimated digital values and the reference voltage. | 05-05-2011 |
20110102220 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced. | 05-05-2011 |
20110122007 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THEREOF - An analog-to-digital converter circuit includes: a plurality of sample-and-hold circuits configured to sample an analog signal; an analog-to-digital converter configured to convert the analog signal held by each of the plurality of sample-and-hold circuits into a digital signal; and a control circuit configured to output a control signal, wherein a pair of sample-and-hold circuits among the plurality of sample-and-hold circuits sample an analog signal in a first period and hold an analog signal sampled by another pair of sample-and-hold circuits in a second period prior to the first period based on the control signal. | 05-26-2011 |
20110128172 | LOW POWER CONVERT AND SHUTDOWN SAR ADC ARCHITECTURE - With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption. | 06-02-2011 |
20110140938 | SIGNAL GENERATING APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus comprising a DA converter that outputs an output signal corresponding to input data supplied thereto; a sample/hold unit that is provided between the DA converter and an output end of the signal generating apparatus, and that samples an output voltage of the DA converter and holds the sampled output voltage; a comparing section that compares (i) a level of a signal output from an analog circuit that propagates the output signal to output a signal corresponding to the input data to (ii) a level of the signal output by the DA converter; and a control section that, during a holding period, (iii) provides the DA converter with comparison data instead of the input data to cause the DA converter to output a comparison voltage corresponding to the comparison data, (iv) causes the comparing section to compare a voltage of the signal output by the analog circuit to the comparison voltage, and (v) adjusts the output voltage of the DA converter based on a comparison result of the comparing section. | 06-16-2011 |
20110140939 | SAMPLE HOLD CIRCUIT AND METHOD FOR SAMPLING AND HOLDING SIGNAL - A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit. | 06-16-2011 |
20110163899 | SAMPLE AND HOLD CIRCUIT AND METHOD FOR CONTROLLING SAME - A sample and hold circuit that is provided with an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a hold circuit bias current switching circuit for switching a bias current of the hold circuit to a first separate circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit. | 07-07-2011 |
20110187569 | ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION - A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value. | 08-04-2011 |
20110199245 | MULTI-CHANNEL ANALOG DIGITAL CONVERSION CIRCUIT AND ANALOG DIGITAL CONVERSION METHOD THEREOF - A multi-channel analog digital conversion circuit includes a plurality of sampling circuits for sampling and buffering a plurality of analog input signals, a single output circuit coupled to the sampling circuits and shared by the sampling circuits and a single analog digital conversion core coupled to the output circuit and shared by the sampling circuits. | 08-18-2011 |
20110241916 | RE-CONFIGURABLE MULTIPURPOSE ANALOG INTERFACE - Systems and apparatus are provided for interfacing a digital controller with an analog input means. The system comprises a digital controller with the input of the digital controller coupled to the output of the analog-to-digital converter. The system further comprises a digital-to-analog converter coupled to an analog interface circuit. The analog interface circuit comprises a reconfigurable RC network switchably coupled to a first amplifier or to a second amplifier. The analog interface circuit further comprises a third amplifier having an input being coupled to an output of the second amplifier and the output of the third amplifier being coupled to the one or more input signal paths to the first amplifier. | 10-06-2011 |
20110241917 | Method And Apparatus For Signal Reconstruction From Saturated Measurements - A method for recovering a signal by measuring the signal to produce a plurality of compressive sensing measurements, discarding saturated measurements from the plurality of compressive sensing measurements and reconstructing the signal from remaining measurements from the plurality of compressive sensing measurements. Alternatively, a method for recovering a signal comprising the steps of measuring a signal to produce a plurality of compressive sensing measurements, identifying saturated measurements in the plurality of compressive sensing measurements and reconstructing the signal from the plurality of compressive sensing measurements, wherein the recovered signal is constrained such that magnitudes of values corresponding to the identified saturated measurements are greater than a predetermined value. | 10-06-2011 |
20110241918 | PIPELINE TYPE A/D CONVERTER - There is provided a pipeline type A/D converter capable of expanding an input range and increasing the number of bits of digital output signals, without increasing thermal noises or an open loop gain needed for an operational amplifier. The number of sample-hold capacitors is divided from M into N and further multiplies the reference voltage by N to increase the number of capacitors available to add to and subtract from the reference voltage. Consequently, it enables expanding the input range and increasing the number of bits of the digital output signals. On this occasion, the thermal noises are not deteriorated before and after the division of the capacitors, as the analog signal is sampled by all the capacitors. Further, the open loop gain needed for the operational amplifier will not be increased, since the ratio of the capacitors each used as a feedback element for amplifying the analog signal to the remaining capacitors is unchanged before and after the division of the capacitors. | 10-06-2011 |
20110254716 | A/D CONVERTER DEVICE AND SIGNAL PROCESSING UNIT - An A/D converter device is provided, which has a D/A conversion function and changes a resolution of A/D conversion and D/A conversion. The A/D converter device is configured to selectively execute an A/D conversion operation and a D/A conversion operation, by the operation of a control circuit controlling switching of switches according to an ADC/DAC function switching signal supplied from an external side. The A/D conversion operation performs A/D conversion of an input signal voltage inputted via a signal input terminal from an external side and outputs an A/D conversion value of 12 bits. The D/A conversion operation outputs, via a signal output terminal, an analog voltage produced by performing D/A conversion of a digital value supplied from the external side. | 10-20-2011 |
20110254717 | AD CONVERTER - Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose. | 10-20-2011 |
20110267212 | CAPACITIVE INTERFACE CIRCUIT FOR LOW POWER SENSOR SYSTEM - This disclosure describes a capacitive interface circuit for a low power system. The capacitive interface circuit is configured to achieve very low noise sensing of capacitance-based transducers, such as a micro-electro-mechanical system (MEMS)-based sensor, with high resolution and low power. The capacitive interface circuit uses a differential amplifier and correlated triple sampling (CTS) to substantially eliminate, or at least reduce, kT/C noise, as well as amplifier offset and flicker (1/f) noise, from the output of the amplifier. The capacitive interface circuit may further include an output stage that reduces glitching, i.e., clock transients, in the output signal by allowing transients in the amplifier output to settle. In this manner, the circuit can be used in a low power system to produce a stable, low-noise output. | 11-03-2011 |
20110279297 | Analog-to-Digital Conversion - One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples that are digital versions of at least one analog signal at a sampling frequency and a memory configured to store data corresponding to an average value of the digital samples in at least one register. The system further includes a processor configured to access the data corresponding to the average value for processing at an access frequency that is less than the sampling frequency. | 11-17-2011 |
20110304490 | LOW POWER COMPARATOR FOR USE IN SAR ADCS - Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved. | 12-15-2011 |
20120007758 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD OF ANALOG TO DIGITAL CONVERSION - An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | 01-12-2012 |
20120007759 | TRACK-AND-HOLD CIRCUIT AND A/D CONVERTER - A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit. | 01-12-2012 |
20120013494 | Time Varying Quantization-based Linearity Enhancement of Signal Converters and Mixed-signal Systems - A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal. | 01-19-2012 |
20120032826 | ANALOG TO DIGITAL CONVERTERS - In one embodiment, an analog to digital converter (ADC) for converting an analog signal to a digital signal includes an input channel for receiving the analog signal, and includes a first and second sampling-integrating units. The first sampling-integrating unit receives the analog signal, samples the analog signal, integrates a superposition of a first feedback signal and a sampled signal of the analog signal, and generates a first output signal. The second sampling-integrating unit receives the first output signal, samples the first output signal, integrates a superposition of a second feedback signal and a sampled signal of the first output signal, and generates a second output signal. The ADC includes a feedback circuit for generating the digital signal according to the second output signal and for providing the first and second feedback signals indicative of the digital signal to the first and second sampling-integrating units respectively. | 02-09-2012 |
20120081244 | METHOD AND APPARATUS FOR ANALOG TO DIGITAL CONVERSION - An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier. | 04-05-2012 |
20120092199 | PIPELINED ADC HAVING A THREE-LEVEL DAC ELEMENTS - In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used. | 04-19-2012 |
20120127006 | Two-Step Subranging ADC Architecture - First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output. | 05-24-2012 |
20120127007 | COMPARISON CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION DEVICE - A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch. | 05-24-2012 |
20120139767 | CHARGE INJECTION MECHANISM FOR ANALOG-TO-DIGITAL CONVERTERS - A low-cost charge injection mechanism may enable oversampling to be used on low frequency signals by injecting dither noise into the ADC input. The dither noise can reduce the quantization noise allowing even direct current (DC) signals to be oversampled correctly. A low-cost charge injection mechanism can also be used to improve the ENOB by characterizing the ADC and digitally correcting the converted signal for non-linearity errors such as INL. Reducing INL errors may also allow a higher degree of oversampling to be used to further improve the ENOB. | 06-07-2012 |
20120154188 | SENSE-AMPLIFIER MONOTIZER - A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase. | 06-21-2012 |
20120188110 | Track and Hold Circuit - A track and hold circuit includes an input, a first output configured to produce a first output signal, and a second output configured to produce a second output signal while the track and hold circuit is in a first mode. While the track and hold circuit is in a second mode, the second output signal is combined with the first output signal and output on the first output. | 07-26-2012 |
20120218132 | INTEGRATED CIRCUITS, LIQUID CRYSTAL DISPLAY (LCD) DRIVERS, AND SYSTEMS - An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel. | 08-30-2012 |
20120249352 | SWITCHED-CAPACITOR INPUT CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME - A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor. | 10-04-2012 |
20120286981 | COMPRESSIVE SENSING ANALOG-TO-DIGITAL CONVERTERS - Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions. | 11-15-2012 |
20120293350 | METHOD AND APPARATUS FOR PERFOMING DATA CONVERSION WITH NON-UNIFORM QUANTIZATION - A method for converting a sampled analog signal into digital is provided. An input signal is sampled at a sampling instant to generate a sample voltage. A first current is then applied to a node to change a voltage on the node, and a first interval to change the voltage on the node to a reference voltage from the sample voltage using the first current is determined. A second current is then applied to the node to change a voltage on the node prior to a subsequent sampling instant, and a determination of a second interval to change the voltage on the node to the reference voltage from the sample voltage using the second current is made. | 11-22-2012 |
20120293351 | Method and Apparatus for Low Power Analog-to-Digital Conversion - A method and apparatus for analog-to-digital conversion. An Analog-to-Digital Converter (ADC) includes M ADC | 11-22-2012 |
20120313800 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120319880 | SUCCESSIVE APPROXIMATION AD CONVERTER AND MOBILE WIRELESS DEVICE - A controller controls first and second supply switches so that, during a sampling period, a ground voltage is supplied to n first up-capacitors and n second up-capacitors while a power supply voltage is supplied to n first down-capacitors and n second down-capacitors. The controller also controls the first and second supply switches based on the result of comparison by a comparator during each of n bit determination periods so that a first analog voltage at a first sampling node and a second analog voltage at a second sampling node gradually approach each other. | 12-20-2012 |
20130002460 | Multichannel Analog To Digital Converter Apparatus And Method For Using - A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order. | 01-03-2013 |
20130002461 | SAMPLE AND HOLD CIRCUIT AND THE METHOD THEREOF - A sample and hold circuit and the method thereof are disclosed. The sample and hold circuit may be applied in voltage regulators or other circuits. The sample and hold circuit comprises: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a control circuit configured to receive the input signal and the output signal, and wherein based on the input signal and the output signal, the control circuit generates a digital signal, and wherein the digital signal increases when the output signal is lower than the input signal, and maintains when the output signal is larger than or equal to the input signal; a digital-to-analog converter (DAC) configured to convert the digital signal to the output signal. | 01-03-2013 |
20130009797 | Distributed Bootstrap Switch - An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate. | 01-10-2013 |
20130015991 | CIRCUITS AND METHODS FOR SAMPLING AND HOLDING DIFFERENTIAL INPUT SIGNALSAANM Cheeranthodi; RajeshAACI BangaloreAACO INAAGP Cheeranthodi; Rajesh Bangalore IN - Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase. | 01-17-2013 |
20130027236 | A/D CONVERSION DEVICE AND A/D CONVERSION CORRECTING METHOD - An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control. | 01-31-2013 |
20130038478 | Systems, Devices and Methods for Capacitor Mismatch Error Averaging in Pipeline Analog-to-Digital Converters - Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed, where in a pipeline element circuit and during a first phase, an input voltage provided by a sample-and-hold circuit is presented to first and second capacitors arranged in parallel in the pipeline element circuit. During a second phase, a second voltage corresponding to a second charge associated with the second capacitance is amplified and stored in the pipeline element circuit. During a third phase, the same input voltage of the first phase is again presented to the first and second capacitors, which are arranged in parallel in the pipeline element circuit. During a fourth phase a first voltage corresponding to the first charge is amplified and stored in the pipeline element circuit. After the first, second, third and fourth phases have been completed, digital representations of the first and second voltages are sent though corresponding registers for subsequent averaging along with digital representations of first and second voltages provided by other pipeline element circuits to produce a digital capacitor mismatch error corrected output. | 02-14-2013 |
20130038479 | Multi-Channel Sampling of Pulse Streams at the Rate of Innovation - A method includes accepting an analog input signal including a sequence of pulses of a given pulse shape. The analog input signal is distributed to multiple processing channels (40) operating in parallel. The analog input signal is sampled by performing, in each of the multiple processing channels, the operations of: mixing the analog input signal with a different, respective modulating waveform to produce a mixed signal; filtering the mixed signal; and digitizing the filtered mixed signal to produce a respective digital channel output. | 02-14-2013 |
20130038480 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-14-2013 |
20130063290 | Recording Circuit and a Method of Controlling the Same - A recording circuit is provided. The recording circuit includes a multiplexing circuit configured to receive a plurality of input signals and to produce a multiplexed output signal including the plurality of input signals, and a plurality of sampling circuits electrically coupled in parallel to each other, each sampling circuit being configured to sample a portion of the multiplexed output signal corresponding to an input signal of the plurality of input signals and the sampling circuits configured to alternately produce an output signal corresponding to the sampled portion. | 03-14-2013 |
20130099948 | SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. | 04-25-2013 |
20130127649 | SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. | 05-23-2013 |
20130135128 | Low Power High Speed A/D Converter - An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement. | 05-30-2013 |
20130135129 | Sensor Circuit for Concurrent Integration of Multiple Differential Signals and Operating Method Thereof - The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuit arranged in array and a plurality of Stage 2 integration circuit arrange in array. Each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal. Each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal. | 05-30-2013 |
20130162455 | Sample-and-Hold Circuit Arrangement - Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two “boost” capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining “error” charge, avoiding delays due to driver output slewing. | 06-27-2013 |
20130176155 | APPARATUS AND SYSTEM TO SUPPRESS ANALOG FRONT END NOISE INTRODUCED BY CHARGE-PUMP THROUGH EMPLOYMENT OF CHARGE-PUMP SKIPPING - An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output. | 07-11-2013 |
20130181854 | CIRCUIT, SENSOR CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SENSOR CIRCUIT - A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region. | 07-18-2013 |
20130201043 | SERIAL-RIPPLE ANALOG-TO-DIGITAL CONVERSION - Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage. | 08-08-2013 |
20130214947 | Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit - A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal. | 08-22-2013 |
20130214948 | SINGLE-ENDED TO DIFFERENTIAL BUFFER CIRCUIT AND METHOD FOR COUPLING AT LEAST A SINGLE-ENDED INPUT ANALOG SIGNAL TO A RECEIVING CIRCUIT WITH DIFFERENTIAL INPUTS - A single-ended to differential buffer circuit is is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively. Moreover, in the buffer circuit the second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively. A method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs is also disclosed. | 08-22-2013 |
20130222163 | TRACK AND HOLD CIRCUIT AND METHOD - A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit. | 08-29-2013 |
20130222164 | DISCRETE TIME ANALOG CIRCUIT AND RECEIVER USING SAME - The discrete time analog circuit ( | 08-29-2013 |
20130229293 | LOW POWER SLOPE-BASED ANALOG-TO-DIGITAL CONVERTER - Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements. | 09-05-2013 |
20130265182 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER BANDWIDTH MATCHING - A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level. | 10-10-2013 |
20130293403 | ADC, IC INCLUDING THE SAME, AND ADC METHOD THEREOF - An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal. | 11-07-2013 |
20140002286 | ADC WITH SAMPLE AND HOLD | 01-02-2014 |
20140062741 | SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, AND CODEC - A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals. | 03-06-2014 |
20140062742 | SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, AND CODEC - An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section. | 03-06-2014 |
20140070971 | TRACK-AND-HOLD CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER WITH SWITCHED CAPACITOR COUPLING OF AMPLIFIER STAGE - A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter. | 03-13-2014 |
20140085117 | SAMPLING CIRCUIT, A METHOD OF REDUCING DISTORTION IN A SAMPLING CIRCUIT, AND AN ANALOG TO DIGITAL CONVERTER INCLUDING SUCH A SAMPLING CIRCUIT - A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor. | 03-27-2014 |
20140085118 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD THEREOF - A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N−1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N−2)-th conversion unit includes a capacitor. The (N−1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N−1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N−2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N−1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N−1)-th conversion unit to generate the value of other bits to perform self linear compensation. | 03-27-2014 |
20140085119 | SEMICONDUCTOR DEVICE - The present invention realizes reliably control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit. | 03-27-2014 |
20140152477 | Time Interleaving Analog-to-Digital Converter - A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs. | 06-05-2014 |
20140176354 | Sampling circuit for ADC - A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC. | 06-26-2014 |
20140210654 | SUCCESSIVE APPROXIMATION AD CONVERTER AND SUCCESSIVE APPROXIMATION AD CONVERSION METHOD - A successive approximation AD converter includes a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage and each of the higher converted voltage and the lower converted voltage; a comparator that outputs a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, and changes a next higher conversion data and a next lower conversion data based on the changed approximate value. | 07-31-2014 |
20140253353 | APPARATUS AND METHOD FOR REDUCING SAMPLING CIRCUIT TIMING MISMATCH - An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels. | 09-11-2014 |
20140320323 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle. | 10-30-2014 |
20140354458 | SAR ANALOG-TO-DIGITAL CONVERSION METHOD AND SAR ANALOG-TO-DIGITAL CONVERSION CIRCUIT - An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at 1/4 or 3/4 of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step. | 12-04-2014 |
20150009053 | INPUT CONFIGURATION FOR ANALOG TO DIGITAL CONVERTER - A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase. | 01-08-2015 |
20150061906 | EFFICIENT HIGH SPEED ADC INTERFACE DESIGN - A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate. | 03-05-2015 |
20150084796 | SEMICONDUCTOR DEVICE - The present invention realizes reliably control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit. | 03-26-2015 |
20150116140 | ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER CIRCUIT - An analog-to-digital converter circuit includes a plurality of conversion stages that are cascaded to be coupled in series. Each of the plurality of conversion stages includes a signal holding circuit configured to hold an input voltage, an analog-to-digital converter configured to convert the input voltage into a digital signal based on a first reference voltage, a digital-to-analog converter configured to generate a first voltage according to the digital signal, the first reference voltage, and the input voltage, an amplifier configured to amplify the first voltage to generate an output voltage, and a reference holding circuit configured to hold a holding voltage that is in proportion to the first reference voltage. The amplifier is coupled to the reference holding circuit to receive and amplify the holding voltage to generate a second reference voltage. | 04-30-2015 |
20150123827 | SENSOR TIME - A sensor includes: a detection element; an analog front end; a digital back end, the digital back end being connected to a control unit via a digital interface, and the sensor providing sampled data in the digital back end; and a timer unit for providing pieces of time information of the sampled data in the digital back end which the control unit is able to access via the digital interface. | 05-07-2015 |
20150138005 | ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD - According to an embodiment, an analog-to-digital converter includes a first AD (analog-to-digital) conversion circuit and a second AD conversion circuit. The first AD conversion circuit performs AD conversion of a first input signal to generate an upper-bit digital signal. The second AD conversion circuit performs AD conversion of a sampled signal to generate a lower-bit digital signal. The sampled signal is obtained by sampling a residual signal corresponding to a residue of the AD conversion in the first AD conversion circuit. A period during which the second AD conversion circuit performs AD conversion of the sampled signal overlaps a period during which a second input signal subsequent to the first input signal is settled. | 05-21-2015 |
20150295588 | SUPPRESSING DIELECTRIC ABSORPTION EFFECTS IN SAMPLE-AND-HOLD SYSTEMS - Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value. | 10-15-2015 |
20150332785 | CONFIGURING SIGNAL-PROCESSING SYSTEMS - A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal. | 11-19-2015 |
20150349795 | COMMON MODE SAMPLING MECHANISM FOR RESIDUE AMPLIFIER IN SWITCHED CURRENT PIPELINE ANALOG-TO-DIGITAL CONVERTERS - A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal. | 12-03-2015 |
20160027528 | Sample-and-Hold Circuit for an Interleaved Analog-to-Digital Converter - The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage. | 01-28-2016 |
20160028412 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - The invention provides a pipelined analog-digital converter (ADC) and pertains to the technical field of integrated circuit (IC) design. The pipelined ADC at least comprises: a sampling holder, n multiplier digital-analog converters that are connected stage by stage, a clock generator, a reference generator and a digital encoder, wherein at least the sampling holder and n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection. The pipelined ADC has an excellent performance and is in particular applicable to high speed/high accuracy application. | 01-28-2016 |
20160072515 | METHOD AND CIRCUIT FOR NOISE SHAPING SAR ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit. | 03-10-2016 |
20160072518 | PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD - Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period. | 03-10-2016 |
20160094236 | SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE - An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped. | 03-31-2016 |
20160105194 | PASSIVE ANALOG SAMPLE AND HOLD IN ANALOG-TO-DIGITAL CONVERTERS - In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors. | 04-14-2016 |
20160105195 | Parallel Sample-and-Hold Circuit for a Pipelined ADC - A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples. | 04-14-2016 |
20160126966 | Successive approximation analog-to-digital converter and conversion method - The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while the number N is an integer greater than one. | 05-05-2016 |
20160164534 | LOAD CURRENT COMPENSATION FOR ANALOG INPUT BUFFERS - Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q | 06-09-2016 |
20160182078 | SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR | 06-23-2016 |
20160191072 | REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS - Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom. | 06-30-2016 |