Class / Patent application number | Description | Number of patent applications / Date published |
341121000 | Trimming control circuits | 7 |
20090322575 | SINGLE PASS INL TRIM ALGORITHM FOR NETWORKS - A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired. | 12-31-2009 |
20100201552 | SELF-CALIBRATION CIRCUIT AND METHOD FOR CAPACITORS - A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced. | 08-12-2010 |
20100253559 | METHODS AND APPARATUS FOR BUILT IN SELF TEST OF ANALOG-TO-DIGITAL CONVERTORS - An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference. | 10-07-2010 |
20110298642 | CURRENT TRIMMING CIRCUIT AND A/D CONVERTER INCLUDING CURRENT TRIMMING CIRCUIT - A current is generated from a reference voltage using an operational amplifier. The current is mirrored by a current mirror circuit to obtain a reference current. For example, the current mirror circuit includes a plurality of PMOS transistors. Based on the result of measurement of the reference current by an external monitor, the connection destination of the gate voltage of each of a plurality of mirror destination current source transistors is switched by an analog switch circuit between a power supply and the gate of a mirror source current source transistor, thereby changing the number of mirror destination current source transistors which are turned on, to change a current minor ratio. Thus, the current can be trimmed. | 12-08-2011 |
20120206283 | Minimum differential non-linearity trim DAC - A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output. | 08-16-2012 |
20150295587 | CAPACITANCE-TO-DIGITAL CONVERTER AND METHOD FOR PROVIDING A DIGITAL OUTPUT SIGNAL - A capacitance-to-digital converter ( | 10-15-2015 |
20160182076 | Background Calibration for Digital-to-Analog Converters | 06-23-2016 |