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CONVERTER CALIBRATION OR TESTING

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341 - Coded data generation or conversion

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Class / Patent application numberDescriptionNumber of patent applications / Date published
341121000 Trimming control circuits 5
20110298642CURRENT TRIMMING CIRCUIT AND A/D CONVERTER INCLUDING CURRENT TRIMMING CIRCUIT - A current is generated from a reference voltage using an operational amplifier. The current is mirrored by a current mirror circuit to obtain a reference current. For example, the current mirror circuit includes a plurality of PMOS transistors. Based on the result of measurement of the reference current by an external monitor, the connection destination of the gate voltage of each of a plurality of mirror destination current source transistors is switched by an analog switch circuit between a power supply and the gate of a mirror source current source transistor, thereby changing the number of mirror destination current source transistors which are turned on, to change a current minor ratio. Thus, the current can be trimmed.12-08-2011
20100253559METHODS AND APPARATUS FOR BUILT IN SELF TEST OF ANALOG-TO-DIGITAL CONVERTORS - An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.10-07-2010
20100201552SELF-CALIBRATION CIRCUIT AND METHOD FOR CAPACITORS - A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.08-12-2010
20090322575SINGLE PASS INL TRIM ALGORITHM FOR NETWORKS - A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired.12-31-2009
20120206283Minimum differential non-linearity trim DAC - A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.08-16-2012
Entries
DocumentTitleDate
20130027235Self-Calibrated DAC with Reduced Glitch Mapping - A digital-to-analog converter (DAC) is disclosed. According to some embodiments of the present disclosure, a DAC may include a plurality of current-steering elements, wherein each respective current-steering element is configured to operate as instructed by a respective calibration signal during respective steps in a calibration cycle, and at least one current-steering element is configured to operate as instructed by a first control signal during at least a first step in which the at least one current-steering element is not being calibrated, and operate as instructed by a second control signal during at least a second step in which the at least one current-steering element is not being calibrated.01-31-2013
20100164766DAC Variation-Tracking Calibration - A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.07-01-2010
20090027245METHOD OF GAIN ERROR CALIBRATION IN A PIPELINED ANALOG-TO-DIGITAL CONVERTER OR A CYCLIC ANALOG-TO-DIGITAL CONVERTER - The invention provides a method of gain error calibration in a pipelined analog-to-digital converter (ADC). In one embodiment, a first stage and a second stage of the pipelined ADC share a common operational amplifier. The first stage is requested to generate the stage output signal thereof according to a first correction number. The second stage is also requested to generate the stage output signal thereof according to a second correction number. A plurality of stage output values generated by stages of the pipelined ADC are collected. The stage output values are respectively correlated with the first correction number and the second correction number to estimate a first gain error estimate of the first stage and a second gain error estimate of the second stage. The first gain error estimate and the second gain error estimate are weighted to obtain a predicted gain error for gain error calibration in the first stage and the second stage.01-29-2009
20080258949Digital background correction of nonlinear error ADC's - The invention provides circuits and methods for estimating and correcting nonlinear error in analog to digital converters that is introduced by nonlinear circuit elements, for example one or more residue amplifiers in a pipelined analog to digital converter integrated circuit. In a preferred method of the invention, pseudo random calibration sequences are introduced into the digital signal to be converted by a flash digital to analog converter in one or more initial stages of the pipelined analog to digital converter circuit. A digital residue signal of the output of the one or more initial pipelined analog to digital converter stages is sampled. Intermodulation products of the pseudo random calibration sequences that are present in the digital residue signal are determined to estimate nonlinear error introduced by the residue amplifier in the one or more stages. A digital correction signal is provided to the output of the one or more stages to cancel estimated nonlinear error.10-23-2008
20100073208APPARATUS AND METHOD FOR THE CALIBRATION OF DELTA-SIGMA MODULATORS - The application relates to a calibration apparatus and calibration method for a tuneable resonator of a delta-sigma modulator of the continuous time, band pass type. The calibration apparatus comprises: a resonator driver capable of causing an oscillating behaviour in a resonator output signal, a reference signal source that provides a reference signal, a frequency detector that provides a frequency relation signal corresponding to the frequency relation between the resonator output signal and the reference signal, and a controller that controls the tuneable resonator in dependence from the frequency relation signal so as to reduce frequency deviation.03-25-2010
20100073207Delta-Sigma Analog-to-Digital Converters and Methods to Calibrate Delta-Sigma Analog-to-Digital Converters - Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate methods to delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, and is configured to provide a feedback signal to a summing device, which generates a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, receive error coefficients corresponding to the selected unit elements, and adjust the n-bit digital signal based on the received error coefficients.03-25-2010
20130076546CHARGE COMPENSATION CALIBRATION FOR HIGH RESOLUTION DATA CONVERTER - A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.03-28-2013
20130082854REDUCING METASTABILITY IN ANALOG TO DIGITAL CONVERSION - A system for performing analog-to-digital conversion comprises a sampling unit that generates multiple digital samples from an analog input signal at each recurrence of a periodic interval, and a processing unit that combines the digital samples to produce a digital output signal. In certain embodiments, the sampling unit comprises multiple analog-to-digital converters arranged in parallel, and the processing unit comprises a digital signal processor that detects outliers in the digital samples and averages any non-outliers among the digital samples to generate the digital output signal.04-04-2013
20130038477Capacitor Mismatch Error Correction in Pipeline Analog-to-Digital Converters - Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed. A plurality of pipeline element circuits are provided, where each pipeline element circuit corresponds to a given bit of the pipeline ADC. A first pipeline element circuit is configured to digitize analog A and B capacitor mismatch error calibration voltages generated by all the pipeline element circuits of the ADC when the pipeline ADC is operating in a capacitor mismatch calibration phase. According to one embodiment, digital representations corresponding to A and B capacitor mismatch error calibration voltages for each of the pipeline element circuits are provided to an output shift register and summing circuit, which generates capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit. The capacitor mismatch error correction codes are applied to each bit weight of the pipeline ADC after conversion of analog signals input to the pipeline ADC has been completed.02-14-2013
20100045496SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device is described which includes a first comparator judging the level of an input signal based on a first judgment value, a second comparator judging the level of the input signal based on a second judgment value, and a calibrator outputting a control signal for starting the calibration of the second judgment value in the case that the calibration of the first judgment value is ended.02-25-2010
20130049999ANALOG/DIGITAL CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.02-28-2013
20130050000Synthesis Method Of Sigma-delta Modulator Capable Of Relaxing Circuit Specification And Reducing Power - A synthesis method of Sigma-Delta modulator capable of relaxing circuit specification and reducing power consumption, comprising the following steps: firstly, set a target bandwidth and a target performance; upon obtaining a Noise Transfer Function (NTF), perform coefficient synthesis a first time, to ascertain a plurality sets of first performance results corresponding to said NTF, and obtain a plurality sets of first circuit specifications fulfilling said said target performance, through analyzing circuit non-ideal effect of said first performance results. Next, increase an oversampling ratio of parameters, to obtain a plurality sets of second performance results, and a plurality sets of second circuit specifications. Then, increase quantizer bit number, and increase attenuation quantity, to obtain a plurality sets of third circuit specifications. Finally, compare said first, second and third circuit specifications, to select one of greatest variation to perform calibrations.02-28-2013
20130088375INPUT-INDEPENDENT SELF-CALIBRATION METHOD AND APPARATUS FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER WITH CHARGE-REDISTRIBUTION DIGITAL TO ANALOG CONVERTER - A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.04-11-2013
20090303091Time-to-Digital Conversion With Calibration Pulse Injection - A time-to-digital converter having at least one chain of delay elements, wherein a status of the chain of delay elements represents a digital signal relating to a time interval to be converted, wherein the time-to-digital converter having an injector for injecting a calibration pulse of known position and/or known duration in time into the chain of delay elements, wherein a first status of the chain of delay elements being expected in response to the calibration pulse, the time-to-digital converter further having a capturer for capturing the actual status of the chain of delay elements in response to the calibration pulse, a calculator for calculating a deviation between the expected first status and the actual status, and a combination unit for taking into account the deviation when converting the time interval to the digital signal.12-10-2009
20090040083ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.02-12-2009
20090091482DIGITAL CALIBRATION TYPE ANALOG-TO-DIGITAL CONVERTER AND WIRELESS RECEIVER CIRCUIT AND WIRELESS TRANSCEIVER CIRCUIT USING THE SAME - In a wireless chip receiving the multi-rate data according to the related art, power consumption and a circuit area of an analog-to-digital converter become large. In a digital calibration type analog-to-digital converter including both a reference analog-to-digital conversion unit and a main analog-to-digital conversion unit, when processing the high-sample rate wireless receive signal, both the reference analog-to-digital conversion unit and the main analog-to-digital conversion unit are operated to configure a general digital calibration type analog-to-digital converter, and when processing a low-sample rate wireless receive signal, analog-to-digital conversion is performed by using the reference analog-to-digital conversion unit and operations of the main analog-to-digital conversion unit or the like are stopped to remarkably reduce power consumption.04-09-2009
20090267815METASTABILITY ERROR REDUCTION IN SIGNAL CONVERTER SYSTEMS - Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds V10-29-2009
20110012763Background Calibration of Analog-to-Digital Converters - A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.01-20-2011
20120223848Calibration Device for Mobile Terminal and ADC Module Thereof - The present invention relates to the field of mobile terminal technology and describes a calibration device for a mobile terminal and an ADC module thereof, the ADC module being disposed inside a baseband chip. The calibration device includes a bandgap voltage reference inside the mobile terminal platform for generating a reference voltage; the device further includes a circuit for connecting the bandgap voltage reference, the circuit being connected with the ADC module for providing the reference voltage generated by the bandgap w voltage reference to the ADC module. The present invention uses a bandgap voltage reference inside a mobile terminal platform to provide voltage to an ADC module, which, during the ADC module calibration, does not require an external reference voltage source to perform the ADC calibration, and therefore greatly reduces calibration errors and improves calibration efficiency.09-06-2012
20130162454HIGH-SPEED SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.06-27-2013
20090237280METHOD, SYSTEM AND APPARATUS FOR DUAL MODE OPERATION OF A CONVERTER - Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.09-24-2009
20120235842Apparatus and Methods Thereof for Reducing Energy Consumption for PWM Controlled Integrated Circuits in Vehicles - An apparatus, protocol and methods for reducing vehicle energy consumption and for precise electronic event control, by implementing full CPU off-loading, using pulse-width modulation (PWM) with analog feedback diagnosis enabling real-time operation. Accordingly, analog feedback is used for external integrated circuits (IC) controlled by a PWM output, for processes to be analyzed. The apparatus includes a microprocessor that integrates an autonomous PWM module and an analog-to-digital converter (ADC) group manager, each including register modules for enabling analog-to-digital signal conversion comparisons of PWM feedback data, and generating of an interrupt command when required, and more specifically to automatically initiate transfer of data from the ADC to memory responsive of an interrupt trigger. As may be necessary the output of the ADC is calibrated or otherwise scaled to enable proper operation.09-20-2012
20090195424A/D Converter Comprising a Voltage Comparator Device - The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.08-06-2009
20110006934PROGRAMMABLE SEGMENTED DIGITAL-TO-ANALOG CONVERTER (DAC) - Provided herein are segmented digital to analog converters (DACs), methods for use therewith, and systems that include one or more such DACs. According to an embodiment, a DAC includes a plurality of sub-DACs, a DAC input adapted to receive a multi-bit digital input and a DAC output adapted to output an analog output current in response to and indicative of the digital input. Each sub-DAC is adapted to receive a separate reference current that specifies a transfer function of the sub-DAC. A magnitude of the reference current provided to each sub-DAC is separately programmable to thereby separately control a gain of each sub-DAC.01-13-2011
20130015990TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.01-17-2013
20100103007FAST FOURIER TRANSFORMATION-BASED ANALOG-TO-DIGITAL CONVERTER CALIBRATION SYSTEM - The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.04-29-2010
20110025536PIPELINE A/D CONVERTER - In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (02-03-2011
20090309772BACKGROUND CALIBRATION SYSTEM FOR CALIBRATING NON-LINEAR DISTORTION OF AMPLIFIER AND METHOD THEREOF - The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier.12-17-2009
20120001784Integrating (SLOPE) DAC Architecture - A current source is used to pre-charge a capacitor to a known value. The capacitor can then be connected to a unity gain buffer to provide a low cost DAC. The DAC can include a self-calibration stage to improve accuracy. The DAC can include two or more circuit branches, each including a current source and a capacitor, where each branch can be calibrated and operated separately to reduce mismatch and to provide a continuous analog voltage output.01-05-2012
20110291868Method for detecting errors of an A/D converter - A method for detecting errors of an A/D converter which is designed for converting an analog input signal into a digital output signal. The digital output signal represents a number z which results from an input value of the analog input signal when an A/D conversion is carried out. In the method, a value range for all possible numbers z is subdivided into subranges, and a value range for all possible input values is subdivided into subranges and an input value and a number z corresponding thereto are associated in each case with subranges which correspond to one another. In the method, a check is made to determine with which subrange an input value which is to be converted is associated, and with which subrange a number which is ascertained by the A/D converter is associated. An error is detected when the number and the input value are associated with subranges which do not correspond to one another.12-01-2011
20090167578ANALOG-TO-DIGITAL CONVERTER AND COMMUNICATION DEVICE AND WIRELESS TRANSMITTER AND RECEIVER USING THE SAME - In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.07-02-2009
20100033358Self-Testing Digital-to-Analog Converter - One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.02-11-2010
20090146854PIPELINE TYPE A/D CONVERTER APPARATUS PROVIDED WITH PRECHARGE CIRCUIT FOR PRECHARGING SAMPLING CAPACITOR - In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.06-11-2009
20080238740Methods and systems for calibrating a pipelined analog-to-digital converter - A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.10-02-2008
20100127905METHOD FOR CALIBRATING ANALOG-TO-DIGITAL CONVERTING CIRCUITS - A method for calibrating at least one analog-to-digital converting circuits includes: during a wafer level probe testing or a chip level testing, inputting at least one calibration signal into the analog-to-digital converting circuit to generate at least one digital signal; and calibrating gain or offset of the analog-to-digital converting circuit according to at least the digital signal.05-27-2010
20120306674AUTOMATIC OFFSET ADJUSTMENT FOR DIGITAL CALIBRATION OF COLUMN PARALLEL SINGLE-SLOPE ADCS FOR IMAGE SENSORS - Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.12-06-2012
20100141492LOW POWER CONSUMPTION ANALOG-TO-DIGITAL CONVERTER - A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.06-10-2010
20100085227Stage-Resolution Scalable Opamp-Sharing Technique for Pipelined/Cyclic ADC - An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.04-08-2010
20100079320DIGITAL TO ANALOG CONVERTER - A digital to analog converter (DAC) converting a digital code to an output voltage and capable of self calibration. The DAC includes a self-calibration signal generator generating a self-calibration signal based on the output voltage, a constant current generator, a first and a second current provider and a current-voltage converter. The current generating elements of the first and second current providers provide proportional currents, and are enabled/disabled according to the self-calibration signal and the digital code, respectively. The constant current is divided into the actual working current generating elements of the first current provider, and an output current is generated by the actual working current generating elements of the second current provider. The output current is converted to the output voltage by the current-voltage converter.04-01-2010
20100079317METHOD AND APPARATUS FOR TESTING DATA CONVERTER - A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.04-01-2010
20100079319DATA CONVERSION CIRCUITRY AND METHOD THEREFOR - A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.04-01-2010
20100079318DATA CONVERSION CIRCUITRY AND METHOD THEREFOR - A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.04-01-2010
20090273497METHOD AND APPARATUS FOR CALIBRATING AN RDAC FOR END-TO-END TOLERANCE CORRECTION OF OUTPUT RESISTANCE - A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.11-05-2009
20090278716SAMPLE HOLD CIRCUIT FOR USE IN TIME-INTERLEAVED A/D CONVERTER APPARATUS INCLUDING PARALLELED LOW-SPEED PIPELINE A/D CONVERTERS - A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.11-12-2009
20100117878PILOT-TONE CALIBRATION FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.05-13-2010
20110169671METHOD FOR TESTING NONLINEARITY ERROR OF HIGH SPEED DIGITAL-TO-ANALOG CONVERTER - A novel method applies the down-conversion sampling technology to test a high-speed digital-to-analog conversion. In the method, a digital-to-analog conversion output signal of a high-speed digital-to-analog converter and a low-frequency sinusoidal carrier wave signal input to a comparator to obtain a low-speed pulse signal. Therefore, the variation of the pulse width of the low-speed pulse signal can be measured by a common logic analyzer to assess the nonlinearity error of the high-speed digital-to-analog converter.07-14-2011
20090261999DEVICE AND METHOD FOR TESTING OF DIGITAL-TO-ANALOG CONVERTER - A current-steering digital-to-analog converter (DAC) is tested using a test component having a relaxation oscillator with an oscillation frequency based on the output current of the DAC. A series of test values is provided in sequence to the DAC for conversion to an output current with a magnitude that varies with the test values. The test component counts the number of oscillations (“the oscillation count”) of the relaxation oscillator over a fixed duration that is substantially equal for each test value. As the number of oscillations over the fixed duration depends on the oscillation frequency of the relaxation oscillator, which in turn is based on the magnitude of the output current, the oscillation count can be used as a relative measure of the magnitude of the output current for the corresponding test value. Accordingly, the oscillation counts for the test values can be used to determine operational characteristics of the DAC.10-22-2009
20120194369RING OSCILLATOR DELTA SIGMA ADC MODULATOR WITH REPLICA PATH NONLINEARITY CALIBRATION - An embodiment provides a continuous-time delta-sigma modulator for analog-to-digital conversion. The modulator includes a signal path generating including a ring voltage controlled oscillator driven by an analog input signal. The signal path produces digital values by sampling the ring voltage controlled oscillator. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects the digital values based upon determined nonlinear distortion coefficients. Preferred embodiment ADC ΔΣ modulators do not require any analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low jitter clock.08-02-2012
20110205093LOGARITHMIC ANALOG/DIGITAL CONVERSION METHOD FOR AN ANALOG INPUT SIGNAL, AND CORRESPONDING DEVICE - A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.08-25-2011
20100103006ADC TEST CIRCUIT AND SEMICONDUCTOR DEVICE - An ADC test circuit has an expected value generator configured to generate an expected value signal for a converted output signal of an ADC (Analog to Digital Converter), a test signal generator configured to generate an input test signal applied to the ADC based on the expected value signal, and a comparator configured to compare the converted output signal of the ADC corresponding to the applied input test signal with the expected value signal.04-29-2010
20100060498CALIBRATION CIRCUIT AND ASSOCIATED METHOD - A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.03-11-2010
20080238739SYSTEM AND METHOD FOR CALIBRATING DIGITAL-TO-ANALOG CONVERTORS - A system and method for calibrating a digital-to-analog converter (DAC) is disclosed, the method comprises providing a plurality of spare bits to each of a group of DAC bits that are designated for calibration, calibrating a first DAC bit of the group of DAC bits using its corresponding plurality of spare bits, and keeping a second DAC bit of the group of DAC bits unchanged while calibrating the first DAC bit.10-02-2008
20100201551AUTOMATIC COMMON-MODE REJECTION CALIBRATION - The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (08-12-2010
20090167577CIRCUIT AND METHOD FOR CALIBRATING DIRECT CURRENT OFFSET - A circuit and a method for calibrating the direct-current offset in the signal output from a signal processing unit are disclosed. The calibration circuit includes a 1-bit quantizer, a control logic unit and a digital-to-analog converter. The 1-bit quantizer is coupled to the output end of the signal processing unit for receiving and detecting a direct-current offset component in the output signal so as to obtain quantization information. The control logic unit is coupled to the 1-bit quantizer for sequentially setting one of a plurality of bits of a compensation value and updating the set bit according to the quantization information. The digital-to-analog converter is coupled to the control logic unit for compensating the direct-current offset component in the signal output from the signal processing unit according to the compensation value.07-02-2009
20090033528TEST APPARATUS, MANUFACTURING METHOD, AND TEST METHOD - There is provided a test apparatus for testing a device under test, the test apparatus including: a test signal supplying section that supplies a digital input signal for testing purposes, to the device under test; a reference signal output section that outputs an analogue reference signal in accordance with the digital input signal; a difference obtaining section that outputs an analogue difference signal representing a difference between the analogue reference signal and an analogue output signal outputted by the device under test in accordance with the digital input signal; and a determining section that determines whether the analogue output signal shows a defect or not based on the analogue difference signal.02-05-2009
20110205094METHOD, SYSTEM AND APPARATUS FOR OPERATION OF A CONVERTER - Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.08-25-2011
20080309529Sigma Delta Modulators - A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behaviour has been observed, and major changes to design are not normally required to implement the detection mechanism.12-18-2008
20080238741SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF SCREENING CONFORMING DIGITAL-ANALOG CONVERTERS AND ANALOG-DIGITAL CONVERTERS TO BE MOUNTED BY AUTO-CORRELATION ARITHMETIC OPERATION - A semiconductor integrated circuit includes a test signal generating section which generates a test signal at the time of a test, a digital-analog converter which converts the test signal into an analog signal, an analog-digital converter which fetches a signal output from the digital-analog converter and converts the fetched signal into a digital signal, and an operating section which performs an auto-correlation arithmetic operation of a signal output from the analog-digital converter. The semiconductor integrated circuit further includes an evaluating section which evaluates presence/absence of distortion of the digital-analog converter and the analog-digital converter based on consistency of an auto-correlation arithmetic operation result in the operating section and a predetermined reference signal.10-02-2008
20090128382SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING APPARATUS, AND SEMICONDUCTOR DEVICE TESTING METHOD - In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution.05-21-2009
20120139766Digital to Analog Converter Circuits and Methods - The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to-analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit.06-07-2012
20120068867SAMPLING/QUANTIZATION CONVERTERS - Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple quantization-noise-shaping continuous-time filters, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter.03-22-2012
20090051574METHOD FOR GAIN ERROR ESTIMATION IN AN ANALOG-TO-DIGITAL CONVERTER AND MODULE THEREOF - The invention provides a method for gain error estimation in an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. A series of correction numbers applied to a target stage selected from the stages are correlated with a series of calculation values calculated according to digital output values of the stages to generate a series of gain error estimates. The series of gain error estimates are multiplied by a series of updating parameters to obtain a series of first values. A series of previous gain error values are multiplied by one minus the corresponding updating parameters to obtain a series of second values, wherein the series of previous gain values are obtained by delaying the present gain error values. The series of first values and the series of second values are correspondingly added to obtain a series of present gain error values for gain error correction.02-26-2009
20110227770DIGITAL-TO-ANALOG CONVERTER (DAC) - A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.09-22-2011
20090201185Analog-to-Digital Conversion Circuit - An analog-to-digital conversion circuit and a method for calibrating an analog-to-digital conversion circuit are provided. A digital translation of an analog voltage is analyzed to determine a characteristic value of the analog voltage. A reference voltage, with which the digital translation is generated, is set to a value that is a minimum amount greater than the characteristic value. Additional embodiments include setting an offset voltage, with which the digital translation is also generated.08-13-2009
20100149008Switching unit for generating an output voltage as a function of a digital data valve and method for calibrating the switching unit - With analog output stages of digital systems, the relationship between a digital data value, which is assigned to an analog output stage and to an actually generated output voltage, often does not correspond to a desired characteristic curve. A switching unit is provided to generate an output voltage as a function of a digital data value, the characteristic curve of which is adjusted by a calibration voltage. A method for calibrating a corresponding switching unit is also provided. The switching unit and the method are used in controllers.06-17-2010
20120194368METHOD AND SYSTEM FOR CALIBRATING COLUMN PARALLEL ADCS - Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.08-02-2012
20120194367CONTINUOUS RAMP GENERATOR DESIGN AND ITS CALIBRATION FOR CMOS IMAGE SENSORS USING SINGLE-RAMP ADCS - Aspects of the invention provide a continuous ramp generator design and its calibration for CMOS image sensors using single-ramp ADCs. An embodiment of the invention comprises controlling a coarse gain, integer gain, and fine gain of the analog-to-digital converter. Gain of the analog-to-digital converter may be calibrated by tuning the integer gain based on reference voltages converted to equivalent digital values.08-02-2012
20100156682METHOD FOR ACHIEVING HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION WITHOUT DEGRADING ACCURACY, AND ASSOCIATED APPARATUS - A method for achieving high-speed analog-to-digital conversion without degrading accuracy includes: receiving digital outputs of a plurality of pipelined analog-to-digital converters (ADCs) that perform analog-to-digital conversion on a same analog signal; and performing digital calculations on the digital outputs to generate a calibrated digital output. An apparatus for achieving high-speed analog-to-digital conversion without degrading accuracy is further provided. The apparatus includes: a digital module arranged to receive digital outputs of a plurality of pipelined ADCs that perform analog-to-digital conversion on a same analog signal. In addition, the digital module includes a plurality of digital calculation paths respectively corresponding to the pipelined ADCs, wherein each digital calculation path corresponding to an associate pipelined ADC of the pipelined ADCs is electrically connected to the associate pipelined ADC. The digital module performs digital calculations on the digital outputs to generate a calibrated digital output.06-24-2010
20100149009CALIBRATION METHOD, A/D CONVERTER, AND RADIO DEVICE - There is disclosed a calibration method for an A/D converter. The A/D converter includes a first amplifier to amplify first and second voltage signals, a second amplifier to amplify the first and second voltage signals amplified by the first amplifier, and a comparator to compare the first and second voltage signals amplified by the second amplifier. The calibration method performs short-circuiting input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a first result, calibrating output voltage of the second amplifier according to the first result, short-circuiting input ports of the first amplifier, opening the short-circuited input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a second result, and calibrating output voltage of the first amplifier according to the second result.06-17-2010
20090121907D-A CONVERT APPARATUS AND A-D CONVERT APPARATUS - Provided is a D-A conversion apparatus that outputs an analog output voltage according to digital input data, which includes a capacitance array main D-A converter that supplies a main voltage according to the input data to an output terminal of the D-A conversion apparatus, a correction data output section that outputs correction data according to the input data, a capacitance array correction D-A converter that outputs a correction voltage according to the correction data, and a voltage dividing capacitor connected serially between an output end of the correction D-A converter and an output end of the main D-A converter.05-14-2009
20100156681METHOD AND MODULE WITH ANALOG-TO-DIGITAL CONVERTER - A method and module with analog-to-digital converter. One embodiment provides for testing an analog-to-digital converter, including generating a voltage ramp. The voltage ramp is converted to a digital signal using the ADC at a rate of a clock signal. A first parameter is calculated according to the clock signal and the digital signal on the chip. The first parameter is indicative of conversion characteristics of the ADC.06-24-2010
20100176976CALIBRATION CIRCUIT AND METHOD FOR A/D CONVERTER - An analog to digital conversion circuit comprises a first digital noise cancellation filter (07-15-2010
20100182175Current Sensing and Background Calibration to Match Two Resistor Ladders - In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.07-22-2010
20100259429METHODS AND APPARATUS FOR ERROR CANCELATION IN CALIBRATED CURRENT SOURCES - Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.10-14-2010
20100001888ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes a reference voltage generator that outputs a reference voltage, a first comparator and a second comparator that compare the reference voltage and a voltage of an input signal and output a digital signal having a first logical value or a second logical value, and a calibrator that compares an output of the first comparator and an output of the second comparator and outputs a first offset control signal and a second offset control signal. The first comparator sets an offset value having a positive or negative polarity to an output inversion threshold level based on the first offset control signal, and the second comparator sets an offset value having a polarity opposite to the polarity set by the first comparator to an output inversion threshold level based on the second offset control signal.01-07-2010
20100013685METHOD AND APPARATUS FOR INTERNALLY CALIBRATING MIXED-SIGNAL DEVICES - A method to tune electronic devices in general using R/2R ladder networks to obtain fixed or variable accurate properties that may include, but are not limited to resistance, current, voltage, and/or timing. As a particular application, a method for internally calibrating a digital-to-analog converter is shown in detail. The DAC uses an extended R/2R ladder to improve the converting accuracy by mapping the extended bits into the original bits. A mapping matrix is maintained, which can be rewritten by an internal calibration process.01-21-2010
20100149007ELECTRONIC CONTROL UNIT HAVING ANALOG INPUT SIGNAL - An analog input signal obtained from an analog sensor group 06-17-2010
20100225513Self-Calibrating Pipeline ADC and Method Thereof - An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation.09-09-2010
20110109487INTEGRATED NON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS) - INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL >−1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2̂N possible digital input codes (that can be accepted by the DAC) to more than 2̂N possible digital output codes, to ensure that all values of DNL >−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.05-12-2011
20100164767DIGITAL CALIBRATION TYPE ANALOG-TO-DIGITAL CONVERTER AND WIRELESS RECEIVER CIRCUIT AND WIRELESS TRANSCEIVER CIRCUIT USING THE SAME - In a wireless chip receiving the multi-rate data according to the related art, power consumption and a circuit area of an analog-to-digital converter become large. In a digital calibration type analog-to-digital converter including both a reference analog-to-digital conversion unit and a main analog-to-digital conversion unit, when processing the high-sample rate wireless receive signal, both the reference analog-to-digital conversion unit and the main analog-to-digital conversion unit are operated to configure a general digital calibration type analog-to-digital converter, and when processing a low-sample rate wireless receive signal, analog-to-digital conversion is performed by using the reference analog-to-digital conversion unit and operations of the main analog-to-digital conversion unit or the like are stopped to remarkably reduce power consumption.07-01-2010
20100103008System and method of signal sensing, sampling and processing through the exploitation of channel mismatch effects - A system for sensing, sampling and processing an input signal includes an encoding subsystem for sensing and sampling the input signal into a plurality of distinct data paths using a sub-Nyquist sampling rate. The system architecture is designed to induce encoded variations between the plurality of data paths, such as channel differences in amplitude or phase. The system additionally includes a decoding subsystem for reconstructing the encoded signal back to its original bandwidth. Preferably, the decoding subsystem exploits mismatch effects between the plurality of data paths as a form of signal diversity to resolve ambiguities introduced from sub-Nyquist signal sampling during signal reconstruction.04-29-2010
20130127648SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.05-23-2013
20090322574TIME-TO-DIGITAL CONVERSION WITH DELAY CONTRIBUTION DETERMINATION OF DELAY ELEMENTS - A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal.12-31-2009
20090073012SELF-CALIBRATING DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - A digital-to-analog converter improves differential non-linearity by performing a calibration of at least one weighted cell in response to a calibration command. The digital-to-analog converter includes a group of weighted cells, a tunable cell having a tunable weight controlled by a tuning word, and a calibration cell to generate a combined output signal in response to a digital input word, the calibration command, and a calibration sequence. The digital-to-analog converter also includes a calibration circuit configured to sample and subsequently process the combined output signal to establish the tuning word in accordance with the calibration command and the calibration sequence.03-19-2009
20080309528Device for detecting voltage and analog-to-digital converter (ADC) using the same - A voltage detecting device and an analog-to-digital converter (ADC) using the same are provided. The voltage detecting device determines whether input voltage is higher than threshold voltage based on contact of a strip and a membrane. Therefore, high resolution and high speed operation is possible, but with consuming lower power, and an element capable of performing the function of resistor and comparator is provided. Furthermore, a more effective ADC may be provided using the above.12-18-2008
20110032128ANALOG-DIGITAL CONVERTER CIRCUIT AND CALIBRATION METHOD - Provided is an analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter including: a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and a first calibration circuit that adjusts an offset voltage of the first comparator. In the calibration mode, assuming that a calibration resolution of the first calibration circuit is Δ02-10-2011
20090109072Testing of Analog to Digital Converters - Methods and apparatus, including computer program products, to test analog to digital converters, are disclosed. In general, data is received that characterizes a first digital code from a device under test at a first analog voltage of an analog signal generator and a second digital code being a digital code threshold, and a step size is generated for another test of the device by performing a calculation by a processor. The calculation may include multiplying a least significant bit size of the device with a difference of the first and second digital codes to generate a product, and dividing the product by a least significant bit size of the analog signal generator. The first digital code may be calculated from results from multiple subtests in the test, where each of the subtests includes multiple analog to digital conversions by the device at the first analog voltage.04-30-2009
20110128171ANALOG/DIGITAL CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.06-02-2011
20110122006CALIBRATION METHOD AND RELATED CALIBRATION APPARATUS FOR CAPACITOR ARRAY - A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.05-26-2011
20110241914TEST SYSTEM AND METHOD FOR ANALOG-TO-DIGITAL CONVERTER - Test system and method for analog-to-digital converter (ADC) based on a loopback architecture are provided to test an M-bit ADC. In the invention, an N-bit digital-to-analog converter (DAC) converts a digital input to a basic test signal, a segmentation circuit scales the basic test signal and superposes it with segmentation DC levels for providing corresponding segmented test signals, such that the ADC converts the segmented test signals to reflect result of testing. With the invention, practical loopback architecture of low-cost can be adopted for testing.10-06-2011
20110043395DIGITAL BACKGROUND CALIBRATION IN PIPELINED ADCS - Digital background calibration in a pipelined ADC is performed by extracting a capacitor mismatch value Δ that represents a mismatch between a sampling capacitor C02-24-2011
20110109488Analog-to-digital converter - An analog-to-digital converter includes a higher-order analog-to-digital converter that outputs a higher-order digital value, a first lower-order converter that converts a first residual signal into a first lower-order digital value, a second lower-order converter that converts a second residual signal into a second lower-order digital value, a calibrator that outputs first and second offset adjustment signals for respectively designating offset adjustment amounts in reversed polarity based on a difference between the first and second lower-order digital values, wherein the first and second lower-order converters set a conversion calibration value based on the first and second offset adjustment signals and calibrate the first and second lower-order digital values based on the conversion calibration value.05-12-2011
20110043394SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.02-24-2011
20110241915Digital-to-Analog Converter - A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.10-06-2011
20090033529System and method of multi-channel signal calibration - A signal processing system for reducing calibration-related distortions in a complete-channel signal generated by a multi-channel subsystem, such as an interleaved ADC, includes a channel separator for separating the distorted digital signal into its various sub-channels and a single-channel corrector for independently processing each sub-channel to reduce distortion products present therein. The system additionally includes a subchannel re-combiner for combining the plurality of sub-channels processed by the single-channel corrector and a multi-channel corrector for calibrating each of plurality of sub-channels relative to one another to yield an equalized, complete-channel output signal. The multi-channel corrector includes a bank of optimized filters, each filter being assigned to a corresponding sub-channel of the complete-channel signal. In one embodiment, one of the plurality of sub-channels is selected as an ideal reference signal and the filters assigned to the remaining sub-channels are optimized to yield outputs which match the ideal reference signal.02-05-2009
20100219996DC OFFSET DETECTION AND CORRECTION FOR USER TRAFFIC - In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.09-02-2010
20100039302Correlation-based background calibration of pipelined converters with reduced power penalty - A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.02-18-2010
20110175760METHOD FOR CALIBRATING ANALOG-TO-DIGITAL CONVERTING CIRCUITS - A method for calibrating at least one analog-to-digital converting circuit includes: during a wafer level probe testing, inputting at least one calibration signal provided by a wafer level testing machine into the analog-to-digital converting circuit to generate at least one digital signal; and calibrating the analog-to-digital converting circuit according to at least the digital signal. The analog-to-digital converting circuit is applied to a video system or an audio system.07-21-2011
20090027246ANALOG-TO-DIGITAL CONVERTER AND METHOD OF GAIN ERROR CALIBRATION THEREOF - The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value. The look-ahead module generates the auxiliary output value according to the stage output value of the target stage, wherein the auxiliary output value is not affected by the correction number.01-29-2009
20100117877CALIBRATING REPLICA DIGITAL-TO-ANALOG CONVERTERS - A system includes a first digital-to-analog converter (DAC), a replica DAC, a control module, and a calibrating DAC. The first DAC receives a first input and generates a first analog output based on the first input. The replica DAC receives the first input and generates a replica analog output based on the first input. The control module generates a first control based on the first input. The calibrating DAC generates a calibration analog output based on the first control. The calibration analog output adjusts the replica analog output.05-13-2010
20080266153HIGH RESOLUTION DIGITAL ANALOG CONVERSION CIRCUIT - To increase the accuracy and resolution of an m bit digital analog converter, n bit input values with n>m are fed to a control circuit and converted to a series of control values for the digital analog converter using dithering techniques. When the series of control values straddles a major transition where a large number of bits are switched between 1 and 0, a corrected series of control values is retrieved from a calibration table. The corrected series takes into account the glitch effects observed at the output of digital analog converter at a major transition.10-30-2008
20120169521CALIBRATION OF TIME CONSTANTS IN A CONTINUOUS-TIME DELTA-SIGMA CONVERTER - A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.07-05-2012
20110068962Programmable Settling for High Speed Analog to Digital Converter - In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.03-24-2011
20100066575Methods and Systems for Calibrating a Pipelined Analog-to-Digital Converter - This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.03-18-2010
20110037632ADC CALIBRATION - An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual.02-17-2011
20120098687METHOD AND APPARATUS FOR SELF-TESTING A DIGITAL-TO-ANALOG CONVERTER (DAC) IN AN INTEGRATED CIRCUIT - An on-chip self testing digital-to-analog converter (DAC) is provided. The functionality of the DAC is measured using a combination of integral non-linearity (INL) and differential non-linearity (DNL). Parts may pass or be rejected based on the testing. When a DAC passes the testing, the process continues to the next DAC or quits if all the DACs have been tested.04-26-2012
20100103005Self Auto-Calibration of Analog Circuits in a Mixed Signal Integrated Circuit Device - Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (A04-29-2010
20110316730ANALOG UNIT - An ADC code given in response to input of an analog input value to an A/D converter circuit is measured at a site where an A/D converter unit is used to measure a user-measured value. A user-set value calculating part calculates a user offset value and a user gain value on the basis of one user-measured value, a factory offset value, and a factory gain value, and stores the calculated user offset value and the user gain value in a nonvolatile memory.12-29-2011
20120044102TIME-TO-DIGITAL CONVERTER WITH BUILT-IN SELF TEST - Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices.02-23-2012
20120007757DIGITAL-TO-ANALOG CONVERTER (DAC) CALIBRATION SYSTEM - The present invention relates generally to a digital-to-analog converter (DAC) calibration. The present invention may be implemented by a DAC calibration system including a first current source, a first switch coupled to the first current source, a second current source, a second switch coupled to the second current source, an output node coupled to the first switch and the second switch, a first calibration module coupled to the output node, an average current measurement module coupled to the first calibration module, and a second calibration module coupled to the average current measurement module.01-12-2012
20120013493CORRECTION SIGNAL GENERATOR AND ANALOG-TO-DIGITAL CONVERTER - A correction signal generator generates a correction signal that corrects a digital signal obtained from an analog input voltage. The correction signal generator has a correction signal output circuit that holds the number of transit stages of delay units detected by a first stage count detection circuit and a third stage count detection circuit at the timing corresponding to the difference in the number of stages between the number of transit stages of delay units detected by the first stage count detection circuit and the number of transit stages of delay units detected by a second stage count detection circuit, and outputs the difference between the number of stages from the first stage count detection circuit and the number of stages from the third stage count detection circuit, which were held, as the correction signal.01-19-2012
20120206282TEST CIRCUITS AND METHODS FOR REDUNDANT ELECTRONIC SYSTEMS - A redundant analog-to-digital conversion system can include at least one input multiplexer, first and second redundant analog-to-digital converters, a comparison circuit and an output multiplexer. The at least one input multiplexer can receive a plurality of analog input signals and output at lest one multiplexed analog input signal. The first and second redundant analog-to-digital converters can convert the at least one multiplexed analog input signal to respectively generate first and second digital output signals, the first digital output having a greater digital resolution than the second digital output. The comparison circuit can produce a comparison output signal as a function of a comparison of a plurality of most significant corresponding bit pairs of the first and second digital output signals. The output multiplexer can produce a multiplexed output including information from the comparison output signal and one of the digital output signals.08-16-2012
20120026024SYSTEM FOR CALIBRATING A TIME CONSTANT OF AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT PROVIDED WITH SUCH A SYSTEM - System and method for calibrating a time constant R02-02-2012
20120249351ADC CALIBRATION - An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.10-04-2012
20100164765DAC calibration circuits and methods - Provided is a DAC with tuning circuitry in accordance with some embodiments for tuning current sources in the DAC. The DAC may be used for a sigma-delta converter in some embodiments.07-01-2010
20110102217Analog-to-digital Converter and Related Calibrating Comparator - An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.05-05-2011
20100289679SYSTEMS AND METHODS FOR VECTOR-BASED ANALOG-TO-DIGITAL CONVERTER SEQUENTIAL TESTING - A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).11-18-2010
20100245140DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - In AD conversion of a voltage under measurement, data continuity is ensured between the result of conversion after amplification by using an amplifier circuit and the result of direct conversion without using the amplifier circuit. In AD conversion operation using a DA converter circuit, an amplifier circuit, and an AD converter circuit under the direction of a control circuit, an analog signal output from the DA converter circuit is directly converted by the AD converter circuit, and also the analog signal is converted therein after amplified by the amplifier circuit with an expected gain of 209-30-2010
20120133536DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.05-31-2012
20120161993DIGITAL ANALOG CONVERTER AND METHOD FOR CALIBRATING CURRENT SOURCES THEREOF - Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.06-28-2012
20090058698System and method for common mode calibration in an analog to digital converter - A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.03-05-2009
20090058699Programmable settling for high speed analog to digital converter - In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.03-05-2009
20120256775METHOD, SYSTEM AND APPARATUS FOR DUAL MODE OPERATION OF A CONVERTER - Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.10-11-2012
20120212359ADC Calibration Apparatus - An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.08-23-2012
20120212360Photonic assisted analog-to-digital conversion using phase detection - A method of digitizing an analog electrical signal combines optical and electronic techniques in order to improve the resolution, sampling rate, input frequency range, or flexibility. It implements an optical interferometric modulator, which modulates an input optical signal by the input electrical signal combined with a calibration signal. A set of two or more photoreceivers receiving the output optical signals from the optical modulator produce output electrical signals, which are digitized and processed in a DSP to produce a digitized version of the electrical input signal, and a digitized calibration signal value is used to optimize the input electrical signal digitization. The method and the device can be used in many fields including instrumentation, communications, and imaging.08-23-2012
20120176260ANALOG-DIGITAL CONVERTING METHOD AND ANALOG-DIGITAL CONVERTING APPARATUS - An analog-digital converting method comprising measuring, in advance, frequency characteristics of each of a plurality of ADCs; intra-group correction of, for each of a plurality of groups obtained by dividing a plurality of measurement signals, generating measurement signals that would be obtained when the frequency characteristics of the corresponding ADCs are ideal by multiplying the measurement signals by a correction coefficient that is based on the frequency characteristics of all the ADCs in the group; and inter-group correction of correcting and combining the frequency characteristics of the groups based on a difference in the frequency characteristics between the groups formed during the intra-group correction, to generate a frequency spectrum of the digital signal.07-12-2012
20120075130METHOD OF TESTING DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS - A method of testing a digital-to-analog or analog-to-digital converter including coarse and fine voltage dividers corresponding respectively to more and less significant bits of the digital signal. Reference input signals are applied corresponding to a first selection of the fine resistor elements with each selection of the coarse resistor elements in succession, corresponding output signals of the converter are measured, and differential non-linearity values and integral non-linearity values for these selections of fine and coarse resistor elements are calculated. Similar measurements and calculations are made for a first selection of the coarse resistor elements with each of the selections of the fine resistor elements in succession. Differential non-linearity values and integral non-linearity values for other combinations of the coarse resistor elements with the fine resistor elements are then calculated using combinations of the calculated differential non-linearity values and the calculated integral non-linearity values.03-29-2012
20100007535Circuit with Calibration Circuit Portion - In an embodiment, a circuit is disclosed comprising a circuit portion coupled to a terminal and a calibration circuit portion coupled to said terminal.01-14-2010
20090315746METHOD AND SYSTEM FOR CALIBRATING AN ANALOGUE I/Q-MODULATOR OF A TRANSMITTER - The invention relates to a method and a system for calibrating an analogue I/Q-modulator (12-24-2009
20120188109Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters - An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.07-26-2012
20100253558PROCESSING APPARATUS FOR CALIBRATING ANALOG FILTER ACCORDING TO FREQUENCY-RELATED CHARACTERISTIC OF ANALOG FILTER, PROCESSING APPARATUS FOR GENERATING COMPENSATION PARAMETER USED TO CALIBRATE ANALOG FILTER, RELATED COMMUNICATION DEVICE, AND METHODS THEREOF - A processing apparatus for calibrating an analog filter of a communication device in a digital domain is disclosed, wherein the analog filter is arranged to perform a filtering operation upon a communication signal in an analog domain. The processing apparatus includes a signal processing circuit and a digital filter. The signal processing circuit is used for transforming the communication signal between the digital domain and the analog domain. The digital filter is coupled to the signal processing circuit, and used for performing a filtering operation upon the communication signal in the digital domain, wherein a frequency response of the digital filter is arranged to compensate a frequency response of the analog filter according to at least a compensation parameter generated with reference to a frequency-related characteristic of the analog filter.10-07-2010
20100328121CIRCUIT TESTING - A method for testing a circuit that generates an n-bit pulse density modulated output in response to an input signal or combination of input signals, for example the analogue section (12-30-2010
20120262319METHOD FOR CALBRATING A PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.10-18-2012
20120262318System and Method for Background Calibration of Time Interleaved Analog to Digital Converters - Various embodiments allow for background calibration of channel-to-channel mismatch errors.10-18-2012
20110001645RANDOMIZATION OF SAMPLE WINDOW IN CALIBRATION OF TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTER - A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).01-06-2011
20110037631DAC CALIBRATION - Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.02-17-2011
20110037630VOLTAGE MODE DAC WITH CALIBRATION CIRCUIT USING CURRENT MODE DAC AND ROM LOOKUP - The invention is a novel scheme of calibrating a voltage-mode digital to analog converter using a current-mode digital to analog converter. A DAC system is comprised of a voltage-mode DAC with an R-2R architecture structure and includes a ROM lookup table where calibration codes associated with each of a plurality of input codes are stored. A reference current is scaled with the calibration codes to output a calibration current that induces adjustments in an output voltage to counteract non-linearities that may be induced by resistor mismatch.02-17-2011
20110037629Coupled Delta-Sigma Modulators - An apparatus and method for reducing error in converting a multi-bit signal to a single bit signal. An analog delta-sigma modulator receives an analog signal and converts it to a multi-bit digital signal that is provided to a digital delta-sigma modulator. The digital delta-sigma modulator introduces error by converting the multi-bit signal to a single-bit signal. The error from the conversion is fed back to the analog delta-sigma modulator which incorporates the error information into the analog signal before it is converted to a multi-bit digital signal.02-17-2011
20110210877CALIBRATION METHODS AND STRUCTURES FOR PIPELINED CONVERTER SYSTEMS - Calibration methods and structures are provided for pipelined analog-to-digital converter systems. They are arranged to process samples of the digital codes with an algorithm that is preferably configured to repeatedly update an estimate of the transfer function with the difference between one of the input signals and the analog equivalent of the corresponding digital code. The calibration methods and structures are further configured to calibrate the transfer function of the converter stage wherein the samples are selected in accordance with various steps. These steps can include the step of injecting dither signals into a flash portion and an MDAC portion of the converter stage to thereby maintain dynamic range. They can also include the step of limiting the samples to those processed through a selected subrange of the subranges. They can further include the step of limiting the samples to those in which the absolute value of the input signals is less that 0.25 of the selected subrange and the absolute value of the dither signals is less that 0.25 of the selected subrange. If the selected subrange is not a central subrange, the steps can further include the step of shifting the samples by a distance between the selected subrange and the central subrange.09-01-2011
20120326903METHOD AND APPARATUS FOR PERFORMING NONLINEARITY CALIBRATION - A method for performing nonlinearity calibration includes the steps of: obtaining temporarily values of a plurality of compensation parameters by performing a perturbation-based calibration process on a nonlinear system with at least one predetermined input being applied to the nonlinear system; and updating the compensation parameters by performing the perturbation-based calibration process in an online manner, wherein the temporarily values are utilized as initial values of the compensation parameters for the step of updating the compensation parameters. In addition, the compensation parameters are utilized for controlling a compensation response of the perturbation-based calibration process. An associated apparatus is also provided.12-27-2012
20130015989System and Method For Providing High Resolution Digital-To-Analog Conversion Using Low Resolution Digital-To-Analog ConvertersAANM Iso; YoshimiAACI TokyoAACO JPAAGP Iso; Yoshimi Tokyo JPAANM Hiroshima; AkaneAACI TokyoAACO JPAAGP Hiroshima; Akane Tokyo JPAANM Tamaki; ToshiyaAACI TokyoAACO JPAAGP Tamaki; Toshiya Tokyo JPAANM Nishimoto; MasashiAACI KanagawaAACO JPAAGP Nishimoto; Masashi Kanagawa JP - DA conversion is performed while improving resolution and reducing the influence of errors. A predetermined weight is applied to an output of at least one of a plurality of DA converters to each of which calibration data is given; the resultant outputs are added by an adder. An output of the adder is converted to a digital value by an AD converter. If the predetermined weight has an error outside an allowable range on the basis of the obtained digital value, a calibrating process of obtaining a correction factor for correcting the digital signal to be converted so as to reduce influence of the error is controlled. When a digital signal is to be converted to an analog signal with high precision, the digital signal is corrected with the correction factor, the resultant value is supplied to the DA converters, and DA converted outputs are added by the adder.01-17-2013
20130169455Calibration of a Charge-to-Digital Timer - A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.07-04-2013
20130169457Resistive/Residue Charge-to-Digital Timer - A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.07-04-2013
20130169456TESTING OF ANALOG-TO-DIGITAL CONVERTERS - Complete testing of an analog-to-digital converter (ADC) can be carried out using digital signals and at high speeds. Circuit elements are added to an ADC so that a first phase of testing may be carried out using a limited number of analog test voltages. The ADC may then be reconfigured using added circuit elements to disable conventional analog-to-digital conversion. A digital signal may then be applied to the ADC to rapidly test all switching elements used in analog-to-digital conversion. According to some implementations, testing times for ADCs may be reduced from hours to milliseconds.07-04-2013
20090189796PIPELINED ANALOG-TO-DIGITAL CONVERTER WITH CALIBRATION OF CAPACITOR MISMATCH AND FINITE GAIN ERROR - The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign. As a result, the two errors can compensate each other to achieve an error-free conversion stage.07-30-2009
20130120175CALIBRATING TIMING, GAIN AND BANDWIDTH MISMATCH IN INTERLEAVED ADCs - A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.05-16-2013
20130141263CALIBRATION METHOD AND CIRCUIT - An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.06-06-2013
20110227769METHOD FOR TESTING A HIGH-SPEED DIGITAL TO ANALOG CONVERTER BASED ON AN UNDERSAMPLING TECHNIQUE - A method for testing a digital to analog converter, which operates in an undersampling environment, wherein signals of a tested DAC and a signal generator are modulated by a PWM device and then processed by a digital processing circuit to generate a digital signal, whereby is formed a low-speed equivalent ADC. The signal generator is provided by uniform-distribution random test patterns, and the signal generator generates an uniform-distribution random analog signal to the equivalent ADC. Thereby, the test error caused by the non-ideality of the signal generator is corrected, and the tested circuit can work in a full speed.09-22-2011
20100283642Digital-to-Analog Converter - A system for converting a digital signal to an analog signal is provided. The present invention provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. The digital-to-analog converter includes a bias regeneration circuit, and three sub-DACs. The bias regeneration circuit provides biasing to the three sub-DACs allowing the DAC to be implemented with smaller circuit area. In addition, the three sub-DACs may be digitally calibrated during the conversion process to increase the linearity of the DAC.11-11-2010
20100289680Self-Calibrated Current Source and DAC Using the Same and Operation Method Thereof - A background self-calibrated DAC is presented. In the present invention, a virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The aforesaid DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.11-18-2010
20120256774METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER - A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.10-11-2012
20120274493Digital-to-Analog Converter circuit with Rapid Built-in Self-test and Test Method - A digital-to-analog converter circuit with rapid built-in self-test is disclosed. The digital-to-analog converter includes a control unit for generating a selection control signal and a digital data control signal, a voltage switching module including a voltage switching module for receiving a first test voltage, a second testing end for receiving a second test voltage, and a plurality of switches, which is utilized for respectively arranging each switch to connect to the first testing end or the second testing end to output the corresponding switching selection signal, and a digital-to-analog converter for selecting an output testing voltage signal from the plurality of switching selection signals according to the digital data control signal.11-01-2012
20120274492METHOD FOR IMPROVING THE PERFORMANCE OF THE SUMMING-NODE SAMPLING CALIBRATION ALGORITHM - An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.11-01-2012
20130154861TESTING APPARATUS AND METHOD FOR TESTING ANALOG-TO-DIGITAL CONVERTER - The invention provides a testing apparatus. In one embodiment, the testing apparatus receives a plurality of bit signals output by an analog-to-digital converter, and comprises a plurality of frequency counters and a comparison module. The frequency counters respectively calculate a plurality of transition frequencies of the values of the bit signals. The comparison module respectively compares the transition frequencies with a plurality of ideal transition frequencies to obtain a plurality of error frequencies. The performance analysis module estimates a performance value of the analog-to-digital converter according to the error frequencies.06-20-2013
20110285564METHOD OF GAIN CALIBRATION OF AN ADC STAGE AND AN ADC STAGE - A method of gain calibration of an ADC stage is disclosed. The method comprises receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The method is characterised in that the calibration signal may take any one of three values. In a preferred embodiment, the calibration is constrained to one of only two of these three values, when the input signal is in an outermost sub-range. An ADC stage adapted to operate according to the method is also disclosed.11-24-2011
20130120174CORRELATION-BASED BACKGROUND CALIBRATION FOR REDUCING INTER-STAGE GAIN ERROR AND NON-LINEARITY IN PIPELINED ANALOG-TO-DIGITAL CONVERTERS - A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.05-16-2013
20110309961A/D CONVERSION CIRCUIT AND A/D CONVERSION METHOD - An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first and second test voltages.12-22-2011
20120293349SIGNAL PROCESSING SYSTEM AND SELF-CALIBRATION DIGITAL-TO-ANALOG CONVERTING METHOD THEREOF - A signal processing system including a DAC, a comparing unit, and a control unit is provided. The DAC receives a digital input and generates an output voltage. The comparing unit receives the output voltage and compares the output voltage with a reference voltage to output an output value. The control unit receives the output value and accordingly generates the digital input in a manner of value mapping through firmware or software to calibrate the DAC. Furthermore, a self-calibration digital-to-analog converting method is also provided.11-22-2012
20130201042METHOD FOR CONFIGURING ANALOG-TO-DIGITAL CONVERTER KEYS AND NON-TRANSITORY MACHINE READABLE MEDIUM STORING PROGRAM CODE EXECUTED FOR PERFORMING SUCH METHOD - A method for configuring a plurality of analog-to-digital converter (ADC) keys includes: utilizing a processor for determining a plurality of divided-voltages respectively corresponding to the Keys according to a plurality of voltage variation ranges respectively corresponding to the Keys; and calculating a plurality of resistive values of a voltage dividing model according to at least the divided-voltages, wherein the voltage dividing model has a plurality of voltage dividing configurations respectively corresponding to the keys.08-08-2013
20120062401ON-DIE DIGITAL-TO-ANALOG CONVERSION TESTING - In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit 370 can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.03-15-2012
20120086590METHOD FOR CALBRATING A PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.04-12-2012
20130207818METHODS AND APPARATUS FOR CALIBRATING PIPELINE ANALOG-TO-DIGITAL CONVERTERS HAVING MULTIPLE CHANNELS - Methods and apparatus are provided for calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.08-15-2013

Patent applications in class CONVERTER CALIBRATION OR TESTING

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