Class / Patent application number | Description | Number of patent applications / Date published |
341126000 |
ANALOG TO OR FROM DIGITAL CONVERSION
| 1790 |
341050000 |
DIGITAL CODE TO DIGITAL CODE CONVERTERS
| 907 |
341020000 |
BODILY ACTUATED CODE GENERATOR
| 643 |
341118000 |
CONVERTER COMPENSATION
| 258 |
341120000 |
CONVERTER CALIBRATION OR TESTING
| 240 |
341110000 |
ANALOG TO DIGITAL CONVERSION FOLLOWED BY DIGITAL TO ANALOG CONVERSION
| 207 |
341173000 |
CODE GENERATOR OR TRANSMITTER
| 198 |
341122000 |
SAMPLE AND HOLD
| 158 |
341001000 |
DIGITAL PATTERN READING TYPE CONVERTER
| 33 |
341111000 |
PHASE OR TIME OF PHASE CHANGE
| 21 |
341200000 |
QUANTIZER
| 11 |
341109000 |
STOCHASTIC TECHNIQUES | 2 |
20110260897 | Circuit and method for generating the stochastic signal - A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products. | 10-27-2011 |
20130307711 | STOCHASTIC TIME-DIGITAL CONVERTER - A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature. | 11-21-2013 |
341108000 |
REVERSIBLE ANALOG TO DIGITAL CONVERTERS | 2 |
20090219184 | Signal Processor, Control Method, and Wireless Communication Device - There is provided a signal processor with a plurality of antennas connected for transmitting and receiving wireless signals, including a plurality of analog reception processing units, AD converters, DA converters, and analog transmission processing units, wherein each of the analog reception processing units converts the wireless signal received through the antenna into an analog baseband signal and outputs the signal to the AD converter, each of the DA converters converts the digital baseband signal into analog format and outputs the signal, and each of the analog transmission processing units shifts the frequency band of the analog baseband signal output from the DA converter to the high frequency side. The signal processor further includes a transmission switch which switches among the DA converters respectively connected to the analog transmission processing units and a reception switch which switches among the AD converters respectively connected to the analog reception processing units. | 09-03-2009 |
20100164761 | DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC - A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes. | 07-01-2010 |