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With reference oscillator or source

Subclass of:

331 - Oscillators

331001000 - AUTOMATIC FREQUENCY STABILIZATION USING A PHASE OR FREQUENCY SENSING MEANS

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
331025000 Signal or phase comparator 43
331019000 Spectrum reference source 1
20090066423SPREAD SPECTRUM CLOCKING IN FRACTIONAL-N PLL - A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase-frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal. A logic interface circuit combines the directional control output signal from the spread spectrum logic circuitry, the phase step control signal from the spread spectrum logic circuitry, and the phase step control signal from the fractional logic circuitry. This means that when both of the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in the same direction, a single phase step control signal is passed to the phase selector and a further phase step control signal is passed to the phase selector in a subsequent clock period. Further, when the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in opposite directions, no phase step control signal is passed to the phase selector.03-12-2009
331022000 Plural significant heterodyne stages 1
20080252384COST EFFECTIVE LOW NOISE SINGLE LOOP SYNTHESIZER - A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.10-16-2008
Entries
DocumentTitleDate
20100117742Circuit with multiphase oscillator - In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.05-13-2010
20100045388Accuracy on-chip clock generator for multi-clock driven single chip solution - A mixed-signal chip is described. The mixed-signal chip comprises a first portion of analog circuit and second portion of digital circuit, an on-chip precision oscillator residing on the first analog portion, the precision oscillator has a precision frequency; a first on-chip non-precision tunable oscillator from a first clock domain residing on the first analog portion, the first non-precision tunable oscillator has a first adjustable frequency; a noise detector for detecting a first noise in the first clock domain; a frequency adjusting register for storing a first desired frequency value of the first on-chip non-precision tunable oscillator, wherein the first desired frequency value is determined based on the first detected noise; a control circuit for adjusting the adjustable frequency of the first non-precision tunable oscillator to the first desired frequency value by using the precision frequency of the on-chip precision oscillator as a reference.02-25-2010
20100097149Methods, Algorithms, Circuits, and Systems for Determining a Reference Clock Frequency and/or Locking a Loop Oscillator - Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.04-22-2010
20090295490DDS CIRCUIT AND ELECTRONIC DEVICE HAVING THE SAME - A circuit includes a DDS unit deriving a sine wave from a tuning word using a frequency of a reference clock, a first frequency divider dividing the frequency of the reference clock, a second frequency divider dividing a frequency of the sine wave output by the DDS unit, and a mixer mixing the sine wave of a divided frequency with the reference clock of a divided frequency to thus produce the sine wave of a mixed frequency.12-03-2009
20090267697Frequency synthesizer using a phase-locked loop and single side band mixer - A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simultaneously improves control over the frequency resolution, noise floor and operating frequency range.10-29-2009
20100295621FREQUENCY GENERATOR AND METHOD OF FREQUENCY GENERATION WITH MULTIPLE SAMPLING PHASE DETECTORS - A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.11-25-2010
20090002080FREQUENCY DIVIDER AND PHASE LOCKED LOOP USING THE SAME - The invention relates to a frequency divider operated digitally and capable of satisfying the Zigbee standard, and a phase locked loop system using the same. The frequency divider includes a plurality of latches in a ring structure with an output of a latter end latch is connected to an input of a former end latch. The frequency divider also includes an input end connected in common to clock ends of the latches, receiving a signal to be divided, and a plurality of output ends connected to the output ends of the latches, outputting divided signals of different phases. The phase locked loop system of the invention has a dividing means dividing an output frequency by 1/P and 1/P+0.5 using the frequency divider, thereby generating the Zigbee channel frequencies at a 5 MHz spacing.01-01-2009
20090085675METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH UNDERSAMPLED FEEDBACK - Aspects of a method and system for signal generation via a PLL with undersampled feedback are provided. In this regard, the output of a VCO may clock a DDFS to generate a sampling frequency, and the output of the VCO may be undersampled at the sampling frequency to generate a feedback signal for controlling the VCO. Additionally, a control word for controlling the DDFS may be generated, and may be based on a phase difference between the feedback signal and a reference signal. The sampling frequency may be determined such that an aliasing product of the undersampling occurs at a frequency of the reference signal. Also, the feedback signal may be filtered to select a desired aliasing product from a plurality of aliasing products. The output of the VCO may be frequency divided before clocking the DDFS, and a divisor of the division may be programmatically controlled.04-02-2009
20090085676Oscillator - An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit.04-02-2009
20120268215CIRCUIT ARRANGEMENT FOR GENERATION OF RADIO FREQUENCY OUTPUT SIGNALS WHICH FORM A BROADBAND FREQUENCY RAMP - A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.10-25-2012
20110169577SYSTEM AND METHOD FOR BUILT IN SELF TEST FOR TIMING MODULE HOLDOVER - Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator. The method further includes testing the selected mathematical model using a sampled version of the correction signal such that the selected mathematical model can be used without the need for a testing duration that is in addition to a period of time used for the training.07-14-2011
20120293269INTEGRATED CIRCUIT FREQUENCY GENERATOR - An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.11-22-2012
20080278246MEMORY CONTROLLER - A memory controller includes a ring oscillator to generate and to output at least one oscillation clock, an oscillation counter to count the output oscillation clocks, a sampler to receive the reference clock so as to sample a number of the counted oscillation clocks during a period of the reference clock, and a phase value output unit to output the sampled number of oscillation clocks as a phase value of the reference clock. Thereby, the memory controller can detect the phase value using only two periods of the reference clock, and reduce the initial operation time of a system.11-13-2008
20080290954Fractional-N phase locked loop - An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor.11-27-2008
20080258823SELF-COMPENSATING VOLTAGE-CONTROLLED OSCILLATOR - In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having including a switched capacitor circuit configured to control a signal delay through the differential inverter stage responsive to a control circuit, whereby an output frequency for the VCO is inherently compensated against changes in semiconductor process variations and thermal variations.10-23-2008
20090184771Systems and Methods for Reducing Flicker Noise in an Oscillator - Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In addition, the circuits include a flicker noise reducing switch that is operable to selectively incorporate the capacitance such that an output of the circuit operates at a frequency based on a combination of the inductance and the capacitance.07-23-2009
20090085674METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DIGITAL PHASE DETECTION - Aspects of a method and system for signal generation via a PLL with a digital feedback path are provided. In this regard, an output of a VCO may clock an accumulator to generate a digital feedback signal for phase comparison with a digital reference signal, wherein a value of a digital control word is added to a value stored in said accumulator on each cycle of said VCO output. The phase comparison may be performed by multiplying the feedback signal and the reference signal. Accordingly, a control voltage of the VCO may be determined based on a product of the multiplication. The value of the control word may be programmatically controlled and may be determined based on a frequency of the VCO output and/or of the reference signal. In this regard, the value of the control word may be retrieved from a look-up table.04-02-2009
20110140789ON-THE-FLY FREQUENCY SWITCHING WHILE MAINTAINING PHASE AND FREQUENCY LOCK - A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock.06-16-2011
20090085673METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DDFS FEEDBACK PATH - Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.04-02-2009
20090243731Apparatus With Clock Generation Function, Method For Setting Reference Frequency, And Method For Adjusting Reference Frequency - An apparatus includes an oscillator, a memory for storing data of a first frequency and of a first voltage, a first controller for causing the oscillator to generate a clock having a required frequency by applying a voltage on the basis of the data of the first frequency and of the first voltage, a second controller for causing the oscillator to generate a clock having a second frequency by applying a second voltage at predetermined timing, an output section for outputting data of the clock of the second frequency to a frequency counter, a writing section for updating the data of the first voltage to data of the second voltage and the data of the first frequency to data of the second frequency when a difference between the second frequency and a third frequency is within a predetermine range.10-01-2009
20100253437METHOD AND SYSTEM FOR USING A MEMS STRUCTURE AS A TIMING SOURCE - A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit.10-07-2010
20090072913Method and system of jitter compensation - The present invention relates to sigma-delta modulators, ΣΔ modulators, and phase locked loops. Especially, it relates to jitter compensation in ΣΔ-controlled fractional-N frequency synthesizers. Jitter compensation is introduced by means of a variable delay line.03-19-2009
20110241784Self-Calibrating Relaxation Oscillator Based Clock Source - A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.10-06-2011
20110084768Dual reference oscillator phase-lock loop - A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.04-14-2011
20110241785Reference signal oscillator - A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages.10-06-2011
20120200361SYSTEM AND METHOD FOR REDUCING HOLDOVER DURATION - A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.08-09-2012
20120200362METHOD AND SYSTEM FOR USING A MEMS STRUCTURE AS A TIMING SOURCE - A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit.08-09-2012
20100321118SYSTEM AND METHOD FOR SELECTING OPTIMUM LOCAL OSCILLATOR DISCIPLINE SOURCE - A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.12-23-2010
20110163817RESONATOR AND OSCILLATOR USING SAME - There is provided with a resonator which can correct the resonance frequency of a vibrator in a wide range and with a high accuracy and also provided with an oscillator using the resonator. In the resonator configured by the vibrator 07-07-2011
20120062326Self-Calibrating Relaxation Oscillator Based Clock Cycle - A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.03-15-2012
20100117743Circuit with noise shaper - In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.05-13-2010
20100214029Integrated circuit frequency generator - An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.08-26-2010
20110148531OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.06-23-2011
20110148530Oscillator with capacitance array - An oscillator is provided which comprises an array of capacitances. At least some capacitances in the array have different capacitance values.06-23-2011
20110156820METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL - A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.06-30-2011
20120056682SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OSCILLATION FREQUENCY CALIBRATION METHOD - A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.03-08-2012
20100214028OSCILLATOR CONTROL APPARATUS - An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase information, to output the oscillator adjusting signal.08-26-2010
20110181366OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.07-28-2011
20120133443SYSTEM AND METHOD FOR SELECTING OPTIMUM LOCAL OSCILLATOR DISCIPLINE SOURCE - A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.05-31-2012
20090243732SDOC with FPHA & FPXC: System Design On Chip with Field Programmable Hybrid Array of FPAA, FPGA, FPLA, FPMA, FPRA, FPTA and Frequency Programmable Xtaless ClockChip with Trimless/Trimfree Self-Adaptive Bandgap Reference Xtaless ClockChip - The Field Programmable Hybrid Array (FPHA) and Frequency Programmable Xtaless Clock (FPXC) are for high-speed and high frequency System-Design-On-Chip(SDOC). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The (10-01-2009
20100052797Direct digital synthesizer for reference frequency generation - A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency f03-04-2010
20100231306POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY - A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.09-16-2010
20130169368Method and Apparatus of a Resonant Oscillator Separately Driving Two Independent Functions - Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.07-04-2013
20100315172Spread spectrum clock generator and semiconductor device - A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator.12-16-2010
20080315961Quality of Phase Lock and Loss of Lock Detector - A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison. The window threshold may be a function of apriori knowledge of at least one loop variable, wherein the window threshold is set based on a predetermined loop variable. An alarm circuit may receive the fourth signal and provide an alarm.12-25-2008

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