Class / Patent application number | Description | Number of patent applications / Date published |
331016000 | Tuning compensation | 69 |
20080218274 | PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET - A control circuit includes a phase frequency detector that receives a reference phase Φ | 09-11-2008 |
20080218275 | Systems and arrangements for operating a phase locked loop - Systems, methods and media for a fast locking phase locked loop (FLPLL) are disclosed. A FLPLL apparatus can include a voltage controlled oscillator (VCO) coupled to a phase frequency detector and can also include a frequency divider as part of a feedback loop. The VCO can accept a pull up voltage and a control signal from the phase frequency detector and provide an output clock signal to circuits that need synchronization. Such a configuration can greatly reduce the time the PLL requires to go from a dormant state to a fully operational state. During this start up mode, a frequency detection module can be utilized to detect an output frequency of the voltage controlled oscillator and when the VCO output frequency is not as high as a reference frequency, the frequency detection module can disabled the feedback loop during this start-up mode. | 09-11-2008 |
20080265999 | RADIATION SOURCE - A source of radiation comprises a first low frequency oscillator | 10-30-2008 |
20080278243 | Edge alignment for frequency synthesizers - A frequency synthesizer ( | 11-13-2008 |
20080278244 | Frequency calibration for frequency synthesizers - A calibration circuit ( | 11-13-2008 |
20080284526 | TUNING CIRCUIT AND METHOD - A tuning circuit and a method for setting its tuning voltage. The tuning circuit has a phase frequency detector coupled to a loop filter which is coupled to a voltage controlled oscillator. An output terminal of the voltage controlled oscillator is coupled to an input terminal of the phase frequency detector to form a feedback loop. A state machine is coupled between the phase frequency detector and the voltage controlled oscillator. A switch is coupled between an output terminal of the state machine and the input terminal to the loop filter or between the output terminal of the state machine and the input terminal of the voltage controlled oscillator. Alternatively, a comparator is coupled between an input terminal of the state machine and the output terminal to the loop filter or between the input terminal of the state machine and the output terminal of the phase frequency detector. | 11-20-2008 |
20090015338 | DIVIDERLESS PLL ARCHITECTURE - A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors. | 01-15-2009 |
20090072911 | SIGNAL GENERATING APPARATUS AND METHOD THEREOF - A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller. | 03-19-2009 |
20090072912 | OSCILLATOR SIGNAL GENERATION WITH SPUR MITIGATION IN A WIRELESS COMMUNICATION DEVICE - Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated. | 03-19-2009 |
20090091396 | METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP - A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance. | 04-09-2009 |
20090096534 | VOLTAGE CONTROLLED OSCILLATOR CIRCUIT, PHASE-LOCKED LOOP CIRCUIT USING THE VOLTAGE CONTROLLED OSCILLATOR CIRCUIT, AND SEMICONDUCTOR DEVICE PROVIDED WITH THE SAME - A VCO circuit includes: a control portion to which a first voltage is inputted and from which a second voltage corresponding to the first voltage is outputted; a current source portion to which the second voltage is inputted and from which a current corresponding to the second voltage is outputted; and an oscillator circuit to which the current is inputted and from which a signal with a frequency in accordance with the current is outputted. The control portion includes an adjusting circuit which changes the second voltage in conjunction with fluctuation of a power supply voltage. Accordingly, fluctuation of the frequency Fo of an output signal of the VCO circuit can be suppressed even when the power supply voltage of the VCO circuit fluctuates. | 04-16-2009 |
20090121793 | Phase locked loop including a frequency change module - A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur. | 05-14-2009 |
20090128240 | OSCILLATOR, PLL CIRCUIT, RECEIVER AND TRANSMITTER - An oscillator, a PLL circuit, a receiver and a transmitter that allow the circuit scale to be reduced and that are suitable for integration. The electrostatic capacities of variable capacitance circuits | 05-21-2009 |
20090128241 | ANALOGUE SELF-CALIBRATION METHOD AND APPARATUS FOR LOW NOISE, FAST AND WIDE-LOCKING RANGE PHASE LOCKED LOOP - A method of operating a phase lock loop includes generating a control voltage based on both an output signal of a voltage-controlled oscillator and a reference signal. An operating mode is selected from one of a high-gain mode, a zero-gain mode and a low-gain mode based on the control voltage. The phase lock loop is operated in the selected one of the high-gain mode, the zero-gain mode, and the low-gain mode. The control voltage is offset to generate an offset voltage based on the selected operating mode. The output signal is generated based on the offset voltage. | 05-21-2009 |
20090134943 | Voltage Control Oscillator - A voltage control oscillator is provided in which a resistance voltage dividing circuit is formed by a switching element so as to arbitrarily change a gain and a reference value of a control voltage, an IC chip area is reduced, and reduction of a noise of an AFC voltage and improvement of C/N are realized. | 05-28-2009 |
20090146743 | Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction - Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%. | 06-11-2009 |
20090153254 | PHASE LOCKED LOOP CIRCUIT PERFORMING TWO POINT MODULATION AND GAIN CALIBRATION METHOD THEREOF - A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation. | 06-18-2009 |
20090153255 | ALL DIGITAL PHASE LOCK LOOP AND METHOD FOR CONTROLLING PHASE LOCK LOOP - An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word. | 06-18-2009 |
20090189699 | FIXED BANDWIDTH LO-GEN - A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a gain calibration module that compensates for variations in the voltage controlled oscillation (VCO) gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the gain calibration module adjusts the charge pump current to compensate for the VCO gain changes. | 07-30-2009 |
20090189700 | Frequency synthesizer - A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator. The voltage-controlled oscillator supplies the first and second frequency dividers with a signal that oscillates at a frequency corresponding to the voltage input to the oscillator. | 07-30-2009 |
20090201093 | PHASE-LOCKED CIRCUIT EMPLOYING CAPACITANCE MULTIPLICATION - A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages. | 08-13-2009 |
20090219099 | DIGITAL SYNTHESIZER FOR LOW POWER LOCATION RECEIVERS - A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block. | 09-03-2009 |
20090231045 | FREQUENCY-LOCKING DEVICE AND FREQUENCY-LOCKING METHOD THEREOF - A frequency-locking device including a digitally-controlled oscillator (DCO) and a comparing unit is disclosed. The DCO is used for generating an output frequency signal. The comparing unit receives a Keep Alive signal or a start of a frame (SOF) from a universal serial bus (USB) and the output frequency signal, and compares the Keep Alive signal or the start of a frame (SOF) with the output frequency signal to generate a calibration signal. Then, the DCO adjusts the frequency of the output frequency signal according to the calibration signal to meet the USB specification for data communication. | 09-17-2009 |
20090256639 | ALL-DIGITAL PHASE-LOCKED LOOP AND BANDWIDTH ADJUSTING METHOD THEREFORE - An all-digital phase-locked loop is disclosed. The all-digital phase-locked loop includes a digitally controlled oscillator, a phase detector, a loop filter, and a bandwidth modification unit. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal, wherein the oscillator tuning word includes a first tuning word and a second tuning word respectively to adjust the capacitance of a first capacitor set and the capacitance of a second capacitor set. The phase detector measures a phase error between the variable signal and a reference signal. The loop filter receives the phase error to generate an initial tuning word. The bandwidth modification unit receives the initial tuning word to adjust the initial tuning word to generate the tuning word according to the available usage range of the first capacitor set and the second capacitor set. | 10-15-2009 |
20090278613 | Two-point modulation polar transmitter architecture and method for performance enhancement - A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth. | 11-12-2009 |
20090284318 | HIGH SPEED PLL CLOCK MULTIPLIER - The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals. | 11-19-2009 |
20090284319 | PHASE-LOCKED CIRCUIT EMPLOYING CAPACITANCE MULTIPLICATION - A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages. | 11-19-2009 |
20090289724 | FREQUENCY SYNTHESIZER AND METHOD FOR CONTROLLING SAME - A frequency synthesizer includes compensation variable capacitance diodes | 11-26-2009 |
20090302951 | DITHERING A DIGITALLY-CONTROLLED OSCILLATOR OUTPUT IN A PHASE-LOCKED LOOP - A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided. | 12-10-2009 |
20090309664 | Phase Alignment Circuit for a TDC in a DPLL - The present disclosure relates to circuits and methods for accelerating a new frequency lock-in process of a digital phase-locked loop. | 12-17-2009 |
20100073093 | Automatic Frequency Compensation for Pulse Width Modulated RF Level Control - Preferred embodiments of the present invention provide systems and methods that automatically correct the desired on-time of switching elements as the resonant frequency changes, so as to maintain the correct proportional value. | 03-25-2010 |
20100102888 | TIMING RECOVERY FOR PARTIAL-RESPONSE MAXIMUM LIKELIHOOD SEQUENCE DETECTOR - An embodiment of the present invention is a technique for timing recovery. A frequency acquisition loop locks a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock. The frequency acquisition loop generates first and second feedback clocks from the VCO clock. A data lock phase loop generates a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock. The driving signal controls the multi-band VCO in a data phase lock mode. A lock detect controller detects a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock. | 04-29-2010 |
20100117740 | BROADBAND VOLTAGE CONTROLLED OSCILLATOR AND METHOD FOR GENERATING BROADBAND OSCILLATION FREQUENCY - The present invention relates to a broadband voltage controlled oscillator and a method for generating a broadband oscillation frequency; and, more particularly, to a broadband voltage controlled oscillator and a method for generating a broadband oscillation frequency capable of operating over a wide frequency band by including a weighted current cell to select two frequency band modes, generating various levels of total 64 oscillation frequencies by including a variable frequency tank and a capacitor bank, and further facilitating adjustment of the total 64 oscillation frequencies distributed over the wide frequency band by including a control signal generator for generating control signals each of which is applied to the weighted current cell, the variable frequency tank and the capacitor bank by a BDD(Binary Decision Diagram) technique. | 05-13-2010 |
20100134191 | Frequency-Locked Clock Generator - A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator. | 06-03-2010 |
20100271137 | VCO CONTROL AND METHODS THEREFOR - A PLL receives an indicator indicating that it is to operate at a different operating frequency than a current operating frequency. A control word is selected from a set of linear control words based upon the different operating frequency. A capacitance of a variable capacitor of a voltage-controlled oscillator is adjusted based upon the control word. The variable capacitor is monotonic and non-linear relative to the set of linear control words. | 10-28-2010 |
20100277244 | ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME - For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner. | 11-04-2010 |
20110115566 | RECEIVER INCLUDING AN LCD TANK FILTER AND METHOD THEREOF - A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal. | 05-19-2011 |
20110140788 | Dithering Control of Oscillator Frequency to Reduce Cumulative Timing Error in a Clock - A method for correcting time error in an oscillator operated clock according to one aspect of the invention includes at selected times determining at least one of a time error in the clock and a frequency difference between the oscillator and a reference oscillator by detecting a time reference signal. A change in the at least one of the time error and the frequency difference between a first one and a second one of the detecting the time reference signals is determined. A frequency of the oscillator is adjusted so as to substantially cancel a cumulative time error between the second one of the detecting the time reference signal and a selected detecting the time reference signal. | 06-16-2011 |
20110163816 | OSCILLATING CIRCUIT, DC-DC CONVERTER, AND SEMICONDUCTOR DEVICE - The oscillating circuit ( | 07-07-2011 |
20110181365 | Synchronization of a Data Output Signal to An Input Clock - A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2 | 07-28-2011 |
20110221534 | Quality of Phase Lock and Loss of Lock Detector - A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal. | 09-15-2011 |
20110260799 | FREQUENCY SETTING CIRCUIT AND METHOD FOR AN INTEGRATED CIRCUIT - A frequency setting circuit and method for an integrated circuit detect the voltage at a pin of the integrated circuit during a frequency setting period, and determine a frequency setting signal according to the detected voltage to set the frequency of a clock provided by an oscillator in the integrated circuit. After setting the frequency, the frequency setting circuit and method store the frequency setting signal and stop detecting the voltage at the pin. Thus the pin can be used for other functions. | 10-27-2011 |
20120112842 | ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE - A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible. | 05-10-2012 |
20120249249 | OSCILLATING SIGNAL GENERATOR UTILIZED IN PHASE-LOCKED LOOP AND METHOD FOR CONTROLLING THE OSCILLATING SIGNAL GENERATOR - An oscillating signal generator utilized in a phase-locked loop (PLL) includes: an oscillating circuit arranged to generate an oscillating signal according to at least a first control signal; and a control circuit, arranged to adjust the first control signal according to a temperature; and the first control signal is tuned between a first boundary and a second boundary, and when the temperature is closer to a first temperature boundary than a second temperature boundary, and the control circuit is arranged to make the first control signal to be closer to the first boundary than the second boundary such that the oscillating circuit outputs the oscillating signal of a predetermined frequency in a locked mode of the PLL. | 10-04-2012 |
20120262239 | LOW POWER WIDEBAND LO USING TUNED INJECTION LOCKED OSCILLATOR - A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased. | 10-18-2012 |
20130076449 | VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING - Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering. | 03-28-2013 |
20130106522 | OSCILLATOR DEVICE | 05-02-2013 |
20130141173 | METHODS AND APPARATUS FOR TUNING DEVICES HAVING MECHANICAL RESONATORS - Methods and apparatus for tuning devices having mechanical resonators are described. In one implementation, a mechanical resonator and a phase shifter are configured in a feedback loop, so that the phase shifter shifts the phase of the resonator output signal. The amount of phase shift induced by the phase shifter may be variable. In another implementation, an LC tuning subcircuit is coupled to a mechanical resonator. In some implementations, the LC tuning subcircuit has a variable capacitance. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS). | 06-06-2013 |
20130162355 | PHASE-LOCK IN ALL-DIGITAL PHASE-LOCKED LOOPS - This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information. | 06-27-2013 |
20130187719 | PLL SYSTEM AND METHOD FOR CONTROLLING A GAIN OF A VCO CIRCUIT - A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages. | 07-25-2013 |
20130207733 | SELF-RESONANT CIRCUIT - A digitally-controlled oscillator circuit receives a digital value and generates a driving signal for driving an oscillator at a frequency according to the received digital value. A time-to-digital converter circuit receives a detection signal of oscillation of the oscillator, receives the driving signal, and detects a phase difference between the detection signal and the driving signal. A control circuit receives the detected phase difference and controls the frequency of the driving signal generated by the digitally-controlled oscillator circuit, such that the detected phase difference coincides with a predetermined resonant phase difference to resonate the oscillator. | 08-15-2013 |
20130222066 | VOLTAGE-CONTROLLED OSCILLATOR WITH AMPLITUDE AND FREQUENCY INDEPENDENT OF PROCESS VARIATIONS AND TEMPERATURE - In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal. | 08-29-2013 |
20130328632 | CLOCK DISTRIBUTOR AND ELECTRONIC APPARATUS - A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator. | 12-12-2013 |
20140091864 | APPARATUS AND METHODS FOR TUNING A VOLTAGE CONTROLLED OSCILLATOR - Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval. | 04-03-2014 |
20140132359 | CURRENT REUSE VOLTAGE CONTROLLED OSCILLATOR WITH IMPROVED DIFFERENTIAL OUTPUT - A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs. | 05-15-2014 |
20140159821 | OSCILLATION APPARATUS - An oscillation apparatus corrects a setting value for an output frequency based on a detection result of an environmental temperature. The oscillation apparatus includes a first crystal unit, a second crystal unit, an integrated circuit chip, and a container. The first crystal unit includes first excitation electrodes on respective surfaces of a crystal element. The second crystal unit includes second excitation electrodes on respective surfaces of a crystal element. The integrated circuit chip includes a first oscillation circuit, a second oscillation circuit, and a correction unit. The container houses the first crystal unit, the second crystal unit, and the integrated circuit chip. Assuming that distances from a gravity center position of the integrated circuit chip to respective gravity center positions of the first excitation electrodes and the second excitation electrodes in plan view are denoted by D1 and D2, D1/D2 is within a predetermined range close to 1. | 06-12-2014 |
20140191810 | SYSTEMS AND METHODS FOR SYNTHESIZER LOCKING USING ITERATIVE NUMERICAL TECHNIQUES - This disclosure includes systems and methods for frequency synthesis using a voltage-controlled oscillator (VCO) with a programmable array of capacitors. A suitable setting for the capacitor array may be derived through a non-successive iterative numerical technique. In one aspect, the iterative numerical technique may apply Newton's method to an equation relating frequency generated by the VCO and the capacitor setting of the first programmable array of capacitors. In another aspect, a secant method may be applied to determine a capacitor array setting based on previously and currently applied capacitor settings and the corresponding measured frequencies. | 07-10-2014 |
20140197894 | NARROW BAND RECEIVER OR TRANSCEIVER - The present invention relates to a narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver comprises an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop. | 07-17-2014 |
20140266471 | PROGRAMMABLE FREQUENCY DIVIDER FOR LOCAL OSCILLATOR GENERATION - A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal. | 09-18-2014 |
20140292416 | OSCILLATOR - An oscillator configured to obtain a frequency output corresponding to a frequency setting value includes: an oscillation circuit portion that receives the frequency setting value; a setting value output portion that outputs a digital value for designating the frequency setting value; an interpolation circuit portion that performs interpolation for a digital value of lower-order bits out of the digital value output from the setting value output portion; and an adder that adds an output of the interpolation circuit portion and a digital value of higher-order bits out of the digital value output from the setting value output portion, wherein a signal output from the interpolation circuit portion is sequential data having first and second values different from each other, and output counts of the first and second values are determined based on a ratio corresponding to the digital value of the lower-order bits. | 10-02-2014 |
20140340161 | DIGITAL PHASE-LOCKED LOOP DEVICE WITH AUTOMATIC FREQUENCY RANGE SELECTION - A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed. | 11-20-2014 |
20140347137 | ADJUSTING TUNING SEGMENTS IN A DIGITALLY-CONTROLLED OSCILLATOR - A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array. | 11-27-2014 |
20140368281 | MID-BAND PSRR CIRCUIT FOR VOLTAGE CONTROLLED OSCILLATORS IN PHASE LOCK LOOP - A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO. | 12-18-2014 |
20150109060 | PROCESS, VOLTAGE AND TEMPERATURE COMPENSATED OSCILLATOR - A process, voltage, and temperature compensated oscillator, formed on an integrate circuit implemented by a semiconductor process, receives a supply voltage and includes: a variation bias unit provided with a variation bias output terminal and generating a process, voltage, and temperature compensated signal; a controlled oscillating unit provided with a control input terminal and an oscillating output and determining a signal oscillating frequency at the oscillating output terminal according to a signal at the control input terminal; and a tuning unit provided with a tuning input terminal, a compensating input terminal, a control output terminal, and a variable-parameter element, wherein the variable-parameter element includes a parameter and is coupled to the control output terminal, and the tuning unit determines the parameter according to a signal at the variation bias output terminal and a voltage signal or a digital signal received at the tuning input terminal. | 04-23-2015 |
20150130543 | METHOD AND APPARATUS OF SYNCHRONIZING OSCILLATORS - A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled. | 05-14-2015 |
20150381186 | OSCILLATOR CIRCUITS AND METHODS TO COMPENSATE FREQUENCY PULLING - An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency. | 12-31-2015 |
20160065225 | METHOD FOR RE-CENTERING A VCO, INTEGRATED CIRCUIT AND WIRELESS DEVICE - A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop. | 03-03-2016 |
20160072513 | HIGH-RELIABILITY HOLDOVER METHOD AND TOPOLOGIES - System and methods for a clock system disciplined to an external reference. In one embodiment, the clock includes a flywheel oscillator controlled by the external reference and a free running holdover oscillator. The holdover oscillator provides increased accuracy during periods of holdover when the external reference is not available. In a further embodiment, the flywheel oscillator is additionally controlled by a phase-locked loop with the holdover oscillator frequency as input, and a control switch for switching the flywheel oscillator to analog control if the phase-locked loop exhibits a fault. | 03-10-2016 |
20180026646 | MULTIPLE-OUTPUT OSCILLATOR CIRCUITS | 01-25-2018 |