| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 330252000 |
Including differential amplifier
| 700 |
| 330277000 |
Including field effect transistor
| 191 |
| 330278000 |
Including gain control means
| 179 |
| 330251000 |
Including Class D amplifier
| 157 |
| 330296000 |
Including particular biasing arrangement
| 138 |
| 330295000 |
Including plural amplifier channels
| 117 |
| 330291000 |
Including signal feedback means
| 68 |
| 330297000 |
Including particular power supply circuitry
| 65 |
| 330302000 |
Including frequency-responsive means in the signal transmission path
| 52 |
| 330262000 |
Including push-pull amplifier
| 45 |
| 330310000 |
Including plural stages cascaded
| 44 |
| 330288000 |
Including current mirror amplifier
| 35 |
| 330307000 |
Integrated circuits
| 30 |
| 330301000 |
Including balanced to unbalanced circuits and vice versa
| 18 |
| 330298000 |
Including protection means
| 17 |
| 330286000 |
Including distributed parameter-type coupling
| 16 |
| 330289000 |
Including temperature compensation means
| 11 |
| 330308000 |
Including atomic particle or radiant energy impinging on a semiconductor
| 6 |
| 330299000 |
Including combined diverse-type semiconductor device | 4 |
| 20090108942 | Low noise, low power and high bandwidth capacitive feedback trans-impedance amplifier with differential fet input and bipolar emitter follower feedback - A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads. | 04-30-2009 |
| 20130120070 | DUAL STAGE ACTIVE PIXEL DEVICES AND RELATED METHODS - Embodiments of dual stage active pixel devices are described herein. Other examples, implementations, and related methods are also disclosed herein. | 05-16-2013 |
| 20120188021 | Low 1/f noise high-frequency broadband amplifier (DC-12 GHz) - A N-Channel HJ-FET cascode amplifier, with a High Frequency NPN Transistor differential error amplifier, having low 1/f noise, a DC to 12 GHz bandwidth, flat frequency response, excellent transient response, high linearity, and low input and output VSWR over a wide frequency range. | 07-26-2012 |
| 20120154055 | POWER AMPLIFIER - A power amplifier includes a first amplifier unit, a second amplifier unit, and an attenuator. The second amplifier receives a signal from the first amplifier unit and amplifies the signal. The attenuator is provided between the first and second amplifier units. The attenuator has arms, including at least one parallel arm and at least one series arm, and has switches connected to the arms to switch the electrical connection states of the arms with respect to the first and second amplifier units. The at least one parallel arm and the at least one series arm are alternately arranged, in the order named, as viewed in the direction from the first amplifier unit to the second amplifier unit. | 06-21-2012 |
| 330290000 |
Including D.C. feedback bias control for stabilization | 1 |
| 20110181364 | Biasing methods and devices for power amplifiers - Biasing methods and devices for power amplifiers are described. The described methods and devices use the power amplifier output voltage to generate bias voltages. The bias voltages are obtained using rectifiers and voltage dividers. The described biasing methods and devices can be used with class-E power amplifiers. | 07-28-2011 |
| Entries |
| Document | Title | Date |
|---|
| 20100156531 | POWER AMPLIFIER, INTEGRATED CIRCUIT, AND COMMUNICATION APPARATUS - A power amplifier of the present invention includes (i) a bipolar transistor for amplifying a signal supplied via a base terminal, so as to obtain an amplified signal, and outputting the amplified signal via a collector terminal and (ii) an inductor between an emitter terminal of the bipolar transistor and a ground. An inductance between the emitter terminal and the ground is larger than a parasitic inductance between the emitter terminal and the ground between which the inductor is not provided. This allows the bipolar transistor to increase an output power without increasing an emitter area. As a result, the present invention makes it possible to provide a highly efficient high-power power amplifier. | 06-24-2010 |
| 20090219089 | Amplifier arrangement and method - An amplifier arrangement having a transistor arrangement comprising a first transistor ( | 09-03-2009 |
| 20130038390 | ATOMIC LAYER DEPOSITION ENCAPSULATION FOR POWER AMPLIFIERS IN RF CIRCUITS - Power amplifiers and methods of coating a protective film of alumina (Al | 02-14-2013 |
| 20130088295 | Multi-Band Power Amplifier - A power amplifier ( | 04-11-2013 |
| 20090267690 | SIGNAL MODULATION DEVICE AND SIGNAL AMPLIFIER COOPERATIVE THEREWITH - A signal modulation device and a signal amplifier cooperative therewith. The signal modulation device includes a local oscillation signal source, a baseband signal source, a first NMOS transistor, and a second NMOS transistor, wherein the first and second NMOS transistors are coupled with the baseband signal source and form a circuit architecture of a Gilbert-cell based differential pair to be directly switched by a differential baseband signal, and a high-frequency signal from the local oscillation signal source is controlled by the baseband signal so as to generate an amplitude-modulation high-frequency signal at an output end. The single-stage signal power amplifier amplifies the amplitude-modulation signal from the preceding circuit so as to increase the magnitude of signals transmitted and simplify the preceding digital/analog signal conversion circuit in a conventional amplitude-modulation circuit. | 10-29-2009 |
| 20090267689 | HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE - A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts. | 10-29-2009 |
| 20090231034 | Inverse mode SiGe HBT cascode device and fabrication method - Disclosed is a device structure using an inverse-mode cascoded Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) beneficial in applications requiring radiation hardened circuitry. The device comprises a forward-mode common-emitter HBT cascoded with a common-base inverse-mode HBT, sharing a common sub-collector. An exemplary device was measured to have over 20 dB of current gain, and over 30 dB of power gain at 10 GHz, thus demonstrating the use of these circuits for high-frequency circuit applications. In addition, the radiation response and voltage limits were characterized and showed to have negligible performance effects in typical operating conditions. Due to the unique topology, the disclosed device has the benefit of being a more compact cascode design and the additional benefit of providing significantly improved radiation tolerance. | 09-17-2009 |
| 20100182082 | AMPLIFIER CIRCUIT WITH A FIRST AND A SECOND OUTPUT LINE - The present invention relates to an amplifier circuit ( | 07-22-2010 |
| 20080231360 | ARRANGEMENT OF SIGNAL LINE PAIRS AND AMPLIFIERS - An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties. | 09-25-2008 |
| 20110248780 | CASCODE AMPLIFIER WITH INCREASED LINEARITY - An amplifier circuit for current amplification. An input stage is adapted to receive an input signal. At least one current multiplication stage is connected to the input stage. The current multiplication stage is adapted to receive a current signal from the input stage and to produce a multiplied output current signal at an output of the amplifier circuit. The current multiplication stage includes at least two current multiplication circuits connected to each other. Each current multiplication circuit is adapted to produce an output current signal essentially equal to the current signal from the input stage, such that the output current signal at an output of the amplifier circuit includes a sum of the current signals received at each current multiplication circuit. A method of improving linearity in an amplification circuit. | 10-13-2011 |
| 20120161867 | METAMATERIAL POWER AMPLIFIER SYSTEMS - Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity. | 06-28-2012 |
| 20120229210 | OVERLAY CLASS F CHOKE - Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification. | 09-13-2012 |
| 20120139630 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - On a surface of a compound semiconductor layer including inner wall surfaces of an electrode trench, an etching residue | 06-07-2012 |
