Class / Patent application number | Description | Number of patent applications / Date published |
329311000 | PULSE OR INTERRUPTED CONTINUOUS WAVE DEMODULATOR | 12 |
20080252367 | Demodulator with Multiple Operating Modes for Amplitude Shift Keyed Signals - A demodulator for demodulating an amplified shift keyed (ASK) signal includes an envelope detector generating an envelope signal, a low-pass filter generating a filtered envelope signal, a switch coupled to disengage the low-pass filter in response to a first control signal, a comparator with hysteresis comparing the envelope signal and the filtered envelope signal. In operation, the switch is open or close in response to the first control signal to cause the demodulator to operate in one of multiple operation modes. In one operation mode, the demodulator uses a small capacitor to form a low-pass filter having a cut-off frequency equal to or greater than the bit-rate of the ASK signal and the demodulator receives an ASK signal having any coding pattern, including ASK signals having unequal number of 1's and 0's. | 10-16-2008 |
20090174471 | SAMPLES OF BANDLIMITED SIGNALS RECOVERY SYSTEM AND METHOD - A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples. | 07-09-2009 |
20090189688 | HIGH DYNAMIC RANGE ASK DEMODULATOR FOR USE IN AN RFID TRANSPONDER - An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna fieldstrength modulation into an ASK limiter current modulation by limiting the antenna voltage to a fixed value and thereby causing the limiter current to be substantially proportional to the ASK antenna field strength, and a current discriminator circuit that discriminates the ASK limiter current modulation. By converting the fieldstrength modulation into a proportional limiter current and discriminating that limiter current, a linear relationship and a stable demodulator sensitivity are achieved. The current discrimination can be made accurately under low-voltage conditions. | 07-30-2009 |
20100315160 | ADAPTIVE DEMODULATOR - An adaptive demodulator for a contactless device, including a rectifier configured to rectify a voltage which is dependent on a signal received by the contactless device, and a voltage regulator coupled to the rectifier and configured to adjust the voltage to be within a voltage window. | 12-16-2010 |
329312000 | Pulse width demodulator | 6 |
20080224765 | Control interface and protocol - In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information. | 09-18-2008 |
20130187708 | Wide Input Bit-Rate, Power Efficient PWM Decoder - A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter. | 07-25-2013 |
20140292402 | SYNCLESS UNIT INTERVAL VARIATION TOLERANT PWM RECEIVER CIRCUIT, SYSTEM AND METHOD - A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal. | 10-02-2014 |
20140361829 | SYSTEM AND METHOD FOR PULSE WIDTH MODULATION - A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle. | 12-11-2014 |
20150303910 | PULSE-WIDTH MODULATION DATA DECODER - Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient. | 10-22-2015 |
20160134269 | I/O MODULE - An input/output (I/O) module is configured to connect a controller and a field device. The I/O module includes a PWM (pulse width modulation) demodulator configured to demodulate a PWM signal that is input from the controller, a current source configured to output a current based on an output signal of the PWM demodulator to the field device, a resistance connected in line with the current source, and a feedback circuit configured to feed back an output current of the current source to the PWM demodulator via the controller. | 05-12-2016 |
329313000 | Pulse position, frequency, phase or spacing demodulator | 2 |
20090251208 | LOW POWER SLICER-BASED DEMODULATOR FOR PPM - An apparatus and method for communications is disclosed. The apparatus includes a slicer configured to generate samples of a signal carrying information, and a demodulator having a digital integrator configured to integrate the samples, the demodulator being further configured to recover from the integrated samples data representative of the information carried by the signal. | 10-08-2009 |
20100295608 | DEMODULATION METHOD UTILIZING DELAYED-SELF-SAMPLING TECHNIQUE - Rather than using an external sampling clock to perform time-to-digital conversion function, input signal is self-sampled by its own delayed signals. A demodulation method utilizing delayed-self-sampling technique, comprising steps of: obtaining a signal processed by a limiting amplifier as the only input signal required for demodulation; transferring the limiting amplified signal via two paths, by one of which the limiting amplified signal is directly sent to an input end of a delayed-self-sampler, and by the other of which the limiting amplified signal is sent to a delay line for generating and outputting time delayed signals; sampling the limiting amplified signal by time delayed signals from the delay line with delayed-self-sampler to generate a group of sampled data; and converting the group of sampled data by a thermometer-to-binary converter into a group of binary codes, which is input into data decision circuitry to be processed into recovered base-band data. The advantage of demodulation method utilizing delayed-self-sampling technique is the delayed-self-sampler can avoid edge synchronization problem and reduce power consumption. | 11-25-2010 |