Class / Patent application number | Description | Number of patent applications / Date published |
327581000 | Field-effect transistor | 69 |
20080258807 | Basic semiconductor electronic circuit with reduced sensitivity to process variations - A basic electronic circuit generates a magnitude. The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit comprises at least two circuit parts suitable for supplying respective fractions of the magnitude and the at least two circuit parts have different structural characteristics. | 10-23-2008 |
20080309401 | Random Number Generating Circuit - Provided is a random number generating circuit having a simple circuit structure, for generating a physical random number based on a noise. The random number generating circuit includes a reference voltage section, an inverting amplifier section having a threshold voltage equal to a reference voltage level, and a semiconductor switch provided between an output terminal of the reference voltage section and an input terminal of the inverting amplifier section. A thermal noise produced from the reference voltage section is held by the semiconductor switch and a capacitor and amplified by the inverting amplifier section to generate the physical random number. | 12-18-2008 |
20090033410 | POWER ELECTRONICS DEVICES WITH INTEGRATED CONTROL CIRCUITRY - A power switch apparatus includes a substrate; a semiconductor die mounted on the substrate and including power electronics circuitry for a high power, alternating current motor application; gate drive circuitry mounted on the substrate and electrically coupled to the power electronics circuitry on the semiconductor die; and control circuitry mounted on the substrate and electrically coupled to the gate drive circuitry. | 02-05-2009 |
20090085656 | Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit - A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: | 04-02-2009 |
20090115505 | SEMICONDUCTOR DEVICE WITH CONTROLLABLE DECOUPLING CAPACITOR - Semiconductor device with a controllable decoupling capacitor includes a decoupling capacitor connected between a power voltage terminal and a ground terminal and a switching unit configured to enable/disable the decoupling capacitor in response to a control signal. According to another aspect, a semiconductor device with a controllable decoupling capacitor includes multiple circuits, decoupling capacitors being connected in parallel to each of the circuits and switching units being configured to enable/disable the decoupling capacitors in response to control signals. | 05-07-2009 |
20090134939 | Transistor device and method - A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages. | 05-28-2009 |
20090140801 | Locally gated graphene nanostructures and methods of making and using - A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described. | 06-04-2009 |
20090160545 | DUAL VOLTAGE SWITCHING CIRCUIT - A dual voltage switching circuit includes an input terminal receiving a control signal, an output terminal, three transistors, and a Zener diode. The gate of the first transistor is connected to the input terminal. The drain of the first transistor is connected to a standby power and the gate of the second transistor. The drain of the second transistor is connected to a first system power and the gate of the third transistor. The sources of the first transistor and the second transistor are grounded. The drain of the third transistor is connected to the input terminal. The source of the third transistor is connected to a second system power. The anode of the Zener diode is connected to the standby power. The cathode of the Zener diode is connected to the output terminal. The output terminal selectively outputs the standby power or the second system power. | 06-25-2009 |
20090206924 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 08-20-2009 |
20090243715 | Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit - A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes:
| 10-01-2009 |
20090284311 | RESISTOR CIRCUIT - Operations as a variable resistor are favorably realized even when a drain-source voltage of a variable MOS resistor and that of a reference MOS resistor are not the same. | 11-19-2009 |
20100013552 | MOSFET Switch with Embedded Electrostatic Charge - A vertical device structure includes a volume of semiconductor material, laterally adjoining a trench having insulating material on sidewalls thereof. A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconducting material. Some portions of the insulating material contain fixed electrostatic charge in a density high enough to invert a second portion of the semiconductor material when no voltage is applied. The inverted portions can be used as induced source or drain extensions, to assure that parasitic are reduced without increasing on-resistance. | 01-21-2010 |
20100026384 | Method and Circuit for Protecting a MOSFET - The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed. | 02-04-2010 |
20100073082 | RECTIFIER - Provided is a highly efficient rectifier which can readily replace a two-terminal diode and whose conduction loss is reduced from that of the two-terminal diode. | 03-25-2010 |
20100090759 | Quantum interference transistors and methods of manufacturing and operating the same - A quantum interference transistor may include a source; a drain; N channels (N≧2), between the source and the drain, and having N−1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed. | 04-15-2010 |
20100097135 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel transistor includes source diffusion ( | 04-22-2010 |
20100127769 | ACTIVE FILTER HAVING A MULTILEVEL TOPOLOGY - A cost-effective device for influencing the transmission of electrical energy of an alternating voltage line with a plurality of phases has phase modules, which each have an alternating voltage terminal for connecting to a phase of the alternating voltage line and two connecting terminals. A phase module branch extends between each connecting terminal and each alternating voltage terminal. The phase module branch is formed of a series connection of sub-modules, each having a power semiconductor circuit and an energy accumulator connected in parallel to the power semiconductor circuit. The connecting terminals are connected to one another. The power semiconductor circuit is equipped with power semiconductors that can be switched off and are connected to each other in a half bridge. | 05-27-2010 |
20100156526 | SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION - A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided. | 06-24-2010 |
20100182078 | METHODS AND APPARATUS FOR REDUCING COUPLING IN A MOS DEVICE - Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances. | 07-22-2010 |
20100201439 | III-Nitride Devices and Circuits - A III-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate. The gate-connected grounded field plate device can minimize the Miller capacitance effect. The transistor can be formed as a high voltage depletion mode transistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor. | 08-12-2010 |
20100201440 | SOI RADIO FREQUENCY SWITCH WITH REDUCED SIGNAL DISTORTION - A doped semiconductor region having a same conductivity type as a bottom semiconductor layer is formed underneath a buried insulator layer in a bottom semiconductor layer of a semiconductor-on-insulator (SOI) substrate. At least one conductive via structure is formed, which extends from a interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to the doped semiconductor region. The shallow trench isolation structure laterally abuts at least one field effect transistor that functions as a radio frequency (RF) switch. During operation, the doped semiconductor region is biased at a voltage that keeps an induced charge layer within the bottom semiconductor layer in a depletion mode and avoids an accumulation mode. Elimination of electrical charges in an accumulation mode during half of each frequency cycle reduces harmonic generation and signal distortion in the RF switch. | 08-12-2010 |
20100207690 | METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE - A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented. | 08-19-2010 |
20100219885 | Broadband low noise amplifier - Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits. | 09-02-2010 |
20100219886 | Broadband low noise amplifier - Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits. | 09-02-2010 |
20100244947 | METHOD OF FORMING A SENSING CIRCUIT AND STRUCTURE THEREFOR - In one embodiment, a sensing circuit includes a sense transistor and a compensation circuit to improve the accuracy of a sensing signal formed by the sensing circuit. | 09-30-2010 |
20100259321 | FIELD EFFECT TRANSISTOR HAVING A PLURALITY OF FIELD PLATES - Embodiments include but are not limited to apparatuses and systems including a field-effect transistor switch. A field-effect transistor switch may include a first field plate coupled with a gate electrode, the first field plate disposed substantially equidistant from a source electrode and a drain electrode. The field-effect transistor switch may also include a second field plate proximately disposed to the first field plate and disposed substantially equidistant from the source electrode and the drain electrode. The first and second field plates may be configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode. | 10-14-2010 |
20100277233 | Gallium nitride traveling wave structures - A traveling wave device employs an active Gallium Nitride FET. The Gallium Nitride FET has a plurality of gate feeding fingers connecting to an input gate transmission line. The FET has a drain electrode connected to an output drain transmission line with the source electrode connected to a point of reference potential. The input and output transmission lines are terminated with terminating impedances which are not matched to the gate and drain transmission lines. The use of Gallium Nitride enables the terminating impedance to be at much higher levels than in the prior art. The use of Gallium Nitride permits multiple devices to be employed, thus resulting in higher gain amplifiers with higher voltage operation and higher frequency operation. A cascode traveling wave amplifier employing GaN FETs is also described having high gain and bandwidth. | 11-04-2010 |
20100283537 | TANTALUM ALUMINUM OXYNITRIDE HIGH-K DIELECTRIC - Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 11-11-2010 |
20100301930 | REDUCING DEVICE PARASITICS IN SWITCHED CIRCUITS - A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise. | 12-02-2010 |
20100308906 | Impedance Transformation With Transistor Circuits - The present disclosure relates to impedance transformation with transistor circuits. | 12-09-2010 |
20110018625 | ELECTRONIC CIRCUIT AND ELECTRONIC CIRCUIT ARRANGEMENT - In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit. | 01-27-2011 |
20110057724 | High- and Low-Power Power Supply with Standby Power Saving Features - A power supply for providing power to an electrical device is described. The power supply converts a received input signal to a first electrical having a first voltage level at a first power converter. The power supply additionally converts the first electrical signal to a second electrical signal having a second voltage level at a second power converter, to provide the second electrical signal having the second voltage level to an output port. The power supply includes a circuit to selectively bypass the second power converter and provide the first electrical signal having the first voltage level from the first power converter to the output port. The first power converter may include one or more switches that may be disabled to disconnect power from the first power converter for additional standby power saving features. | 03-10-2011 |
20110057725 | SEMICONDUCTOR DEVICE - A semiconductor device such as an RFID, which can easily generate a given stable potential, is provided. Circuits included in a semiconductor device are categorized depending on whether a given stable power source potential is necessary. A power source potential generated from a wireless signal received by an antenna with the use of the antenna and a rectifier circuit is supplied to a circuit which needs a given stable power source potential through a regulator. On the other hand, a power source potential generated by the rectifier circuit is supplied to a circuit other than the circuit which needs the arbitrary power source potential. Thus, a semiconductor device including a regulator circuit easily designed with a smaller layout can be provided, and the semiconductor device can easily generate a given stable power source potential. | 03-10-2011 |
20110063024 | METHOD AND SYSTEM FOR BANDWIDTH ENHANCEMENT USING HYBRID INDUCTORS - A method and system for bandwidth enhancement using hybrid inductors are disclosed and may include providing an electrical impedance that increases with frequency via hybrid inductors comprising a transistor, a capacitor, an inductor, and a resistor. A first terminal of the hybrid inductors may comprise a first terminal of the transistor. A second terminal of the transistor may be coupled to a first terminal of the resistor and a first terminal of the capacitor. A second terminal of the resistor may comprise a second terminal of the hybrid inductors. A third terminal of the transistor may be coupled to a first terminal of an inductor, and a second terminal of the inductor may be coupled to a second terminal of the capacitor. The hybrid inductors may be configured by varying transconductance, resistance, and/or capacitance and may be utilized as an amplifier load. | 03-17-2011 |
20110063025 | High Breakdown Voltage Double-Gate Semiconductor Device - A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated. | 03-17-2011 |
20110080213 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source. | 04-07-2011 |
20110090006 | ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE - An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×10 | 04-21-2011 |
20110121895 | CONTROL AND READOUT OF ELECTRON OR HOLE SPIN - This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the ESR line substrate beneath it. A fourth gate in close proximity to a single dopant donor gate atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate. In use either the third or fourth gate also serve as an Electron Spin Resonance (ESR) line to control the spin of the single electron or hole of the dopant atom. In a further aspect it concerns a method for using the device. | 05-26-2011 |
20110148517 | Shift Register and Driving Method Thereof - A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion, of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided | 06-23-2011 |
20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 08-25-2011 |
20110227640 | POWER SUPPLY DEVICE - In a power supplying system that includes a plurality of power supply devices, each of which has a backflow prevention circuit at an output side thereof, and supplies power to a load device, a backflow prevention circuit is configured by using a hetero-junction FET (HEMT). A normally-on type GaNFET is used for the hetero-junction FET (HEMT), so that the backflow prevention circuit is further simplified. | 09-22-2011 |
20110234311 | CURRENT DETECTION CIRCUIT AND INFORMATION TERMINAL - According to one embodiment, a current detection circuit is provided with: a NMOS transistor, whose control signal is given to a gate electrode, whose source electrode is connected to a ground line, and whose drain electrode is connected to an input/output terminal; a first PMOS transistor, in which the control signal is given to a gate electrode, and whose drain electrode is connected to the input/output terminal and the drain electrode of the NMOS transistor; and a second PMOS transistor, whose drain electrode is connected to the source electrode of the first PMOS transistor, and a first supply voltage is given to a source electrode. A detection section detects whether or not a current has changed at the input/output terminal from a change in current flowing through the second PMOS transistor. | 09-29-2011 |
20110248778 | DEVICES COMPRISING COLOSSAL MAGNETOCAPACITIVE MATERIALS AND RELATED METHODS - Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor. | 10-13-2011 |
20110291752 | Dendrite resistant input bias network for metal oxide semiconductor field effect transistor (MOSFET) devices - A circuit includes a high impedance direct current (DC) gate having a DC impedance higher than a maximum impedance DC above which dendrite growth occurs in the circuit, and a low impedance radio frequency (RF) gate having an RF impedance lower than a minimum impedance RF needed to ensure RF stability for the circuit for an application. | 12-01-2011 |
20110298534 | INTEGRATED CIRCUIT DEVICE - The channel number detecting circuit | 12-08-2011 |
20110304389 | Drive Circuit With a Transmission Circuit for Capacitively Transmitting a Signal and Associated Method - A drive circuit with a circuit for transmitting a signal from a primary side having a first ground to a secondary side having a second ground. The transformer has capacitive coupling between the primary and secondary sides. The transformer has an ON transmission branch and an OFF transmission branch, which each have a first partial branch and a second partial branch. Capacitive coupling between the primary and secondary sides is effected in each partial branch by high-voltage capacitors. In the inventive method, in each transmission branch, the signal generates a current flow through a first HV capacitor of a first partial branch and an inverse current flow through a second HV capacitor of a second partial branch. This respective current flow is detected on the secondary side and is supplied to an evaluation circuit common to the two partial branches and reconstructs the primary-side input signal on the secondary side. | 12-15-2011 |
20120019315 | BIO MATERIAL RECEIVING DEVICE AND METHODS OF MANUFACTURING AND OPERATING THE SAME - A bio material receiving device includes a thin film transistor (“TFT”) including a drain electrode, and a nano well accommodating a bio material. The drain electrode includes the nano well. The TFT may be a bottom gate TFT or a top gate TFT. A nano well array may include a plurality of bio material receiving devices. In a method of operating the bio material receiving device, each of the bio material receiving devices may be individually selected in the nano well array. When the bio material is accommodated in the selected bio material receiving device, a voltage is applied so that another bio material is not accommodated. | 01-26-2012 |
20120019316 | APPARATUS FOR DRIVING A RESONANT CIRCUIT - An apparatus for driving a resonant circuit is disclosed. The apparatus comprises: a first drive circuit, the first drive circuit arranged to provide a drive current to said resonant circuit; and a controller coupled to said first drive circuit, the first drive circuit further comprising: a first input adapted to receive a current from a power supply; a switch; a second input adapted to receive from said controller a signal to control said switch; an output coupled to said resonant circuit; a first inductor, which acts to set the drive current through said resonant circuit when the switch is closed; and a first diode coupled across said first inductor, said first diode arranged to enable current to continue to flow in the first inductor when the switch is open, wherein the controller is adapted to receive from a sensor a signal derived from the current flowing in said resonant circuit, wherein said sensor is coupled to said controller, and said controller is configured to close said switch to enable the drive current to flow through said resonant circuit when said signal derived from said sensor satisfies a first condition and said controller is further configured to open said switch to cause the drive current to stop flowing through the resonant circuit when said signal derived from said sensor satisfies a second condition. In a preferred embodiment, the apparatus also comprises a forward diode in series with the switch, so as to allow the resonance to be driven to a greater amplitude than otherwise possible. | 01-26-2012 |
20120086506 | APPARATUS FOR COMPENSATING FOR PROCESS VARIATION OF RESISTOR IN ELECTRONIC CIRCUIT - An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage. | 04-12-2012 |
20120105146 | REGULATOR CIRCUIT - A first transistor coupled between a power supply line and an inductor, a second transistor coupled between a source of the first transistor and a reference voltage line, and a third transistor coupled between the source of the first transistor and a load are included, and efficiency deterioration caused by a dead time is improved by keeping a current flow through a current path of an inductor, a load, and the third transistor during the dead time by supplying a voltage which is less than a threshold voltage and approximately the threshold voltage to a gate of the third transistor as a gate voltage. | 05-03-2012 |
20120126883 | VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME - A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed. | 05-24-2012 |
20120126884 | DOUBLE GATED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME - A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower gate on the opposite sidewall, wherein the first upper gate is formed above the first lower gate and the second upper gate is formed above the second lower gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first upper gate and second upper gate to preselect the transistors of a fin and then biasing the first lower gate and second lower gate to operate the transistors of the fin. | 05-24-2012 |
20120126885 | DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME - A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin. | 05-24-2012 |
20120133428 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 05-31-2012 |
20120188008 | CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF - A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET. | 07-26-2012 |
20120212289 | EMS TUNABLE TRANSISTOR - A field effect transistor comprises an electrostatically moveable gate electrode. The moveable gate is supported by at least two posts, and the source, drain, and channel of the transistor are centrally located under the moveable layer. At least one electrode is positioned on at least two sides of the source, drain, and channel. | 08-23-2012 |
20120223770 | RESETTABLE HIGH-VOLTAGE CAPABLE HIGH IMPEDANCE BIASING NETWORK FOR CAPACITIVE SENSORS - A high-voltage MEMS biasing network. The network has a reset mode wherein a capacitive sensor is charged, and a functional mode wherein the MEMS biasing network provides a high impedance between the capacitive sensor and a bias voltage source. The network includes a biasing circuit, a mirror circuit, and a control circuit. The biasing circuit and the mirror circuit have a charging state and a high impedance state. The control circuit includes a first branch that controls the biasing circuit and a second branch that controls the mirror circuit. The biasing network receives a logic control signal, the first branch puts the biasing circuit into the charging state when the logic control signal is a first logic signal, and puts the biasing circuit into the high impedance state when the logic control signal is a second logic signal. | 09-06-2012 |
20130009700 | Power Converter Circuit with AC Output - A power converter circuit includes output terminals, and a plurality of converter units each comprising input terminals configured to be coupled to a DC power source, and output terminals for providing an AC output voltage and an AC output current. The plurality of converter units are connected in series between the output terminals of the power converter circuit. At least one of the converter units is configured to detect its AC output voltage and its AC output current and is configured to regulate a generation of the AC output current such that a phase difference between the AC output voltage and the AC output current corresponds to a given set value. | 01-10-2013 |
20130033310 | CARBON NANOTUBE CROSSBAR BASED NANO-ARCHITECTURE - Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. A CNT crossbar based nano-architecture, includes layers of orthogonal carbon nanotubes with electrically bistable and charge holding molecules at each crossing, forming a dense array of reconfigurable double gate carbon nanotube field effect transistors (RDG-CNFETs) and programmable interconnects, which is addressed via a voltage controlled nanotube addressing circuits on the boundaries. | 02-07-2013 |
20130043941 | CURRENT-SENSING CIRCUIT - In one embodiment, a circuit is provided. The circuit includes a low-ohmic circuit and a a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load from which current can be drawn. The circuit also includes a current reference circuit, configured and arranged for setting a current reference level that is based on a portion of the current from the power supply node, and a current-sensing circuit. The current-sensing circuit senses and is responsive to current passing through the low-ohmic circuit. The current-sensing circuit operates in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is greater than the current threshold level. | 02-21-2013 |
20130069716 | TUNABLE VOLTAGE-CONTROLLED PSEUDO-RESISTOR - A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position V | 03-21-2013 |
20130082769 | DIFFERENTIAL PVT/TIMING-SKEW-TOLERANT SELF-CORRECTING CIRCUITS - Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor. | 04-04-2013 |
20130335139 | Isolator Circuit - An isolator circuit ( | 12-19-2013 |
20140002185 | VOLTAGE REGULATING CIRCUIT | 01-02-2014 |
20140022011 | SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURES COMPRISING COLOSSAL MAGNETOCAPACITIVE MATERIALS - Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor. | 01-23-2014 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 09-18-2014 |
20140320204 | ADJUSTABLE MOS RESISTOR - A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range. | 10-30-2014 |
20140354351 | CHOPPING CIRCUIT FOR MULTIPLE OUTPUT CURRENTS - A circuit for reducing flicker noise includes a first current source coupled to an input current. The circuit includes current minors to generate output currents in response to the input current. The output currents include the flicker noise. In addition, the circuit includes a chopping circuit to reduce the flicker noise from each of the output currents. | 12-04-2014 |
20150097617 | H-BRIDGE GATE CONTROL CIRCUIT - A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively. | 04-09-2015 |