Entries |
Document | Title | Date |
20080246540 | Semiconductor integrated circuit for voltage detection - A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well. | 10-09-2008 |
20090015322 | Integrated circuit with multiple layers of circuits - An integrated circuit | 01-15-2009 |
20090115504 | CIRCUIT DESIGN METHODOLOGY TO REDUCE LEAKAGE POWER - A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value. | 05-07-2009 |
20090184759 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a semiconductor integrated circuit device that reduces the influence of crosstalk noise and is operable properly even when relatively long signal wirings that pass over a macrocell are formed. In the semiconductor integrated circuit according to the present invention, buffering cells formed between the macrocell and an input/output circuit close thereto are connected to their corresponding signal wirings extended so as to pass over an area formed with the macrocell. | 07-23-2009 |
20090251206 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided. | 10-08-2009 |
20090289701 | Self-Identifying Stacked Die Semiconductor Components - A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components. | 11-26-2009 |
20100033239 | SEMICONDUCTOR DEVICE - A main chip has a signal processing circuit for executing signal processing; a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and a signal transmitting circuit; and a control circuit for controlling operation/non-operation of the signal transmitting circuits in accordance with signal processing content of the signal processing circuit. Functional chips each have a signal processing circuit for executing auxiliary signal processing different from that of the signal processing circuit; and one or a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and the signal transmitting circuits. The main chip and the functional chips are stacked. The signal transmitting circuits and the signal transmitting circuit are non-contact-type signal transmitting circuits utilizing inductive coupling and are arranged so as to overlap when viewed from the stacking direction. | 02-11-2010 |
20100127768 | SEMICONDUCTOR DEVICE AND ELECTRONIC INSTRUMENT - A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side. | 05-27-2010 |
20100164614 | Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules - An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell. | 07-01-2010 |
20100277232 | HYBRID MICROSCALE-NANOSCALE NEUROMORPHIC INTEGRATED CIRCUIT - Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer. | 11-04-2010 |
20100327966 | SEMICONDUCTOR DEVICE HAVING CIRCUIT BLOCKS WITH MUTUALLY THE SAME CIRCUIT CONFIGURATION - To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area. | 12-30-2010 |
20110001559 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data. | 01-06-2011 |
20110012673 | INTEGRATED CIRCUIT INCLUDING A LARGE NUMBER OF IDENTICAL ELEMENTARY CIRCUITS POWERED IN PARALLEL - The invention relates to an integrated circuit comprising a succession of N identical elementary circuits, juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V | 01-20-2011 |
20110050335 | LOW-CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION DIODES - A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width. | 03-03-2011 |
20110084758 | Semiconductor device - To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced. | 04-14-2011 |
20110090005 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND SUBSTRATE - A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes. | 04-21-2011 |
20110095816 | NETWORK ON CHIP BUILDING BRICKS - The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick. The bricks are oriented at 180° from one to the next in the direction of the columns and in the direction of the rows, and each brick comprises an even number of power supply conductor segments arranged symmetrically with respect to an axis of symmetry of the brick and connecting opposite edges of the brick. | 04-28-2011 |
20110102076 | Semiconductor integrated circuit - A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line. | 05-05-2011 |
20110109381 | Integrated Circuit Die Stacks With Rotationally Symmetric Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die. | 05-12-2011 |
20110109382 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a plurality of semiconductor chips is configured in such a manner that the plurality of semiconductor chips share one or more source voltages generated in one of the plurality of semiconductor chips. | 05-12-2011 |
20110128072 | REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through n | 06-02-2011 |
20110169564 | Integrated Circuit - An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down. | 07-14-2011 |
20110187450 | OUTPUT CIRCUIT OF SEMICONDUCTOR APPARATUS HAVING TWO DIFFERENT TYPES OF DECOUPLING CAPACITORS - An output circuit of a semiconductor apparatus having two different types of decoupling capacitors is presented. The output circuit includes a first pad, a second pad, a main output unit and a decoupling capacitor region. The first and second pads are configured to respectively provide a power supply voltage and a ground voltage. The main output unit is coupled to the first and second pads. One end of the decoupling capacitor region is coupled to the first pad and the other end is coupled to the second pad. The decoupling capacitor region includes a first decoupling capacitor region spaced apart from a portion of the main output unit by a first distance, and a second decoupling capacitor region spaced apart from the main output unit by a second distance which is greater than the first distance. | 08-04-2011 |
20110309881 | THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor. | 12-22-2011 |
20120086505 | SWITCHING CORE LAYOUT - Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection. | 04-12-2012 |
20120105144 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120105145 | Thermal Power Plane for Integrated Circuits - A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120176192 | Self-Identifying Stacked Die Semiconductor Components - A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components. | 07-12-2012 |
20120200347 | SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A skewed placement grid for an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a placement grid which includes a plurality of cells. Each of the plurality of cells includes one of a corresponding plurality of circuits. A center point of each of the cells is located at a unique coordinate along a first axis and a second axis with respect to each of the other ones of the plurality of cells. The IC further includes a first plurality of signal interconnections, wherein each of the plurality of signal interconnections is coupled to a corresponding one of the first plurality of circuits. | 08-09-2012 |
20120242403 | SWITCHING CORE LAYOUT - Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection. | 09-27-2012 |
20120256683 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line. | 10-11-2012 |
20120286858 | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells - An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together. | 11-15-2012 |
20130057339 | Circuit and Electronic Module for Automatic Addressing - An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration terminals. The auto addressing circuit is responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal. The integrated circuit is subsequently responsive to the node address when the node address is received. | 03-07-2013 |
20130154727 | DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS - A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained. | 06-20-2013 |
20130162344 | DISTRIBUTED LC RESONANT TANKS CLOCK TREE SYNTHESIS - A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption. | 06-27-2013 |
20130162345 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING A POWER CONTROLLABLE REGION - A semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit includes a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to outside the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to outside of the chip. When inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain. | 06-27-2013 |
20130162346 | INTERCONNECTION DEVICE IN A MULTI-LAYER SHIELDING MESH - An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines. | 06-27-2013 |
20130257527 | Providing Voltage Isolation On A Single Semiconductor Die - In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry. | 10-03-2013 |
20130271211 | MULTI-LAYERED SEMICONDUCTOR APPARATUS - Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus ( | 10-17-2013 |
20130285739 | Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation - The present invention relates to technologies for integrated circuits and Large Area Integrated Circuits (LAICs), which are integrated circuits made from photo-repetition of one or several reticle image fields, stitched together on at least one lithographic process layer. It also relates to a specific class of LAIC that can connect to the contacts of other ICs placed on its surface, where specific contact detection algorithms means are disclosed. The innovations include means for defect tolerance of serial communication links, means for efficient diagnosis of short and stuck-at faults in regular reconfigurable network, means for a programmable interposer for rapid prototyping of 3D stacked chips, means to build efficient large area micro-system devices (LAMS), with distributed and configurable hierarchical structures for power supply, thermal regulation and signal propagation, means to reduce mechanical/thermal/thermo-mechanical issues in LAMS devices, means to propagate analog signal on a configurable digital network, means to predict thermo-mechanical stress peaks. | 10-31-2013 |
20130293292 | INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK - Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules. | 11-07-2013 |
20130321074 | SEMICONDUCTOR INTEGRAGED CIRCUIT HAVING COMPATIBLE MODE SELECTION CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip or a plurality of semiconductor chip stacked therein, wherein each semiconductor chip includes, a compatible mode selection unit configured to select a chip allocation signal allocated to the semiconductor chip, among a plurality of chip allocation signals inputted through a plurality of pads, in response to a stack package information, and an internal circuit configured to perform a given operation in response to the chip allocation signal selected by the compatible mode selection unit. | 12-05-2013 |
20140097892 | DOUBLE PATTERNING COMPATIBLE COLORLESS M1 ROUTE - A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone. | 04-10-2014 |
20140152384 | TRANSMISSION LINE FOR AN INTEGRATED CIRCUIT PACKAGE - Communication between chips is provided using a transmission line. Any one of the chips may tap into the transmission line, and communicate with another chip tapped into the transmission line by transmitting a radio frequency (RF) signal to the other chip via the transmission line or receiving an RF signal from the other chip via the transmission line. The transmission line may include a microstrip transmission line, a waveguide, a stripline transmission line, or another type of transmission line. The chips may use the transmission line to communicate data, control and/or clock signals with one another. | 06-05-2014 |
20140176234 | APPARATUSES AND METHODS OF COMMUNICATING DIFFERENTIAL SERIAL SIGNALS INCLUDING CHARGE INJECTION - Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed. | 06-26-2014 |
20140184320 | SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal. | 07-03-2014 |
20140184321 | SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal. | 07-03-2014 |
20140218102 | INTEGRATED CIRCUIT - An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node. | 08-07-2014 |
20140253228 | INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION - An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block. | 09-11-2014 |
20140266418 | Stacked Chip System - A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other. | 09-18-2014 |
20140306753 | MULTI-CHIP PACKAGE SYSTEM - A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value. | 10-16-2014 |
20140320203 | SEMICONDUCTOR DEVICE - A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias | 10-30-2014 |
20150008979 | ACTIVE PEN IC WITH A REDUCED AMOUNT OF PADS AND A METHOD THEREOF - An active pen IC includes a plurality of pads coupled to receive a plurality of receive (RX) signals induced from a mobile device, the received RX signals constituting an original group of RX signals. The active pen IC also includes a permuting unit configured to permute the pads such that the received RX signals corresponding to the permuted pads constitute a generated group of RX signals. | 01-08-2015 |
20150022262 | COMPLETE SYSTEM-ON-CHIP (SOC) USING MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) TECHNOLOGY - Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required. | 01-22-2015 |
20150084689 | SEMICONDUCTOR CHIP INCLUDING A SPARE BUMP AND STACKED PACKAGE HAVING THE SAME - A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing. | 03-26-2015 |
20150130534 | INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK - Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules. | 05-14-2015 |
20150348941 | STACK PACKAGE AND REDUCTION OF STANDBY CURRENT - The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal. | 12-03-2015 |
20150371926 | INTEGRATED CIRCUIT HAVING MAIN ROUTE AND DETOUR ROUTE FOR SIGNAL TRANSMISSION AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAME - The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction. | 12-24-2015 |
20160036427 | PHOTOREPEATED INTEGRATED CIRCUIT WITH COMPENSATION OF THE PROPAGATION DELAYS OF SIGNALS, NOTABLY OF CLOCK SIGNALS - Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays. | 02-04-2016 |
20160064328 | MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING - Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers. | 03-03-2016 |
20160086920 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor device may include a first input/output (I/O) unit and a second I/O unit. The first I/O unit may include a first input path that receives a signal through a first pad and a first output path and a first I/O controller that output a signal to the first pad. The second I/O unit may include a second input path that receives a signal through a second pad and a second output path and a second I/O controller that output a signal to the second pad. | 03-24-2016 |
20160134262 | LOW-NOISE ARRANGEMENT FOR VERY-LARGE-SCALE INTEGRATION DIFFERENTIAL INPUT/OUTPUT STRUCTURES - Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other. | 05-12-2016 |
20160148901 | INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY - Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order. | 05-26-2016 |
20160148908 | MULTI-CHIP PACKAGE SYSTEM - A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value. | 05-26-2016 |
20160156359 | PARAMETER CONTROL METHOD FOR INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT USING THE SAME | 06-02-2016 |
20160163619 | SEMICONDUCTOR CHIP AND STACK TYPE SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals. | 06-09-2016 |
20190149147 | SIGNAL PROCESSING DEVICE | 05-16-2019 |