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Integrated structure

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327524000 - SPECIFIC IDENTIFIABLE DEVICE, CIRCUIT, OR SYSTEM

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
327565000 With specific layout or layout interconnections 64
Entries
DocumentTitleDate
20130043939Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture - An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.02-21-2013
20130043940BACK-TO-BACK STACKED DIES - Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.02-21-2013
20130027127INTEGRATED CIRCUIT SYSTEMS INCLUDING VERTICAL INDUCTORS - An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion.01-31-2013
20100164613SEMICONDUCTOR DEVICE REDUCING LEAKAGE CURRENT OF TRANSISTOR - A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.07-01-2010
20130082767SIGNAL DISTRIBUTION AND RADIATION IN A WIRELESS ENABLED INTEGRATED CIRCUIT (IC) - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.04-04-2013
20130033308SEMICONDUCTOR DEVICE - A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.02-07-2013
20130135041ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTION - An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.05-30-2013
20130049851ACTIVE PULL-UP/PULL-DOWN CIRCUIT - A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.02-28-2013
20130088289SEMICONDUCTOR CHIP PACKAGE INCLUDING VOLTAGE GENERATION CIRCUIT WITH REDUCED POWER NOISE - A semiconductor chip package illuminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.04-11-2013
20130088288INTEGRATED MAGNETIC FIELD SENSOR-CONTROLLED SWITCH DEVICES - Embodiments relate to integrated magnetic field sensor-controlled switch devices, such as transistors, current sources, and power switches, among others. In an embodiment, a magnetic switch and a load switch are integrated in a single integrated circuit device. In embodiments, the device can also include integrated load protection and load diagnostics. Embodiments can provide load switching and optional simultaneous logic signaling, for example to update a microcontroller or electronic control unit (ECU), while reducing space and complexity and thereby cost.04-11-2013
20130057338POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS - A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.03-07-2013
20130063206INTEGRATED CIRCUIT - Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.03-14-2013
20120229202Power efficient generation of band gap referenced supply rail, voltage and current references, and method for dynamic control - Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation. A Dynamic Control of the Commutating Components ensures least disturbance of the voltage potentials, thus allowing shorter ON times and respectively better power efficiency. The invention can also be applied to reference voltage and to bias current generator circuits.09-13-2012
20130162343INTEGRATED CIRCUIT SYSTEM - An integrated circuit system includes a first chip including a first node and configured to generate first identification information indicating the first chip in response to a voltage of the first node, a second chip including a second node and configured to generate second identification information indicating the second chip in response to a voltage of the second node, and a channel connected to the first node and the second node and generate a voltage difference between the first node and the second node.06-27-2013
20120112829SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V05-10-2012
20120112828Systems and methods for self powered electronic devices - The innovation teaches methods how electronic circuits can power themselves by detecting and converting the energy of electric field lines provided from the surrounding environment.05-10-2012
20120112827APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Design apparatuses according to the present embodiments each include a CDFG generator, a scheduler, a binder, a retention register selector, a control circuit generator, and an RTL description generator. The binder generates a data path circuit in which a hardware element is allocated to a CDFG after scheduling by the scheduler. The retention register selector detects, as a retention control step, one of the control steps which has a minimum number of latch bits from the CDFG after scheduling and selects, as a retention register, a register allocated to the detected retention control step. The control circuit generator generates a control circuit which performs an execution control of the data path circuit and causes a state to transition to the retention control step when a signal for power-off is enabled.05-10-2012
20110032029CONFIGURABLE EMBEDDED PROCESSOR - A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.02-10-2011
20100079203Semiconductor Device - An object is to provide a semiconductor device which operates normally even when the communication distance is extremely short, while the maximum communication distance is maintained, and which can make amplitude of a response waveform large even when a large amount of electric power is supplied to the semiconductor device and a protection circuit operates. The object is achieved with a semiconductor device including a first modulation circuit and a second modulation circuit each of which performs load modulation by an input signal, a detection circuit which determines an output signal by electric power supplied externally, a protection circuit which is controlled by the output signal of the detection circuit, and a modulation selecting circuit which switches the first modulation circuit and the second modulation circuit depending on the output signal of the detection circuit.04-01-2010
20110285459SEMICONDUCTOR DEVICE - A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.11-24-2011
20110298532INTEGRATED CIRCUIT, INTEGRATED CIRCUIT DESIGN DEVICE AND INTEGRATED CIRCUIT DESIGN METHOD - The disclosed integrated circuit includes a first and a second power supply wirings, a flip-flop circuit, and a switch element. The first and the second power supply wirings are connected to the common power supplies. The flip-flop circuit is required to hold the stored data even when the voltage supply from the power supplies to the integrated circuit is stopped. The flip-flop circuit is connected to the first power supply wiring. The switch element is a transistor, for example, and switches whether or not the voltage is supplied from the power supplies. The switch element is provided on the second power supply wiring.12-08-2011
20090160544SEMICONDUCTOR INTEGRATED CIRCUIT - A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area06-25-2009
20090284310SEMICONDUCTOR DEVICE - A semiconductor device which may be used as an ID chip and data may be rewritten only one time. In addition, a semiconductor device may be used as an ID chip and data may be written except when manufacturing the chip. The invention has a modulating circuit, a demodulating circuit, a logic circuit, a memory circuit, and an antenna circuit over an insulating substrate. The modulating circuit and the demodulating circuit are electrically connected to an antenna circuit, the demodulating circuit is connected to the logic circuit, the memory circuit stores an output signal of the logic circuit, and the memory circuit is a fuse memory circuit using a fuse element.11-19-2009
20110006840Fixing Full-Chip Violations Using Flip-Flops - A method of forming an integrated circuit includes providing a first design of the integrated circuit; analyzing the first design to identify a first flip-flop having setup/hold violations and a second flip-flop not having setup/hold violations; and replacing the first flip-flop with a third flip-flop having a substantially same cell delay as the first flip-flop to form a second design of the integrated circuit. The first flip-flop and the third flip-flop have different setup and hold windows.01-13-2011
20120068763SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.03-22-2012
20090079496MULTI-CHIP PACKAGE FOR REDUCING PARASITIC LOAD OF PIN - Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.03-26-2009
20100259320Semiconductor device capable of switching operation modes - A semiconductor device includes a substrate, a first internal terminal, a second internal terminal, a third internal terminal, and a fourth internal terminal which are placed along perimeter of the substrate, a circuit formed above the substrate and coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal and placed beside one side of the substrate where the second external terminal is located, wherein the circuit generates a signal indicative of a connection state between the first internal terminal and the first external terminal, and wherein the first internal terminal and the second internal terminal are arranged to form two rows in a direction perpendicular to one side of the substrate beside which the first external terminal is placed.10-14-2010
20100277231 FILTERING ON CURRENT MODE DAISY CHAIN INPUTS - Embodiments may include a data receiver having input for a current signal. The data receiver may further include a current generator to generate a reference current for comparison against the input current signal. The data receiver may also include a data converter having an input coupled to an intermediate node of the data receiver, the data converter comprising a plurality of cascaded stages with intermediate nodes among the stages.11-04-2010
20100148859Methods for Manufacturing RFID Tags and Structures Formed Therefrom - Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.06-17-2010
20120032735REDUCING COUPLING COEFFICIENT VARIATION BY USING CAPACITORS - A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace associated with a first port and a second port. The first port is configured substantially as an input port and the second port is configured substantially as an output port. The coupler further includes a second trace associated with a third port and a fourth port. The third port is configured substantially as a coupled port and the fourth port is configured substantially as an isolated port. In addition, the coupler includes a first capacitor configured to introduce a discontinuity to induce a mismatch in the coupler.02-09-2012
20110102074PROGRAMMABLE RF ARRAY - The present disclosure relates to radio frequency integrated circuits. More particularly, systems, devices and methods related to field programmable, software implemented, radio frequency integrated circuits are disclosed. In accordance with an exemplary embodiment, a field programmable, software implemented, radio frequency integrated circuit may comprise a high frequency IF embodiment. An input signal may be up converted to a high frequency, such as 60 GHz. Next, the amplitude and/or phase may be adjusted as desired. Subsequently, the signal may be down converted.05-05-2011
20110102075POWER DISTRIBUTION SYSTEM FOR INTEGRATED CIRCUITS - A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.05-05-2011
20110254618DIFFERENTIAL THERMISTOR CIRCUIT - This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.10-20-2011
20110254619Powered Device Including a Multi-Use Detection Resistor - In a particular embodiment, a method includes receiving a powered device (PD) detection signal at a PD from a powered network and applying the PD detection signal to an external resistor to provide a detection signature to the powered network. Further, the method includes receiving a PD classification mark signal at the PD, applying the received PD classification mark signal to the external resistor, and selectively activating a classification mark current path in parallel with the external resistor to produce a classification mark signature.10-20-2011
20110133825INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND SAMPLED CONTROL SIGNALS - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.06-09-2011
20110133827SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK06-09-2011
20110133826INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND QUEUE ALLOCATION - A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.06-09-2011
20110148516MINUTE CAPACITANCE ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.06-23-2011
20110181351Application Specific Power Controller - Configuring the operational behavior of an integrated circuit. The integrated circuit (IC) comprises a plurality of configuration inputs for configuring the IC. The IC also has a memory which stores a plurality of sets of parameter values. Each parameter value of the respective set corresponds to a different operational parameter of a plurality of operational parameters. The IC includes logic which determines a first plurality of configuration values corresponding to the first plurality of configuration inputs. The logic then selects a set of parameter values from the stored plurality of sets of parameter values. The selection of parameter values is based on the first plurality of configuration values. The IC is then configured for operation according to one or more operational parameter values in the selected set of parameter values.07-28-2011
20090108928LARGE-SCALE INTEGRATED CIRCUIT - A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.04-30-2009
20110050334Integrated Voltage Regulator with Embedded Passive Device(s) - A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.03-03-2011
20120007669ON-DIE ANTI-RESONANCE STRUCTURE FOR INTEGRATED CIRCUIT - A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.01-12-2012
20120025905Multiple circuit blocks with interblock control and power conservation - A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.02-02-2012
20120206196SEMICONDUCTOR MODULE - A PFC module includes: a diode bridge having first and second diodes in the upper arm, and third and fourth diodes in the lower arm; and first and second switching elements for power factor correction. The first and second diodes are Schottky barrier diodes formed by using a wide bandgap semiconductor. The third and fourth diodes, and the first and second switching elements are Schottky barrier diodes and switching elements respectively formed by using silicon.08-16-2012
20120062314SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM OF CONTROLLING THE SAME - According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first power supply terminal. The second circuit is configured to have a second power supply terminal independent of the first power supply terminal. The signal propagation control circuit is configured to provide a first fixed value to the second circuit for a predetermined period after power is supplied to the second circuit, and after the predetermined period, configured to control whether to transfer an output signal from the first circuit to the second circuit or provide the first fixed value to the second circuit.03-15-2012
20110018623INTEGRATED CIRCUIT PACKAGE - An integrated circuit combination, comprising first and second integrated circuit dies with respective first and second control register banks, and a path for external control data, within said combination, coupling a first data interface on said first die, which receives the external control data, to the first and second control register banks.01-27-2011
20110090004RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES - Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.04-21-2011
20100244946SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.09-30-2010
20110181350HIGH FREQUENCY SEMICONDUCTOR DEVICE - According to one embodiment, a high frequency semiconductor device is provided, which includes: a distribution/input matching circuit board that mounts thereon a distribution/input matching circuit and an input transmission line pattern; an input capacitor board that is arranged adjacent to the distribution/input matching circuit board, and mounts a plurality of input capacitor cells thereon; a semiconductor board that is arranged adjacent to the input capacitor board, and mounts a plurality of field effect transistor cells thereon; an output capacitor board that is arranged adjacent to the semiconductor board, and mounts a plurality of output capacitor cells thereon; and a synthesis/output matching circuit board that is arranged adjacent to the output capacitor board, and mounts thereon an output transmission line pattern and a synthesis/output matching circuit, wherein the number of active field effect transistor cells is changed by connecting and disconnecting a plurality of field effect transistor cells to one another in response to a desired output power value, whereby a total gate electrode length is substantially changed, and an output power value is adjusted.07-28-2011
20120133427Semiconductor Devices And Methods Of Controlling Temperature Thereof - An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.05-31-2012
20120249230INTEGRATED CIRCUIT POWER CONSUMPTION CALCULATING APPARATUS AND PROCESSING METHOD - An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of each of the circuit components.10-04-2012
20120169415SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS - A semiconductor device is disclosed. The structure includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.07-05-2012
20120182066METHOD OF MANUFACTURING A PACKAGE FOR EMBEDDING ONE OR MORE ELECTRONIC COMPONENTS - The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.07-19-2012
20090021298METHOD AND APPARATUS TO SELECT A PARAMETER/MODE BASED ON A TIME MEASUREMENT - Techniques are disclosed to select functional parameters and/or operating modes of a circuit based on a time measurement are disclosed. One example integrated circuit includes a threshold detection and timing circuit that is coupled to measure a signal during an initialization period of the integrated circuit from a multifunction capacitor that is to be coupled to a first terminal of the integrated circuit. A selection circuit is coupled to the threshold detection and timing circuit to select a parameter/mode of the integrated circuit in response to the measured signal from the multifunction capacitor during the initialization period of the integrated circuit. The multifunction capacitor is coupled to provide an additional function for the integrated circuit after the initialization period of the integrated circuit is complete.01-22-2009
20120268199Chip Having Register to Store Value that Represents Adjustment to Reference Voltage - A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.10-25-2012
20110215863Integrated Voltage Regulator with Embedded Passive Device(s) - A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator.09-08-2011
20120081176On-Die Voltage Regulation Using p-FET Header Devices with a Feedback Control Loop - The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or of the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.04-05-2012
20120326775CHIP SELECT CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A chip select circuit includes a chip select identification unit, a chip select control unit and a data input unit. The chip select identification unit generates a chip select identification signal in response to a chip select enable signal and an address signal. The chip select control unit provides the chip select identification signal as a chip select signal or provides a signal fixed to a predetermined level as the chip select signal, in response to a test mode signal. The data input unit receives data in response to the chip select signal.12-27-2012
20130015915SEMICONDUCTOR DEVICEAANM KOMATSU; YukioAACI Kanagawa-kenAACO JPAAGP KOMATSU; Yukio Kanagawa-ken JPAANM Ohta; HitoshiAACI Kanagawa-kenAACO JPAAGP Ohta; Hitoshi Kanagawa-ken JPAANM Awano; DaisukeAACI Kanagawa-kenAACO JPAAGP Awano; Daisuke Kanagawa-ken JP - A semiconductor device including: a first pad to receive first and second test commands supplied from the outside; a voltage generator circuit to generate a test target voltage on the basis of the first and second test commands; a second pad to receive first and second monitor voltages supplied from the outside in response to respective of the first and second test commands, the first and second monitor voltages corresponding to respective lower and upper limit voltages of the test target voltage; and a comparator to output a first output signal at one of first and second logical levels by comparing the test target voltage with the first monitor voltage, and to output a second output signal at one of the first and second logical levels by comparing the test target voltage with the second monitor voltage.01-17-2013
20130021093DUAL-FUNCTION INTEGRATED CIRCUIT - An electronic circuit in a package, including two functions, the package orientation activating a single one of the two functions.01-24-2013
20110273228MULTIPLE E-PROBE WAVEGUIDE POWER COMBINER/DIVIDER - A power combiner/divider having a waveguide, a plurality of amplifiers disposed on a supporting structure, a plurality of probes, each one having a first end electrically coupled to an output of a corresponding one of the plurality of amplifiers and a second end projecting outwardly from the supporting structure and into the waveguide. The probes are disposed in a common region of the waveguide. The region has a common electric field maximum within the waveguide. A first portion of the probes proximate the sidewalls have lengths different from a second portion of the probes disposed in a region distal from the sidewalls of the waveguide. The waveguide is supported by the support structure. The power combiner is a monolithic microwave integrated circuit structure.11-10-2011
20130169355Integrated Circuit Device - An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.07-04-2013
20120249229SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.10-04-2012
20120256682Method and Apparatus to Enable a Selective Push Process During Manufacturing to Improve Performance of a Selected Circuit of an Integrated Circuit - Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.10-11-2012
20100315159HIGH VOLTAGE POWER INTEGRATED CIRCUIT - A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.12-16-2010
20130194035SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V08-01-2013

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