Class / Patent application number | Description | Number of patent applications / Date published |
327560000 | Nonlinear amplifying circuit | 26 |
20080284506 | System and method for controlling an electromagnetic field generator - A system for driving an electromagnetic field generator. In one aspect, the system may include a plurality of transistors arranged in an H-bridge configuration, the H-bridge having first and second output terminals, first and second switching inputs, and a power input. The system may further include a control transistor coupling the power input to a power supply, and a diode having a cathode coupled to the power input and an anode coupled to ground. The first and second output terminals may be coupled to the electromagnetic field generator and the first and second switching inputs may receive switching signals based on an output of the electromagnetic field generator. | 11-20-2008 |
20100097134 | APPARATUS FOR GENERATING A CORRECTION SIGNAL - An apparatus for generating a correction signal for linearizing an output signal of a non-linear element includes a correction signal generator. The correction signal generator is configured to generate a correction signal on the basis of a superposition of a digital reference signal and a superposed output signal. The superposed output signal is based on a superposition of the output signal and an analog reference signal. | 04-22-2010 |
20100219884 | TRANSMITTER, RECEIVER, POWER AMPLIFICATION METHOD, AND SIGNAL DEMODULATION METHOD - There is provided a transmitter including a nonlinear input-output conversion characteristic control unit configured to determine a nonlinear input-output conversion characteristic for converting a signal depending on a usage status of a frequency band; an amplitude control unit configured to convert an amplitude of the signal based on the determined nonlinear input-output conversion characteristic; and a transmission power amplification unit configured to amplify power of the signal with the converted amplitude. There is also provided a transmitter including a nonlinear input-output conversion characteristic control unit configured to determine a nonlinear input-output conversion characteristic for converting a signal depending on a usage status of a frequency band; plural transmission power amplification units having different nonlinear input-output conversion characteristics; and a selecting unit configured to select one of the plural transmission power amplification units based on the determined nonlinear input-output conversion characteristic. | 09-02-2010 |
20110121894 | APPARATUS AND METHOD FOR POWER ADDED EFFICIENCY OPTIMIZATION OF HIGH AMPLIFICATION APPLICATIONS - A power added efficiency optimizer apparatus is provided for measuring and monitoring input and output power of an amplifying device, and adjusting the load impedance seen by the amplifying device so that power added efficiency is maintained at optimum levels. A power added efficiency optimizing device includes a variable load impedance that can be controlled, at least one power detection device located after the load, a difference forming apparatus, and at least one coupling device. The power added efficiency optimizing device provides an ability to maintain an amplifier at peak efficiency in a dynamic way and in the presence of changing electromagnetic load conditions. | 05-26-2011 |
20110285458 | RMS Detector with Automatic Gain Control - Embodiments of the present invention provide systems, devices and methods for detecting the RMS value of a signal. The RMS detector uses multiple variable-gain stages and internal gain control to generate an RMS output signal based on an arbitrary signal input. This RMS detector significantly reduces the signal swings seen on a squarer within prior art RMS detectors and reduces the detector's dependency on DC offsets at low signal levels and overload errors at high signal levels. The embodiments of the present invention also improve the accuracy of the RMS detector within large dynamic signal ranges by obviating the operation of a squarer in saturation or out of the squaring region. Accordingly, embodiments of the present invention are able to more accurately detect RMS values on a signal, operate over relatively higher signal ranges, and better function within different signal modulation schemes, particularly those with large peak-to-average ratios. | 11-24-2011 |
20120038417 | INTEGRATED CIRCUIT FOR REDUCING NONLINEARITY IN SAMPLING NETWORKS - An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input. | 02-16-2012 |
20120161863 | AMPLIFIER PROVIDING POWER RECOVERY FROM A NARROW-BAND ANTENNA - A method, amplifier and system are provided for enabling power recovery from a narrow-band antenna when a signal having bandwidth exceeding that of the antenna is utilized. The amplifier provides amplification of a source signal to the antenna and recovery of power stored in the antenna during periods when the impedance of the antenna is negative to enable reverse current through the amplifier to a direct current (DC) power source. | 06-28-2012 |
20120176191 | DIGITAL COMPENSATION OF A NONLINEAR SYSTEM - A method for digital compensation of a nonlinear system comprises identifying a plurality of circuit parameters of a nonlinear system. Each circuit parameter determines a nonlinear response of the nonlinear system. A first circuit parameter is chosen from the plurality of circuit parameters. The first circuit parameter determines a first effect on the nonlinear response. The first effect is at least as large a second effect from a second circuit parameter from the plurality of circuit parameters. At least one stimulus is applied to the nonlinear system. The nonlinear response of the nonlinear system is measured in response to the at least one stimulus. A compensation architecture is synthesized to substantially linearize the nonlinear response. The compensation architecture receives the nonlinear response of the nonlinear system and provides a substantially linear response. | 07-12-2012 |
20120293249 | POWER AMPLIFIER INSENSITIVE TO LOAD IMPEDANCE CHANGES - Disclosed herein is a power amplifier insensitive to load impedance changes. According to the present invention, the power amplifier comprises a power amplification circuit which amplifies an input signal, an output matching circuit connected to an output terminal of the power amplification circuit to perform impedance matching between the power amplification circuit and an antenna load, and a 4-port coupler connected between the output matching circuit and the antenna load. | 11-22-2012 |
20130200947 | Programmable antenna having metal inclusions and bidirectional coupling circuits - A programmable antenna includes a substrate, metallic inclusions, bidirectional coupling circuits, and a control module. The metallic inclusions are embedded within a region of the substrate. The bidirectional coupling circuits are physically distributed within the region and are physically proximal to the metallic inclusions. The control module activates a set of bidirectional coupling circuits, which, when active, the set of interconnects a set of metallic inclusions to provide a conductive area within the region. The conductive area functions an antenna. | 08-08-2013 |
20160134240 | METHOD AND CIRCUITRY FOR CMOS TRANSCONDUCTOR LINEARIZATION - Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor. | 05-12-2016 |
327561000 | With operational amplifier | 3 |
20080218257 | Distributed track-and-hold amplifier - An apparatus includes an analog input buffer having one or more inputs and one or more outputs, a plurality of differential track-and-hold stages, one or more input transmission lines, and one or more output transmission lines. Each track-and-hold stage has one or more inputs and one or more outputs. The one or more input transmission lines connect the one or more outputs of the differential analog input buffer to the inputs of the track-and-hold stages. The one or more output transmission lines connect to the outputs of the track-and-hold stages. The connections to the inputs of the stages are spatially distributed along the one or more input transmission lines, and connections to the outputs of the stages are spatially distributed along the one or more output transmission lines. | 09-11-2008 |
327562000 | With field-effect transistor | 2 |
20080272839 | OPERATION AMPLIFIER AND CIRCUIT FOR PROVIDING DYNAMIC CURRENT THEREOF - An operation amplifier (op-amp) and a circuit for providing dynamic current thereof are disclosed. The circuit can be applied to any current op-amp. The circuit comprises two transistors which are simultaneously or non-simultaneously turned on as the input signals respectively received by the first input and the second input of the op-amp get a transition, namely, as the op-amp is in the transient state, so as to increase the bias current at the first input terminal or/and the second input terminal of the op-amp by a dynamic current. Therefore, not only the internal slew rate of the op-amp can be accelerated by the circuit of the present invention, but also the power consumption of the op-amp can not be increased by the circuit of the present invention as the op-amp in the steady state. | 11-06-2008 |
20110298531 | CHARGE STORAGE CIRCUIT FOR A PIXEL, AND A DISPLAY - A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors ( | 12-08-2011 |
327563000 | With differential amplifier | 12 |
20090167427 | Power circuit and power amplifier and base station device using the same - Disclosed are a high-efficiency power amplifier and base station device with respect to high-speed, broadband radio communication method. A broadband power supply circuit includes a linear voltage amplifier to which an input signal is applied, a resistor connected to an output side of the linear voltage amplifier, a switching regulator amplifying the voltage difference between both ends of the resistor to convert the amplified voltage difference into current, and a high frequency amplifier. The high frequency amplifier is designed to exhibit high efficiency at a frequency band where the efficiency of the switching regulator starts to be deteriorated, or at a high frequency band where the operation of the linear amplifier is dominant. In this case, the amplification of low frequency components are performed by the switching regulator, and the amplification of high frequency components are performed by the linear amplifier and the high frequency amplifier. | 07-02-2009 |
20090219085 | DIFFERENTIAL TO SINGLE-ENDED CONVERSION CIRCUIT AND COMPARATOR USING THE CIRCUIT - An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs. | 09-03-2009 |
20100039173 | SINGLE-ENDED SENSE AMPLIFIER USING DYNAMIC REFERENCE VOLTAGE AND OPERATION METHOD THEREOF - A single-ended differential sense amplifier comprises a dynamic reference voltage generation circuit and a differential sense amplifier circuit. Input data with an input data line voltage is provided to the differential sense amplifier circuit. The input data line voltage also feeds back to the dynamic reference voltage generation circuit, which then generates a dynamic reference voltage based on the input data line voltage. The differential sense amplifier circuit is coupled to the dynamic reference voltage generation circuit and receives the dynamic reference voltage for determining the input data. The dynamic reference voltage increases and the input data line voltage decreases when reading the input data of a logic state, e.g., logic “0.” | 02-18-2010 |
20100052777 | High Performance Input Receiver Circuit For Reduced-Swing Inputs - An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain “buffered” output signals therefrom with symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two stages of differential amplifier pairs (i.e., a total of 4 separated differential amplifiers). The differential amplifiers in the first stage convert the single-ended input signal to a full-differential signal, which is then converted back to a single-ended output signal by the differential amplifier pair in the second stage. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross” coupled structure. Various current saving and biasing methods may also be employed to keep the operating current the same or lower than the previous receiver circuit designs. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 03-04-2010 |
20100214015 | DETECTION CIRCUIT AND PHYSICAL QUANTITY SENSOR DEVICE - A switched capacitor has a differential amplifier and a sampling capacitance and a feedback capacitance at least one of which has a variable capacitance value, and is switchable between a first drive mode of amplifying an input signal with a positive gain responsive to the capacitance ratio of the sampling capacitance to the feedback capacitance and a second drive mode of amplifying the input signal with a negative gain responsive to the capacitance ratio. A control circuit changes the capacitance ratio, and also changes the drive mode of the switched capacitor, at predetermined timing. | 08-26-2010 |
20100259319 | LOW NOISE AMPLIFIER WITH COMBINED INPUT MATCHING, BALUN, AND TRANSMIT/RECEIVE SWITCH - A low noise amplifier (LNA) with combined input matching, balun, and/or transmit/receive (T/R) switch is described. In one exemplary design, an apparatus includes a coupled inductor and an LNA. The coupled inductor receives a single-ended input signal, performs single-ended to differential conversion, and provides a differential input signal. The LNA receives and amplifies the differential input signal and provides a differential output signal. The coupled inductor includes magnetically coupled first and second coils. The first coil provides input impedance matching when the LNA is enabled. A resonator circuit formed with the first coil provides high input impedance when the LNA is disabled. A tuning capacitor coupled to the second coil provides amplitude imbalance tuning for the differential input signal. A transmit switch is coupled between the first coil and a transmitter. | 10-14-2010 |
20100308904 | DEVICE FOR GENERATING A REFERENCE VOLTAGE DESIGNED FOR A SYSTEM OF THE SWITCHED-CAPACITOR TYPE - The device generates a reference voltage, in particular designed for a system of the switched-capacitor type, based on a setpoint voltage. It includes a regulation loop having a first input to receive the setpoint voltage, and an output stage arranged as a voltage follower and looped to a second input of the loop. An additional stage is configured to deliver the reference voltage to the switched-capacitor system, this additional stage, coupled to the output stage, also being arranged as a voltage follower and paired with the output stage. | 12-09-2010 |
20110227639 | Method and Apparatus for Suppressing Bitline Coupling Through Miller Capacitance to a Sense Amplifier Interstitial Node - A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs. | 09-22-2011 |
20120146718 | HIGH PERFORMANCE INPUT RECEIVER CIRCUIT FOR REDUCED-SWING INPUTS - An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive reduced-swing and high bandwidth inputs to provide “buffered” output signals having symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two differential amplifier pair stages (i.e., 4 total differential amplifiers). The first stage of differential amplifiers convert the single-ended input signal to a full-differential signal, which is converted back to a single-ended output signal by the second stage of differential amplifiers. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross coupled” structure. Various current saving and biasing methods may also be employed to keep operating current the same or lower than previous designs. | 06-14-2012 |
20130038387 | Detector Circuit - A detector circuit can be used for determining the reflection coefficients of HF signals in a signal path. The detector circuit includes a bidirectional hybrid coupler, logarithmic amplifiers connected to the hybrid couple, and a subtractor having an offset connection. | 02-14-2013 |
20130135040 | HIGHLY LINEAR, LOW-POWER, TRANSCONDUCTOR - Systems and methods which implement a transconductor replica feedback (TRF) block in a transconductor circuit are shown. In accordance with embodiments, the TRF block comprises a feedback transistor disposed as a replica of a corresponding transconductance transistor of the transconductor circuit. The TRF block provides enhanced looking-in degeneration impedance for the transconductor circuit, thereby allowing for higher linearity and lower power at the same time. TRF transconductors of embodiments can be implemented in, or otherwise applied to, various different circuits such as LNAs, filters, etc. | 05-30-2013 |
20140002182 | OUTPHASING POWER COMBINING BY ANTENNA | 01-02-2014 |