Class / Patent application number | Description | Number of patent applications / Date published |
327545000 | Including signal protection or bias preservation | 15 |
20090153237 | COMPENSATION CAPACITOR NETWORK FOR DIVIDED DIFFUSED RESISTORS FOR A VOLTAGE DIVIDER - A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is connected across the resistors and the voltage divider output. The feed-forward capacitor network allows the output to rise and fall quickly with a change in the voltage divider input. Accordingly, an improved frequency response should be obtained utilizing divided diffused resistors. | 06-18-2009 |
20100001789 | SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE THROUGH ADJUSTMENT OF RELATIVE SIGNAL LEVELS - Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential. Regardless of the particular embodiment used, raising the midpoint-voltage level of the signals on the TWIs relative to the substrate decreases capacitance, which increases the frequency of the data which can propagate through the TWIs while potentially reducing the signaling power. | 01-07-2010 |
20100253422 | SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter. | 10-07-2010 |
20110291749 | APPARATUS AND METHOD FOR PROTECTING A SEMICONDUCTOR JUNCTION - Apparatus and methods are disclosed, such as those involving protection of a semiconductor junction of a semiconductor device. One such apparatus includes a bipolar transistor including an emitter, a base, and a collector; a first junction protection device including a first end electrically coupled to the emitter of the bipolar transistor, and a second end electrically coupled to a node; and a second junction protection device including a first end electrically coupled to a voltage reference, and a second electrically coupled to the emitter of the bipolar transistor. Each of the first and second junction protection devices may have a substantially higher leakage current than the leakage current of the base-emitter junction of the bipolar transistor when reverse biased. | 12-01-2011 |
327546000 | With field-effect transistor | 11 |
20080303588 | REFERENCE VOLTAGE GENERATING CIRCUIT AND CONSTANT VOLTAGE CIRCUIT - A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate. | 12-11-2008 |
20090058517 | High Voltage Tolerant Input Buffer - An input buffer protection circuit is disclosed which comprises a NMOS transistor with a source, drain and gate coupled to an input terminal of the input buffer, a pad and a chip peripheral positive power supply voltage (VDDP), respectively, and a PMOS transistor with a source, drain and gate coupled to the pad, the input terminal of the input buffer and a first terminal of a biasing circuit, respectively, wherein the biasing circuit has a second terminal coupled to the pad and generates at the first terminal a voltage lower than the pad's input signal voltage (VPAD) to turn on the PMOS transistor when the VPAD is lower than or equal to the VDDP, or a voltage substantial equals to the VPAD to turn off the PMOS transistor when the VPAD is higher than the VDDP. | 03-05-2009 |
20090108922 | Method and System for Managing Voltage Swings Across Field Effect Transistors - A circuit for managing voltage swings across FETs comprising a reference precision resistor, a first FET and a second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first FET and the third FET maintain a linear relationship with respective drain to source voltages of the first FET and the third FET. | 04-30-2009 |
20090108923 | Structure for Precision Integrated Phase Lock Loop Circuit Loop Filter - A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor. | 04-30-2009 |
20090108924 | Structure for Managing Voltage Swings Across Field Effect Transistors - A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs. | 04-30-2009 |
20090160542 | STABLE VOLTAGE GENERATING CIRCUIT FOR A DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF GENERATING A STABLE VOLTAGE FOR A DELAY LOCKED LOOP - A stable voltage generating circuit for a delay locked loop for generating a stable internal voltage for a delay locked loop and a semiconductor memory device including the same, and a method of generating a stable voltage for a delay locked loop is disclosed. The voltage generating circuit includes a first detector which compares a feedback voltage that represents the internal voltage for the delay locked loop with a reference voltage and outputs the comparison result as a first detection signal. A second detector detects the escape timing of a power down mode to provide a second detection signal having a configurable enable width interval after the escape timing of the power down mode. Finally, the voltage generating circuit includes a voltage driver which drives and outputs the internal voltage either the first detection signal or the second detection signal is enabled to maintain a stable internal voltage level. | 06-25-2009 |
20090174470 | LATCH-UP PROTECTION DEVICE - A latch-up protection device is provided. The latch-up protection device includes a first transistor, a detection module, and a processing module. The first transistor includes a first source/drain coupled to a pad, a body and a second source/drain coupled to a first voltage, and a gate. The detection module is adapted for detecting a terminal voltage between the first source/drain and the second source/drain of the first transistor, and generating a first signal when the terminal voltage is greater than a trigger voltage. The processing module is coupled between the detection module and the gate of the first transistor, for conducting a logic processing to the first signal, and generating an enable signal to the gate of the first transistor to conduct the first transistor. | 07-09-2009 |
20090243714 | Power noise immunity circuit - A power noise immunity circuit includes a unidirectional device and a switch both connected between a power input terminal and a power output terminal, and a noise detector to control the switch. The power input terminal is for being connected to an external voltage source, and the power output terminal is for being connected to the circuit of an IC. The switch is normally closed and is opened by the noise detector if the noise detector detects power noise at the power input terminal. The power noise immunity circuit thus prevents the IC from power breakdown and provides a stable voltage thereto. | 10-01-2009 |
20100090756 | SWITCHED CAPACITOR CIRCUIT WITH REDUCED LEAKAGE CURRENT - Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode. | 04-15-2010 |
20110227637 | Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge - A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body. | 09-22-2011 |
20160003887 | ISOLATOR, SEMICONDUCTOR DEVICE, AND METHOD FOR CONTROLLING ISOLATOR - An isolator includes: a transmission circuit that generates an alternating current transmission signal in which a first potential is set to be a reference potential; a first insulating element to which the alternating current transmission signal is supplied; a second insulating element that generates an alternating current reception signal in which a second potential is set to be a reference potential by being alternating current-coupled to the first insulating element through an insulating film; a reception circuit that reproduces reception data based on the alternating current reception signal; an impedance control unit that controls an impedance of the first or the second insulating element to be higher than an impedance before the control; and a leakage current detection unit that detects a leakage current flowing between the first and the second insulating elements through the first or the second insulating element in which the impedance has been controlled. | 01-07-2016 |