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Having stabilized bias or power supply level

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327524000 - SPECIFIC IDENTIFIABLE DEVICE, CIRCUIT, OR SYSTEM

327530000 - With specific source of supply or bias voltage

327534000 - Having particular substrate biasing

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
327536000 Charge pump details 338
327537000 With field-effect transistor 99
Entries
DocumentTitleDate
20130043929POWER SUPPLY DEVICES AND CONTROL METHOD THEREOF - A power supply device is provided. The power supply device provides a maintenance voltage at an output terminal to a system chip of a system and includes a first battery, a capacitor, a charging circuit, and a monitoring circuit. The first battery provides a battery voltage. The capacitor stores a capacitor voltage. The charging circuit is coupled to the capacitor. The monitoring circuit detects whether the battery voltage is less than a first threshold and whether the capacitor voltage is larger than a second threshold and generates a control signal according to the determination result. When the monitoring circuit detects that the battery voltage is less than the first threshold and the capacitor power supply device voltage is not larger than the second threshold, the monitoring circuit asserts the control signal to control the charging circuit to charge the capacitor.02-21-2013
20100156511BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH - A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.06-24-2010
20090195297CCD DEVICE AND METHOD OF DRIVING SAME - Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate.08-06-2009
20100109757COMPENSATION OF OPERATING TIME-RELATED DEGRADATION OF OPERATING SPEED BY A CONSTANT TOTAL DIE POWER MODE - By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.05-06-2010
20120218031METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (08-30-2012
20090237145Semiconductor device - A semiconductor device includes an interface circuit that varies drive ability according to a control signal, and a control circuit that generates the control signal according to a range of an output voltage of the interface circuit. The interface circuit and the control circuit are provided on one chip.09-24-2009
20130162333Apparatus and associated methods - An apparatus including first and second layers of electrically conductive material separated by a layer of electrically insulating material, wherein one or both layers of electrically conductive material include graphene, and wherein the apparatus is configured such that electrons are able to tunnel from the first layer of electrically conductive material through the layer of electrically insulating material to the second layer of electrically conductive material.06-27-2013
20120286853SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a main circuit including a transistor, a pseudo-power supply line connected to a first power supply terminal of the main circuit, a first power supply line connected to the pseudo-power supply line via a first switch, a second power supply line connected to a second power supply terminal of the main circuit, a diode having a first end connected to the pseudo-power supply line and a second end connected to the first power supply line so that a potential difference between the pseudo-power supply line and the second power supply line is reduced in a conductive state, and a second switch having a first end connected to the pseudo-power supply line and a second end connected to the second power supply line.11-15-2012
20110316616SEMICONDUCTOR INTEGRATED CIRCUIT FOR CONTROLLING POWER SUPPLY - A semiconductor integrated circuit includes a plurality of circuit regions, at least one power source switch that switches between two states of supplying power or not supplying power to at least one of the plurality of circuit regions, a power source control circuit that controls the at least one power source switch, a clamp scan chain having a plurality of flip-flops to which an output from the at least one circuit region to another region is input, and a clamp data control circuit that sets the plurality of flip-flops of the clamp scan chain to a predetermined output state.12-29-2011
20090284306METHOD OF PRODUCING A LOW-VOLTAGE POWER SUPPLY IN A POWER INTEGRATED CIRCUIT - In a chip containing high-voltage device with a semiconductor substrate of a first conductivity type, a method of implementing low-voltage power supply is provided, wherein the electrical potential of an isolated region of a second conductivity type in a surface portion is used as one output terminal or as a voltage by which a transistor is controlled to provide output current for a low-voltage power supply. The other output terminal could be either terminal of the two that apply high voltage to high-voltage device or could be a floating terminal. Using this method, a low-voltage power supply can be implemented not only for the low-voltage integrated circuit (I) in a power IC containing one high-voltage device, but also for the low-voltage integrated circuit in a power IC having totem-pole connection or CMOS connection. As there is no need to implement depletion mode device in the chip, the fabrication cost is reduced.11-19-2009
20110163795SEMICONDUCTOR CIRCUIT AND COMPUTER SYSTEM - A device includes, but is not limited to, a first transistor, a first current mirror circuit, a second transistor, and a first compensation circuit. The first transistor is controlled by a first control voltage. The first current mirror circuit is driven by the first transistor as a first current source. The second transistor is driven by the first current mirror circuit. The second transistor has a first output voltage that varies depending on the first control voltage. The first compensation circuit reduces variations of the first output voltage. The variations of the first output voltage are caused by variations in performance of the first and second transistors.07-07-2011
20110291745LOW-NOISE CURRENT SOURCE - A low noise current source includes first and second voltage input terminals. The current source further includes an amplifying device having an input terminal and an output terminal, where the output terminal is coupled to the second voltage input terminal via a load. The current source also includes a bias circuit coupled between the first voltage input terminal, the second voltage input terminal, and the input terminal. The current source additionally includes a first bypass circuit coupled between the first voltage input terminal and the input terminal, where the first bypass circuit configured to provide a substantially high electrical resistance and substantially no electrical impedance between the first voltage input terminal and the input terminal.12-01-2011
20100271113INTEGRATED CIRCUIT WITH MULTIPLE INDEPENDENT POWER SUPPLY ZONES - An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.10-28-2010
20090206914SEMICONDUCTOR DEVICE GENERATING VARIED INTERNAL VOLTAGES - The present invention describes a semiconductor device that generates internal voltages having different levels using an external voltage. The semiconductor device includes a plurality of asynchronous internal voltage generating circuits that share an external voltage source and generate internal voltages having different levels from one another. The plurality of asynchronous internal voltage generating circuits maintain the levels of the internal voltages at target levels by using the external voltage at different time points, respectively. The semiconductor device minimizes noise in the external voltage according to the use of the internal voltages.08-20-2009
20080284495MOS CAPACITOR WITH LARGE CONSTANT VALUE - A capacitor circuit includes a first capacitor having a positive terminal coupled to a first node and a negative terminal coupled to a second node, a second capacitor having a negative terminal coupled to the first node and a positive terminal coupled to the second node, a third capacitor having a positive terminal coupled to the first node and a negative terminal coupled to a third node, a fourth capacitor having a negative terminal coupled to the first node, and a positive terminal coupled to the third node, a first voltage drop generator coupled between the second node and a fourth node for providing a first voltage drop between the second node and the fourth node, and a second voltage drop generator coupled between the fourth node and the third node for providing a second voltage drop between the fourth node and the third node.11-20-2008
20090261889DATA OUTPUT CLOCK SIGNAL GENERATING APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THE SAME - A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.10-22-2009
20090261888AUTONOMOUS CONTROL OF MULTIPLE SUPPLY VOLTAGE GENERATORS FOR DISPLAY DRIVERS - Circuits and methods to operate an arrangement of one or more charge pumps with two or more power supplies where each supply is able to vary over a range of voltages, and where any one supply can be of a higher or lower voltage than any of the others have been achieved. In a preferred embodiment the output of the arrangement of charge pumps is used to drive an electronic display. The strongest power supply available is selected and the arrangement of one or more charge pumps is reconfigured according to the value of the actual strongest supply voltage. In case of a change of a source of supply voltage the operation of the charge pumps during the short time required for reconfiguration. While the charge pump is running it can be suspended, reconfigured and released or restarted in the case of a change of supply source, or simply reconfigured on-the-fly without suspending in the case of a selected supply voltage change.10-22-2009
20110199151INCREASING CHARGE CAPACITY OF CHARGE TRANSFER CIRCUITS WITHOUT ALTERING THEIR CHARGE TRANSFER CHARACTERISTICS - A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.08-18-2011
20080246534MULTI-CHIP SEMICONDUCTOR DEVICE WITH HIGH WITHSTAND VOLTAGE, AND A FABRICATION METHOD OF THE SAME - A multi-chip semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a plastic mold. The first semiconductor chip has a function for executing a predetermined electrical operation and is installed on the substrate. The second semiconductor chip is installed on the first semiconductor chip and is configured to integrate a power circuit to receive an external power supply and to supply an electric power to the first semiconductor chip based on the external power supply. The plastic mold seals together the first and second semiconductor chips on the substrate.10-09-2008
20080238533Semiconductor Device - A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.10-02-2008
20120062311System including adaptive power rails and related method - According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.03-15-2012
20090184751BOOSTED VOLTAGE GENERATOR FOR INCREASING BOOSTING EFFICIENCY ACCORDING TO LOAD AND DISPLAY APPARATUS INCLUDING THE SAME - A boosted voltage generator for increasing boosting efficiency according to the amount of load and display apparatus including the same are provided. The boosted voltage generator includes an input voltage generator configured to generate a first input voltage or a second input voltage based on a reference voltage, compare the reference voltage with a feedback boosted voltage fed back based on the amount of load at an output terminal, and output a comparison result; and a booster configured to boost the first or second input voltage using at least one external capacitor based on the comparison result and output a boosting result as a boosted voltage to the output terminal. The boosted voltage generator and the display apparatus including the same can increase the boosting efficiency according to the amount of load.07-23-2009
20090184752BIAS CIRCUIT - A bias circuit includes a first and a second transistors to which a common gate voltage is supplied, a load circuit coupled to drains of the first and the second transistors, a control circuit generating a control signal based on a signal from the load circuit, a current source controlled based on the control signal and coupled to the first and the second transistors, and a first impedance circuit coupled between the second transistor and the current source.07-23-2009
20090231021Semiconductor Device - An element is protected without hampering an actual operation in the case where overvoltage that might damage the element is applied. A semiconductor device includes a first potential supply terminal 09-17-2009
20090128227HIGH VOLTAGE GENERATING DEVICE OF SEMICONDUCTOR DEVICE - A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and performs a pumping operation in response to the first enable signal and a first clock signal to generate the first high voltage. The second high voltage pump unit compares a second high voltage and a second reference voltage to generate a second enable signal, and performs a pumping operation in response to the second enable signal and a second clock signal to generate the second high voltage. The clock signal generating unit generates the first clock signal or the second clock signal in response to the first enable signal and the second enable signal when at least one of the first enable signal and the second enable signal is enabled.05-21-2009
20100148855Constant Reference Cell Current Generator For Non-Volatile Memories - A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (I06-17-2010
20100225382APPARATUS FOR CONTROLLING SUBSTRATE VOLTAGE OF SEMICONDUCTOR DEVICE - A semiconductor integrated circuit apparatus includes an internal circuit having a MIS transistors on a semiconductor substrate and a substrate voltage control block that supplies a substrate voltage to the internal circuit and controls threshold voltages for the MIS transistors of the internal circuit. The apparatus also includes a leakage current detection MIS transistor and a leakage current detection circuit. The substrate voltage control block generates a substrate voltage based on comparison results of the comparator and applies the generated substrate voltage to the substrate of the leakage current detection MIS transistor and the substrate of the MIS transistors of the internal circuit. The substrate voltage control block includes a switch arranged between first and second input terminals of a comparator and a drain of the leakage current detection MIS transistor and a reference potential terminal, as well as an input data corrector that carries out substrate voltage adjustment.09-09-2010
20090251202SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A control target circuit formed by transistors is provided with a power supply level control circuit for controlling the power supply voltage supplied to the control target circuit, a substrate level control circuit for controlling the substrate voltages of the transistors, and a special substrate level control circuit for controlling the substrate voltages during transition of the power supply voltage through a different system. During transition of the power supply voltage, the special substrate level control circuit positively controls the substrate voltages such that desired substrate voltage levels are reached earlier, whereby the time for the substrate voltages to transfer to the desired substrate voltage levels is shortened. To suppress latch-up and breakdown voltage degradation, the special substrate level control circuit controls supply of voltages and currents so as to comply with the potential difference conditions defined between the power supply voltage and the substrate voltages.10-08-2009
20100164606DC BIASING CIRCUIT FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR - A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.07-01-2010
20110109374DYING GASP CHARGE CONTROLLER - In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.05-12-2011
20100039166CIRCUIT FOR GENERATING NEGATIVE VOLTAGE AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating negative voltage includes a variable period oscillator configured to generate an oscillator signal enabled in response to a detection signal and to determine a period of the oscillator signal in response to a control signal, a pump configured to perform pumping operations in response to the oscillator signal and to generate a negative voltage by the pumping operations, a negative voltage detecting unit configured to detect the level of the negative voltage to generate the detection signal, and a gate-induced drain leakage current detecting unit configured to measure the amount of a gate-induced drain leakage current to generate the control signal.02-18-2010
20090322412SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE - Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.12-31-2009
20100039165CURRENT CONTROLLER AND METHOD THEREFOR - In one embodiment, a current controller is configured to control a value of the current without regulating a voltage formed by the controller.02-18-2010
20100066439SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT - A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.03-18-2010
20100066438Biasing a Transistor Out of a Supply Voltage Range - The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.03-18-2010
20110068855Semiconductor integrated circuit device and method for controlling power supply voltage - The present invention is a semiconductor integrated circuit device including a target circuit, a voltage supply circuit that supplies the power supply voltage to the target circuit, a control circuit that controls an output voltage of the voltage supply circuit, and a target voltage prediction circuit that predicts a voltage value of the power supply voltage. The control circuit changes the output voltage of the voltage supply circuit by a predetermined voltage value. The target voltage prediction circuit detects a change amount of an operating frequency of the target circuit along with the change of the predetermined voltage value, and calculates a target voltage value based on a relation between the change amount of the operating frequency and the predetermined voltage value. The voltage supply circuit supplies a power supply voltage corresponding to the target voltage value to the target circuit.03-24-2011
20080309398MULTIPLIER CIRCUIT - A multiplier circuit includes a bias circuit which outputs a reference voltage and a bias signal, a first delay circuit which inputs a input signal and outputs a first delayed signal according to the reference voltage and the bias signal, a second delay circuit which inputs an inversed input signal and outputs a second delay signal according to the reference voltage and the bias signal and an OR circuit which outputs a OR logic result generated with the first and second delayed signals.12-18-2008
20100176871SIGNAL RECEIVER AND VOLTAGE COMPENSATION METHOD THEREOF - A signal receiver includes a first-stage circuit, a second-stage circuit, a current compensation circuit, and a biasing circuit. A first input end of the first-stage circuit receives a reference voltage, and a second end of the first-stage circuit receives an input signal. A first input end and a second input end of the second-stage circuit are respectively coupled to a first output end and a second output end of the first-stage circuit. The current compensation circuit is coupled to the first input end of the second-stage circuit for dynamically providing a compensation current to the first input end of the second-stage circuit in response to a biasing voltage, so as to stabilize its voltage level. The biasing circuit biases the first-stage circuit and the current compensation circuit and sets the biasing voltage of the current compensation circuit in response to the reference voltage.07-15-2010
20100060342METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.03-11-2010
20100194468SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, COMMUNICATION DEVICE, INFORMATION REPRODUCING DEVICE, IMAGE DISPLAY DEVICE, ELECTRONIC DEVICE, ELECTRONIC CONTROL DEVICE, AND MOBILE BODY - In order to suppress an instantaneous carrying current (surge current) and power supply noise caused by the instantaneous carrying current (the surge current), the power supply cutoff structure of a semiconductor integrated circuit device comprises a switching circuit for controlling a power supply to a controlled circuit. The switching circuit includes a plurality of transistors each having a different current capability. The transistors are sequentially provided with a certain regularity, including from a low current capability transistor up to a high current capability transistor.08-05-2010
20110025408SWITCHES WITH BIAS RESISTORS FOR EVEN VOLTAGE DISTRIBUTION - Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.02-03-2011
20090174465SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a boost circuit configured to boost a power supply voltage so as to generate first and second voltages, the second voltage being lower than the first voltage, a load circuit supplied with the first voltage, and a capacitor. The capacitor has first and second diffusion regions, a first insulating film formed on a channel region, a first electrode formed on the first insulating film, a second insulating film formed on the first electrode, and a second electrode formed on the second insulating film. The second voltage is applied to the first electrode. The first voltage is applied to the second electrode. The power supply voltage is applied to at least one of the first and second diffusion regions.07-09-2009
20120146714APPARATUS AND METHOD FOR ADJUSTABLE BACK BIAS CONTROL OF AN INTEGRATED CIRCUIT - An apparatus for dynamically varying a bias voltage that is applied to a substrate of an integrated circuit. The apparatus includes an adaptive bias generator, a state processor, and a fuse array. The adaptive bias generator is disposed on the integrated circuit, and is configured to generate a variable bias voltage according to a value received over a bias bus, where the variable bias voltage is applied to the substrate. The state processor is coupled to the adaptive bias generator, and is configured to receive one or more power management states, and is configured to provide the value over the bias bus, where the value is a function of the one or more power management states. The fuse array is operatively coupled to the state processor, and is configured to control one or more weighting values, where the weighting values are employed by the function to provide the value.06-14-2012
20120007661APPARATUS AND METHOD FOR DETERMINING DYNAMIC VOLTAGE SCALING MODE, AND APPARATUS AND METHOD FOR DETECTING PUMPING VOLTAGE USING THE SAME - A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal.01-12-2012
20120007662HIGH VOLTAGE CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE - A high voltage control circuit of a semiconductor device includes an output node control circuit configured to set an initial potential of an output terminal or to discharge the potential of the output terminal, in response to an input signal and a high voltage supply circuit comprising an acceleration unit and a potential control unit coupled in series between the output terminal and a supply terminal for supplying a high voltage. The acceleration unit is operated in response to the potential of the output terminal, and the potential control unit is operated in response to the input signal.01-12-2012
20120313692SUPER-HIGH-VOLTAGE RESISTOR ON SILICON - An integrated circuit (IC) including a first layer of a conducting material; a second layer of an insulating material, where the second layer has a first side arranged adjacent to the first layer, and a second side; and a substrate arranged adjacent to the second side of the second layer. A first well arranged in the substrate. The first well is adjacent to the second side of the second layer. The substrate and the first well have opposite doping.12-13-2012
20120212285PRECISE CONTROL COMPONENT FOR A SUBSTARATE POTENTIAL REGULATION CIRCUIT - A control circuit for substrate potential regulation for an integrated circuit device. The control circuit includes a current source configured to generate a reference current. A variable resistor is coupled to the current source. The variable resistor is configured to receive the reference current and generate a reference voltage at a node between the current source and the variable resistor. The reference voltage controls the operation of a substrate potential regulation circuit coupled to the node.08-23-2012
20090058505VOLTAGE CONVERTING CIRCUIT AND BATTERY DEVICE - A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element is increased as the potential of the selected power storage device is increased when a power storage device is selected from a plurality of power storage devices that are connected in series. A certain drive voltage for turning on p-type MOS transistors Q03-05-2009
20120313693SEMICONDUCTOR DEVICE, METHOD AND SYSTEM WITH LOGIC GATE REGION RECEIVING CLOCK SIGNAL AND BODY BIAS VOLTAGE BY ENABLE SIGNAL - A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.12-13-2012
20120081174SWITCHED CURRENT MIRROR WITH GOOD MATCHING - A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.04-05-2012
20100148854COMPARATOR WITH REDUCED POWER CONSUMPTION - A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.06-17-2010
20130015911SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIPAANM Cranford, JR.; Hayden C.AACI CaryAAST NCAACO USAAGP Cranford, JR.; Hayden C. Cary NC USAANM Hook; Terence B.AACI JerichoAAST VTAACO USAAGP Hook; Terence B. Jericho VT US - Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.01-17-2013
20130113545METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (05-09-2013
20130200942SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES - A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.08-08-2013
20080278220HIGH-LINEARITY LOW NOISE AMPLIFIER AND METHOD - Embodiments of a high-linearity low-noise amplifier (LNA) and method are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier and a common-gate stage. The common-gate stage is dynamically biased based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage.11-13-2008
20100315153APPARATUS AND ASSOCIATED METHODS IN RELATION TO CARBON NANOTUBE NETWORKS - In one or more embodiments described herein, there is provided an apparatus comprising a substrate, and a plurality of carbon nanotubes (semiconducting nano-elements) disposed and fixed with said substrate. The nanotubes are disposed and fixed on said substrate such that they define a carbon nanotube network substantially at the percolation threshold of the network. As the network is at the percolation threshold, this provides for one or more signal paths extending from an input region to an output region. The apparatus is configured to, upon receiving particular input signalling via the input region, provide particular predefined output signalling at the output via the one or more signal paths, the particular output signalling being predefined according to the one or more one signal paths.12-16-2010
20120286852CHARGE-DISCHARGE DEVICE - A charge-discharge device has a current generating circuit, a charging circuit, a discharging circuit, and a signal processing circuit. The current generating circuit has a first transistor and a second transistor for generating a reference current. The charging circuit has a third transistor, coupled with the first transistor, for providing a charging current to a load according to the reference current. The discharging circuit has a fourth transistor, coupled with the second transistor, for providing a discharging current to the load according to the reference current. The signal processing circuit has a first input end coupled with the first and the second transistors, a second input end for coupling with the load, and an output end coupled with the first and the third transistors. The signal processing circuit amplifies the difference signal between the first end and the second input end to adjust the charging current and/or the discharging current.11-15-2012
20120001681LIGHT EMITTING DEVICE WITH ENCAPSULATED REACH-THROUGH REGION - A light emitting device (01-05-2012

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