Class / Patent application number | Description | Number of patent applications / Date published |
327526000 | Redundant | 13 |
20090091374 | ELECTRONIC DEVICE FOR COMMUTATION OF ELECTRIC LOAD CONTROLLED BY A MICROCONTROLLER - An electronic device and method for commuting an electric load, including an electronic commutator controlled by a microcontroller, positively supplied at a voltage, with an outlet that may adopt at least three states and operating in a nominal mode that may be switched intentionally or by default to a failsafe mode in case of malfunction of the electronic commutation device. The electronic commutation device additionally includes a positive commuted supply greater than the voltage and connected to the microcontroller of the electronic commutation device by a resistive polarization device to carry out the function of safety barrier, and an interface device for recognizing the presence or absence of the positive commuted supply. | 04-09-2009 |
20090315614 | DIVERSITY SIGNAL PROCESSING SYSTEM AND A PRODUCING METHOD THEREOF - Each of APRM units equipped for each of the diversity channels has printed circuit boards having circuit patterns thereon and a circuit description elements installed on the printed circuit board. The circuit description elements are FPGA elements manufactured by mutually different providers for example and implemented an electric circuit described in a hardware description language by a configuration tool. The circuit description elements can be implemented mutually different descriptions of the electric circuit, or can be implemented the electric circuit by mutually different configuration tools. Also, the printed circuit boards for the diversity channels can be different from each other. | 12-24-2009 |
20090322411 | CIRCUIT AND METHOD FOR AVOIDING SOFT ERRORS IN STORAGE DEVICES - A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement. | 12-31-2009 |
20100127758 | APPARATUS FOR BYPASSING FAULTY CONNECTIONS - Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors. | 05-27-2010 |
20100134176 | ELECTRONIC DEVICE INCLUDING CIRCUITRY COMPRISING OPEN FAILURE-SUSCEPTIBLE COMPONENTS, AND OPEN FAILURE-ACTUATED ANTI-FUSE PATHWAY - An electronic device including series-connected open failure-susceptible components and re-routing assemblies for directing current through an ancillary current path to maintain operability of the series array despite an open-failed component therein. The re-routing assembly can be constituted as an ancillary circuit containing a bypass control element arranged to maintain the ancillary circuit in a non-current flow condition when none of the open failure-susceptible components has experienced open failure, and to re-route current from a main circuit around an open-failed component therein and through the ancillary circuit and back to the main circuit, to bypass the open-failed component so that all non-failed series components of the main circuit remain operative when electrically energized. | 06-03-2010 |
20110234304 | On-Chip Redundancy High-Reliable System and Method of Controlling the Same - The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure. | 09-29-2011 |
20110241763 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison. | 10-06-2011 |
20110241764 | REDUNDANCY CIRCUITS - In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal. | 10-06-2011 |
20110267137 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result. | 11-03-2011 |
20120086501 | REDUNDANCY CIRCUIT - A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array. | 04-12-2012 |
20120218030 | METHOD FOR MANAGING CIRCUIT RELIABILITY - Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components. | 08-30-2012 |
20130009694 | METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL - An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of μbumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the μbumps as a faulty μbump, and store a first value that corresponds with the identified faulty μbump in the first memory. | 01-10-2013 |
20140159803 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. | 06-12-2014 |