Class / Patent application number | Description | Number of patent applications / Date published |
327357000 | Quadrant | 12 |
20080252355 | Super-Symmetric Multiplier - A circuit includes a multi-tanh cell having a common-emitter node to receive a bias current, and an extra transistor coupled to the common-emitter node to dynamically divert a portion of the bias current from the multi-tanh cell. The circuit may be arranged as a multiplier with an input network arranged to apply two or more input signals to the multi-tanh cell. A second multi-tanh cell with an extra transistor may be arranged in a feedback loop where the outputs of the first and second multi-tanh cells are coupled together at an integrating node. A buffer drives the final output and feedback cell to cancel nonlinearities in the multiplier cells. | 10-16-2008 |
20100327940 | EMBEDDED PHASE NOISE MEASUREMENT SYSTEM - Phase noise detection systems for a device under test (DUT) are provided that can be embedded within a chip. According to one embodiment, the embedded phase noise detection system can include an active delay line cell, a phase shifter, and a phase detector. The active delay line and phase shifter separately receive the output signal of the DUT. The phase detector can include a double-balanced mixer followed by an active RC filter. The double-balanced mixer receives, as input, the outputs from the active delay line and phase shifter and can produce different dc voltages proportional to the difference from the input phase quadrature. An auto-adjustment circuit can also be included to help the input signal from the phase shifter to the mixer maintain quadrature. | 12-30-2010 |
20110121881 | MULTIPLE INPUT / GAIN STAGE GILBERT CELL MIXERS - Multiple input and/or gain stage Gilbert cell mixer designs are disclosed. The designs allow one input to be turned on at a time, and are suitable, for example, for use in receiver and transmitter applications. In addition, the designs allow for the inputs of the multi-input Gilbert cell mixer to be connected together, thereby allowing for switching of gain states within the Gilbert cell mixer. The mixer design may include, for example, a Gilbert cell mixer stage, and a plurality of input/gain stages. Each input/gain stage has its output connected to the input of the mixer stage, and is configured for receiving an input signal and applying a gain factor to that input signal to provide a signal for mixing with the LO. Each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, so that only one input/gain stage is active at a time. | 05-26-2011 |
20120081169 | Mixer Divider Layout - A symmetrical, balanced, down-conversion mixer is achieved by the coordinated layout of a balanced Local Oscillator (LO) divider circuit and a balanced Radio Frequency (RF) mixer circuit, such that the LO divider is in the center and the RF mixer is arrayed symmetrically around the LO divider. In particular, the LO divider is partitioned into four portions (e.g., Ip, In, Qp, Qn), which are placed in respective quadrants, defined by orthogonal reference axes through the LO divider center. The RF mixer is similarly partitioned into four corresponding portions, which are placed around the LO divider portions in each quadrant. By integrating the LO divider and RF mixer in the layout of the symmetric, balanced, down-conversion mixer, greater component matching and control of current paths are possible, improving operational quality parameters such as IRR, IP | 04-05-2012 |
20120299633 | FREQUENCY UP AND DOWN CONVERTER - A frequency up and down converter, in which, when down converting a high frequency signal into an intermediate frequency signal or up converting an intermediate frequency signal into a high frequency signal by controlling switching elements using a local oscillator signal, a signal with a frequency to be converted is controlled a number of times during one cycle of the local oscillator signal, whereby the local oscillator signal with a frequency lower than an original frequency may be used. Transistors are added in parallel to switching transistors disposed in a frequency down conversion unit or a frequency up conversion unit, and local oscillator signals with predetermined phases and pulse widths are provided to the gates of the transistors such that a high frequency signal or an intermediate frequency signal is transferred to an output terminal at least two times during one cycle of a local oscillator signal. | 11-29-2012 |
20130147539 | DOWN-CONVERTER, UP-CONVERTER, RECEIVER AND TRANSMITTER APPLYING THE SAME - A down-frequency conversion circuit and up-frequency conversion circuit, and a receiver and transmitter applying the same are provided. The down-frequency conversion circuit includes a harmonic mixer and general mixer, and thus becomes able to convert frequency using one LO (Local Oscillator) frequency, thereby reducing burden on generating LO frequency. | 06-13-2013 |
20130257508 | HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION - A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33 ⅓ percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the 1-0 image and even order harmonics. | 10-03-2013 |
20140152370 | Circuit and Method for Image Frequency Rejection - A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device. | 06-05-2014 |
20140152371 | HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION - One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals. | 06-05-2014 |
20140253216 | GILBERT MIXER WITH NEGATIVE GM TO INCREASE NMOS MIXER CONVERSION - A cross coupled NMOS transistors providing a negative g | 09-11-2014 |
20140347117 | IMPEDANCE TRANSFORMER FOR USE WITH A QUADRATURE PASSIVE CMOS MIXER - An impedance transformer for use with a quadrature passive mixer is disclosed. In an exemplary embodiment, an apparatus includes a mixer configured to generate an up-converted signal at a mixer output port in response to local oscillator (LO) signals, and an impedance transformer configured to provide a complex impedance at the mixer output port. The complex impedance configured to generate a selected level of the reverse isolation for the mixer thereby generating a selected amplitude flatness symmetry characteristic for the up-converted signal. | 11-27-2014 |
20160117527 | COMPACT CMOS CURRENT-MODE ANALOG MULTIFUNCTION CIRCUIT - The compact CMOS current-mode analog multifunction circuit is based on an implementation using MOSFETs operating in a sub-threshold region and forming two overlapping translinear loops capable of performing multiplication, division, controllable gain current amplifier, current mode differential amplifier, and differential-input single-output current amplifier. | 04-28-2016 |