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Interstage coupling (e.g., level shift, etc.)

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327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327306000 - Amplitude control

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DocumentTitleDate
20130043926LEVEL SHIFT CIRCUIT - In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node W02-21-2013
20090231016GATE OXIDE PROTECTED I/O CIRCUIT - An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.09-17-2009
20130027108LEVEL SHIFT CIRCUIT - According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.01-31-2013
20130027109VOLTAGE LEVEL SHIFTER HAVING A FIRST OPERATING MODE AND A SECOND OPERATING MODE - Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode.01-31-2013
20090289685Bias voltage generation for capacitor-coupled level shifter with supply voltage tracking and compensation for input duty-cycle variation - A circuit architecture, or topology, that provides a level shifter substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled input terminals connected to the gates of the high-side transistors and circuitry to set the bias voltage at the gates of the high-side transistors, wherein the bias voltage generation circuitry receives at least information indicative of both the H-bridge power supply voltage and the modulation of the input signal. Various embodiments include a switchable element coupled in series with a voltage divider portion in the bias voltage generation circuitry. The ratio of on to off time of the switchable element determines the average current through the voltage divider and thus the bias voltage. To prevent excessive short-circuit current flow through the high-side transistors, the switchable elements are turned off responsive to detection of a short-circuit condition.11-26-2009
20100026362HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.02-04-2010
20090195292SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.08-06-2009
20090195291Level shift circuit, and driver and display system using the same - Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated.08-06-2009
20090289686VOLTAGE LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M11-26-2009
20090243696HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME - Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.10-01-2009
20110193609Voltage Level Shifter with Dynamic Circuit Structure having Discharge Delay Tracking - In a particular embodiment, an apparatus includes a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.08-11-2011
20090121771LEVEL SHIFT CIRCUIT AND METHOD THEREOF - A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.05-14-2009
20100117708Voltage Level Converter without Phase Distortion - A voltage level converter with reduced signal phase distortion is provided. The voltage level converter includes a level shifting circuit followed by a unit interval retrieval circuit. The level shifting circuit takes complementary input voltage signals and converts to signals with different voltage levels. The unit interval retrieval circuit responds to the output complementary signals from the level shifting circuit and generates one or more output signals that restore the period of the original input voltage signals with no or negligible phase distortion.05-13-2010
20090021292RELIABLE LEVEL SHIFTER OF ULTRA-HIGH VOLTAGE DEVICE USED IN LOW POWER APPLICATION - The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shifter. Embodiments of the invention provide a structure and a method for fabricating the IC wherein the level shifter is incorporated within the IC to improve reliability of the IC.01-22-2009
20130076428LEVEL CONVERTER AND PROCESSOR - A level converter includes a level conversion circuit, which is provided between a reference power supply line having a reference voltage level and a first power supply line coupled to a first power supply outputting a first voltage level, which inputs a first signal and outputs a second signal, the first signal having a first logic level and a second logic level, the second signal having a first logic level and a second logic level; a control signal generating circuit to output a control signal having the reference voltage level when a second power supply outputting the second voltage level is turned off and the first voltage level when the second power supply is turned on; and a coupling circuit to control an electrically connection between the first power supply line and an output node of the level conversion circuit based on the control signal.03-28-2013
20130082758SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.04-04-2013
20130082759LEVEL SHIFTER AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SHIFTER - A level shifter for converting an input pulse signal of low-voltage amplitude to high-voltage amplitude includes a low voltage circuit configured to generate complementary-pulse signals of low-voltage amplitude from the input pulse signal, and a high voltage circuit configured to generate a pulse signal of high-voltage amplitude based on the complementary-pulse signals. The low voltage circuit, including high-threshold voltage transistors, includes a plurality of inverter circuits connected in cascade and at least one resistive-switch circuit connected between an input and an output of at least one of the plurality of inverter circuits configured to operate as a resistor when in a conductive state.04-04-2013
20100045358LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit capable of operating at low input voltage. The level shift circuit comprises: a first switch element coupled to a first output terminal, a second switch element coupled to a second output terminal, a third switch element coupled to the second output terminal and the first output terminal, a fourth switch element coupled to the first output terminal and the second output terminal, a first current source module for letting a current passing through the third switch element smaller than a current passing through the first switch element when the first switch element and the third switch element are conducted, and a second current source module for let a current passing through the fourth switch element smaller than a current passing through the second switch element when the second switch element and the fourth switch element are conducted.02-25-2010
20130038375VOLTAGE LEVEL SHIFTER - A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter.02-14-2013
20100109744LEVEL SHIFTER HAVING A CASCODE CIRCUIT AND DYNAMIC GATE CONTROL - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS05-06-2010
20100109743LEVEL SHIFTER HAVING NATIVE TRANSISTORS - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS05-06-2010
20100109742Level shift circuit - A level shift circuit includes a first resistor with one end connected to GND, a first transistor with a drain and a gate connected to the other end of the first resistor, and a source connected to a first power supply, a second transistor with a source connected to the first power supply, and a gate connected to the drain and the gate of the first transistor, a second resistor with one end connected to a drain of the second transistor, a third transistor with a source connected to the other end of the second resistor, and a gate connected to an input terminal, a first current source connected between a second power supply and a drain of the third transistor; and a fourth transistor connected between an output terminal and the first power supply with a gate connected to the drain of the second transistor.05-06-2010
20100109745LEVEL CONVERSION CIRCUIT FOR CONVERTING VOLTAGE AMPLITUDE OF SIGNAL - In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.05-06-2010
20100026363HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.02-04-2010
20120182060NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT - A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.07-19-2012
20130069706APPARATUS AND METHODS FOR ADAPTIVE COMMON-MODE LEVEL SHIFTING - Apparatus and methods for adaptive level shifting are provided. In one embodiment, a method of level shifting in an adaptive level shifter (ALS) is provided. The technique includes charging a first capacitor and a second capacitor each to a voltage that is about equal to a difference between a common mode voltage of a differential input voltage signal and a reference voltage. The technique can further include inserting the first capacitor between a first input and a first output of the ALS and the second capacitor between the second input and a second output of the ALS. The technique can further include switching the first capacitor and the second capacitor such that the first capacitor is inserted between the second input and the second output and the second capacitor is inserted between the first input and the first output.03-21-2013
20130069707LEVEL SHIFTER CIRCUIT - An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.03-21-2013
20090302924Level shifter capable of improving current drivability - A level shifter circuit is provided that is capable of improving current drivability and executing stable operation with a low voltage by boosting a voltage level of an input signal. The level shifter circuit includes a level shifting unit for producing a boosted voltage by boosting an input signal and shifting a voltage level of the boosted voltage to output an output signal.12-10-2009
20090091368DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER - Disclosed are embodiments of a design structure for a voltage level shifter circuit that operates without forward biasing junction diodes, regardless of the sequence in which different power supplies are powered up. The circuit embodiments incorporate a pair of series connected switches (e.g., transistors) between an input terminal and a voltage adjusting circuit. Each switch is controlled by a different supply voltage from a different power supply. Only when both power supplies are powered-up and the different supply voltages are received at both switches will a first signal generated using one of the supply voltages be passed to a voltage adjusting circuit and thereafter converted into a second signal representative of the first signal, but generated using the second supply voltage. Incorporation of the pair of series connected switches into the voltage level shifter circuit prevents forward biasing of junction diodes in the circuit and thereby prevents current leakage from the power supplies.04-09-2009
20090051403Signal process circuit, level-shifter, display panel driver circuit, display device, and signal processing method - In one embodiment of the present invention, a signal process circuit in accordance with the present invention includes: a first input terminal via which an input signal is supplied; a second input terminal via which a predetermined signal is supplied; a cross-coupled inverter circuit, including first and second CMOS inverter circuits, in which an input of the first CMOS inverter circuit and an output of the second CMOS inverter circuit are interconnected to each other and an output of the first CMOS inverter circuit and an input of the second CMOS inverter circuit are interconnected to each other; a current control circuit that applies currents to the first and second CMOS inverter circuits in accordance with a timing signal, the input signal, and the predetermined signal; output terminals which are connected to the outputs of the first and second CMOS inverter circuits, respectively, and from which an output signal is supplied; and a reset circuit that resets the output signal based on the timing signal. With the arrangement, it is possible to cause a signal of a small amplitude to be level-shifted and latched at low power consumption.02-26-2009
20090085638Semiconductor Device - It is an object of the present invention to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width in a semiconductor device capable of communicating data wirelessly. In a semiconductor device, a level shift circuit is provided between a data demodulation circuit and each circuit block where demodulated signals are outputted from the data demodulation circuit. In such a manner, voltage amplitude of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, a pulse width of the demodulated signal is made almost equal to that of signals in each circuit block, or a pulse width of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, it is possible to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width.04-02-2009
20120223760LEVEL SHIFT CIRCUIT - A level shift circuit including a level shift voltage generation circuit that receives an input signal having an amplitude between a voltage of a first voltage system power supply and a ground potential and performs conversion of the amplitude of the input signal to produce an output signal voltage with an amplitude between a voltage of a second voltage system power supply and the ground potential, a replica circuit monitoring a voltage corresponding to a logic threshold of the first voltage system power supply, the replica circuit, with the logic threshold of the first voltage system power supply as an input, monitoring and outputting a voltage corresponding to a logic threshold of the second voltage system power supply, and a bias generation circuit that receives an output from the replica circuit and generates a bias.09-06-2012
20130162318DIFFERENTIAL OUTPUT CIRCUIT - A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage.06-27-2013
20130063198BUFFER CIRCUIT HAVING SWITCH CIRCUIT CAPABLE OF OUTPUTTING TWO AND MORE DIFFERENT HIGH VOLTAGE POTENTIALS - A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage.03-14-2013
20090251194DC COMMON MODE LEVEL SHIFTER - A switched-mode level-shifter shifts a differential voltage superimposed on a common-mode voltage. In the level shifter, a common-mode inductive reactor has at least two windings, and at least one of the differential voltage and the common-mode voltage are applied to at least one of the windings of the reactor. A switch charges the inductive reactor when caused to be in a first state, where the inductive reactor when charged experiences a change of flux according to the applied voltage. The switch also actuates a reset of the charged inductive reactor when caused to be in a second state, where the inductive reactor when reset reverses the change of flux experienced thereby. A source of a chopping signal is provided to alternately drive the switch between the first and second states, where each of the first and second states is one of in and out of conduction.10-08-2009
20090237139Level shifter with reduced current consumption - A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode.09-24-2009
20090027104Methods and apparatus for predictable level shifter power-up state - In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state01-29-2009
20090027103SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source V01-29-2009
20090027101LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit that can reliably cut off the path of a through current regardless of the state of supply of power to plural circuit sections that operate by different power supplies. The level shift circuit is provided with an input circuit section that operates by a power supply voltage VDD01-29-2009
20090009230Semiconductor device - A semiconductor device includes a level shift circuit to convert an input signal having an amplitude from a first power supply potential to a second power supply potential to a signal having an amplitude from the first power supply potential to a third power supply potential, a first output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the first output portion including a NMOS transistor, and a second output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the second output portion including a PMOS transistor.01-08-2009
20090009229HIGH/LOW VOLTAGE TOLERANT INTERFACE CIRCUIT AND CRYSTAL OSCILLATOR CIRCUIT - A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.01-08-2009
20120235728Level Shifter Design - A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V09-20-2012
20110025399AMPLITUDE CONVERSION CIRCUIT - In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal.02-03-2011
20100033224Level Shifter, Standard Cell, System And Method For Level Shifting - Implementations are presented herein that include a level shifter circuit.02-11-2010
20090033400VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT - Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.02-05-2009
20090033401Level Shifting Circuit With Symmetrical Topology - A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed.02-05-2009
20100123505ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.05-20-2010
20120032724CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.02-09-2012
20120001673LOW POWER FAST LEVEL SHIFTER - A lever shifter is provided for receiving a signal in a first voltage domain and providing an output signal in a second voltage domain. The level shifter reduces propagation delay and power consumption by mitigating contention between NFETs and PFETs during signal propagation.01-05-2012
20110285448SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region.11-24-2011
20110298519LEVEL SHIFTER - The present invention provides a level shifter. In an embodiment, the level shifter includes first to sixth transistors. The first and second transistors have common control nodes coupled to a first bias voltage, receive a pair of input signals and respectively provide a first output node and a second output node. The fifth and sixth transistors have common control nodes coupled to a second bias voltage to form a current mirror. The third transistor is coupled between the first and the fifth transistors and has a control node coupled to the second output node. The fourth transistor is couple between the second and the sixth transistors and has a control node coupled to the first output node.12-08-2011
20120098584CIRCUIT AND METHOD FOR IMPROVEMENT OF A LEVEL SHIFTER - A current limiter is connected between a voltage source and the level shifting latch of a level shifter for limiting the driving current for the level shifting latch under a threshold, to thereby reduce the current consumption of the level shifter during logic transition, by which the level shifting latch can be implemented by transistors with shorter channels, thereby downsizing the circuit area of the level shifter. Preferably, the threshold is adjustable for adjusting the output driving capability of the level shifter and speeding up logic transition of the level shifter.04-26-2012
20090066398Voltage Level Shifter Circuit - A voltage level shifter circuit is provided. A high power voltage is input to a first power voltage terminal, an enable signal is input to an enable terminal, and an intermediate voltage level between the first power voltage and a high enable signal voltage is input to a second power voltage terminal. First and second inverters are connected to the enable terminal. A first transistor has a source connected to the second inverter. A second transistor has a drain connected to a drain of the first transistor, a source connected to the second power voltage terminal, and a gate connected to an output terminal of the first inverter. Third and fourth transistors have gates connected to the outputs of the first and second transistors, the fourth transistor having a source connected to the first power voltage terminal.03-12-2009
20100264977Cascoded level shifter protection - A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed. The cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range, the cascoded level shifter comprising: an input node configured to receive an input signal; a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device comprising a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal; and reference voltage perturbation circuitry, configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.10-21-2010
20100264976Circuitry for processing signals from a higher voltage domain using devices designed to operate in a lower voltage domain - An apparatus is disclosed for receiving input signals in a first higher voltage domain and for generating and outputting signals in a second lower voltage domain, said apparatus comprising: an input pad for receiving said input signals in said first higher voltage domain; output circuitry comprising a plurality of devices arranged between a high voltage source of said second lower voltage domain and a low voltage source, said plurality of devices being arranged in a first set and a second set, said first set being arranged between said high voltage source and said output and said second set being arranged between said output and said low voltage source, said output circuitry being configured to switch to output a first predetermined value in response to a rising input signal exceeding an upper threshold value and to switch to output a second predetermined value in response to a falling input signal falling below a lower threshold value; a first input path for sending said received input signals to a first input of said first set; a second input path for sending said received input signals to a second input of said second set; wherein said second input path comprises a switch delay device for reducing a voltage of said received input signal such that on a rising input signal, said input signal has reached a higher value when said output circuitry switches in response to said input signal than it would have reached had said input signal voltage not been reduced; and a controllable connecting path between said first and second inputs for connecting said first and second inputs together in response to detection of said first predetermined value at said output and for not connecting said first and second inputs together in response to detection of said second predetermined value at said output.10-21-2010
20130214843BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE - A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.08-22-2013
20100033226Level shifter with output spike reduction - A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.02-11-2010
20100033225Gate Driving Circuit - A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.02-11-2010
20090002050Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a diode, an inductor, a first capacitor, and a boost circuit. The boost circuit includes a level shifter, a third transistor, and a second capacitor. Whether the third transistor 01-01-2009
20090189669METHODS AND APPARATUS TO REDUCE PROPAGATION DELAY OF CIRCUITS - Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off.07-30-2009
20090189670LEVEL SHIFTER WITH REDUCED POWER CONSUMPTION AND LOW PROPAGATION DELAY - A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.07-30-2009
20090153218LEVEL SHIFT CIRCUIT WITH POWER SEQUENCE CONTROL - A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled.06-18-2009
20090153220SOURCE DRIVER AND POWER DOWN DETECTOR THEREOF - The present invention discloses a source driver powered by a power supply comprising at least one channel, at least one output pad coupled to the channel, at least one switch connected between the output pad and a predetermined voltage, and a power down detector for detecting whether a first supply voltage from the power supply is insufficient and generating a reset signal to turn on the switch if yes.06-18-2009
20090153219Replica bias circuit for high speed low voltage common mode driver - A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage.06-18-2009
20090015313Level Shift Circuit and Semiconductor Integrated Circuit Including the Same - In a level shift circuit, including two Nch transistors Tn01-15-2009
20080315938DRIVING CIRCUIT FOR SWITCHING ELEMENTS - A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state.12-25-2008
20080265970VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME - A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.10-30-2008
20110074486METHOD AND APPARATUS FOR TRACKING POWER SUPPLIES - A method for tracking power supplies includes the following steps: receiving, by a controller, a signal to be tracked and outputting, according to the signal to be tracked, a control signal. The control signal controls at least two sets of voltage level selection circuits in selecting at least one tracking voltage level from at least two groups of isolation voltage levels and controls each set of the voltage level selection circuits selecting at most one tracking voltage level from a group of isolation voltage levels. An isolation power supply provides the at least two groups of isolation voltage levels according to the voltage level interval of the signal to be tracked. Each group of isolation voltage levels includes at least two tracking voltage levels. The voltage level selection circuits provide the selected tracking voltage level to supply power to a load circuit. An apparatus for tracking power supplies is also provided. The present disclosure is applicable to the power supply tracking on a reference signal.03-31-2011
20130033299APPARATUS FOR INTERFACING CIRCUIT DOMAINS - An interface circuit for controlling a cross-domain signal link between a first circuit domain and a second circuit domain in a circuit may include first and second controllers, each of the first and second controllers including a first input coupled to a first voltage source of the first circuit domain and a second input coupled to a second voltage source of the second circuit domain. The interface circuit may further include a first switch controlled by an output of the first controller, the first switch including a first end coupled to the cross-domain signal link and a second end coupled to a first defined voltage state, and a second switch controlled by an output of the second controller, the second switch including a first end coupled to the cross-domain signal link and a second end coupled to a second defined voltage state, in which during a power-up of the circuit, if one of the first and second voltage sources is unavailable, at least one of the first and second controllers generates a control signal to engage at least one of the first and second switches and pull the cross-domain signal link to one of the first and second defined voltage states, while providing cross-domain protection against field-induced charge device model (FICDM) stress conditions at small drivers and receiver inputs connected to the signal interface link.02-07-2013
20110063012CIRCUIT ARRANGEMENT - A circuit arrangement is provided. The circuit arrangement includes a first transistor, a second transistor, a third transistor, and a fourth transistor respectively comprising a first terminal, a second terminal, and a control terminal, a first capacitor and a second capacitor respectively comprising a first terminal and a second terminal, an inverter comprising an input terminal and an output terminal, and a circuit arrangement input terminal and a first circuit arrangement output terminal, wherein the first terminals of the first transistor, the second transistor and the third transistor are connected with each other, wherein the second terminal of the first transistor is connected to the control terminal of the second transistor and to the first terminal of the first capacitor, and wherein the second terminal of the second transistor is connected to the control terminal of the first transistor, to the control terminal of the third transistor, and to the first terminal of the second capacitor, wherein the second terminal of the first capacitor is connected to the input terminal of the inverter, and wherein the second terminal of the second capacitor is connected to the output terminal of the inverter, wherein the output terminal of the inverter is connected to the control terminal of the fourth transistor, wherein the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, wherein the circuit arrangement input terminal is connected to the input terminal of the inverter, wherein the first circuit arrangement output terminal is connected between the second terminal of the third transistor and the first terminal of the fourth transistor.03-17-2011
20100079186Adaptive Drive Signal Adjustment for Bridge EMI Control - An embodiment of the invention relates to a driver adapted to provide a drive signal with an adjustable waveform for an external bridge to control EMI. The driver includes a detector configured to measure a switching characteristic of a switch in the external bridge to produce the drive signal with an adjustable waveform characteristic. The driver includes an adjustable circuit element to adjust the waveform characteristic in response to the measured switching characteristic. The measured switching characteristic may be a derivative of a voltage of the switch in the bridge such as a derivative of a drain-to-source voltage of a half-bridge circuit. The driver may be formed with an amplifier with an adjustable gain controlled by the signal produced by the detector. The adjustable gain amplifier may be formed with a transistor coupled in series with a leg of a current mirror.04-01-2010
20110169544SOURCE DRIVER - A source driver, which has a first resistor string, a first digital-to-analog converter, and a channel buffer, is provided. The first resistor string has a plurality of resistors connected in series, wherein each of the resistors of the first resistor string provides a corresponding gamma voltage. The first digital-to-analog converter is coupled to the resistors of the first resistor string. The digital-to-analog converter selectively outputs one of gamma voltages provided by the resistors as a first output voltage according to a data code. The channel buffer is coupled to an output terminal of the first digital-to-analog converter to output a second output voltage by shifting a voltage level of the first output voltage.07-14-2011
20090243694VOLTAGE CONVERTING DRIVER APPARATUS - A voltage converting apparatus is provided that includes a dynamic driver circuit and a voltage converting circuit. The dynamic driver circuit may receive a clock signal and input signals and provide a dynamic signal based on the clock signal and the input signals. The voltage converting circuit may receive the dynamic signal from the dynamic driver circuit and provide an output signal based on the received dynamic signal. The dynamic driver circuit may be powered by a first voltage source and the voltage converting circuit may be powered by a second voltage source.10-01-2009
20100123506MULTISTAGE LEVEL TRANSLATOR - Multistage signal amplification, including level translation, improves signal integrity, e.g., slew rate, complementary signal delay and duty cycle performance, by mirroring complementary output current in an output stage based on a signal developed in an input stage pull-up network. A multistage amplifier may comprise a first stage comprising a differential input circuit coupled, respectively, between first and second inputs and first and second nodes, wherein the first node is coupled to a first pull-up circuit controlled by the first node and the second node is coupled to a second pull-up circuit controlled by the second node; and a second stage comprising a complementary output circuit coupled, respectively, between first and second nodes and first and second outputs, wherein a current mirror sinks essentially the same current at the first output as is sourced at the second output and vice versa. The pull-up network may further comprise a cross-coupled pull-up circuit.05-20-2010
20090115487Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.05-07-2009
20100264975Level Shifter with Rise/Fall Delay Matching - In one embodiment, a level shifter circuit is provided that may include approximately matched rising edge and falling edge delays through the level shifter. The level shifter may also have a low delay and low power consumption. The level shifter circuit may include a pair of low voltage input inverters coupled to a pulldown transistor, where a node between the low voltage input inverters is coupled through another pulldown stack to a pullup transistor. Including an output inverter, both rising transitions and falling transitions may include about 4 gate delays in one embodiment. The level shifter may include keeper transistors to turn off the pullup transistor after the pullup is performed, and the pulldown transistor may be turned off as the pullup transistor is turned on. The pullup and pulldown transistors may not drive against each other during operation, which may reduce power consumption in the circuit.10-21-2010
20090278587LEVEL SHIFT CIRCUIT - A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 11-12-2009
20120194255MULTIVOLTAGE CLOCK SYNCHRONIZATION - A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.08-02-2012
20100271104IMAGE SIGNAL INPUT CIRCUIT - An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor.10-28-2010
20090295452BOOSTING CIRCUIT - A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented.12-03-2009
20090295451Systems and Methods of Digital Isolation with AC/DC Channel Merging - Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.12-03-2009
20090102537METHOD OF FORMING A SIGNAL LEVEL TRANSLATOR AND STRUCTURE THEREFOR - In one embodiment, a first portion (04-23-2009
20090261885POWER-ON DETECTING CIRCUIT AND LEVEL CONVERTING CIRCUIT - When a low supply potential has risen while a high supply potential has not risen, a logical value “0” is output as an output signal by applying a ground potential to an input terminal of a latch circuit through a capacitor. On the other hand, when the high supply potential has risen while the low supply potential has not risen, a logical value “0” is output as an output signal by converting the high supply potential into the ground potential by the level shifter. If both the low supply potential and the high supply potential have risen, the logical value “1” is output as an output signal by converting the ground potential into the high supply potential by the level shifter.10-22-2009
20090261884Level shifter using coupling phenomenon - A level shifter removes delay, which is generated at the time of transition of an input signal level, by adjusting a size of NMOS transistors to perform pull-down and pull-up operations. The level shifter includes a coupling unit for setting up a voltage level of a first node according to a voltage level of an input signal, a first buffer for transferring an output signal by buffering a signal from the first node, and a driving unit configured to receive the input signal and the output signal and drive the first node.10-22-2009
20100060337POWER SUPPLY INSENSITIVE VOLTAGE LEVEL TRANSLATOR - A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.03-11-2010
20080246529MULTI-CHANNEL SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal.10-09-2008
20080238522METHOD FOR INCORPORATING TRANSISTOR SNAP-BACK PROTECTION IN A LEVEL SHIFTER CIRCUIT - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.10-02-2008
20080238524LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the present invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between the level shifter and the buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.10-02-2008
20080238523LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.10-02-2008
20100127752LEVEL SHIFTER WITH LOW VOLTAGE DEVICES - A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs.05-27-2010
20090167405Reduced Leakage Voltage Level Shifting Circuit - A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.07-02-2009
20100201427Level Shifter Circuits For Integrated Circuits - A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption.08-12-2010
20120293231Semiconductor Device - An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied.11-22-2012
20080284486INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE - An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal.11-20-2008
20100201426LEVEL SHIFTER CIRCUIT - A level shifter circuit converts a signal generated by an internal circuit which operates with a first power supply, into a signal by a second power supply having voltage higher than that of the first power supply. The voltages at substrate terminals of two NMOS transistors, to which complementary two signals by the first power supply are input, is boosted to voltage higher than circuit ground potential in a period in which a voltage level of one of the two input signals and a voltage level of an output signal by the second power supply do not coincide with each other.08-12-2010
20080309395Systems and Methods for Level Shifting using AC Coupling - Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.12-18-2008
20080265971Voltage level shift circuits - A voltage level shift circuit has a plurality of input voltage sources, a reference voltage source, a voltage level shift unit, a stabilizing unit, a first output voltage terminal, and a second output voltage terminal. The input voltage sources provide a plurality of input voltages. The reference voltage source provides a reference voltage. The voltage level shift unit raises the input voltages to a level of the reference voltage. The stabilizing unit prevents power leakage and resulting abnormal voltage levels in the voltage level shift unit. The first output voltage terminal provides a first output voltage. The second output voltage terminal provides a second output voltage inverse to the first output voltage.10-30-2008
20080246530LEVEL SHIFTER - The present invention provides a level shifter that prevents through currents thereat. In the level shifter, a holding circuit is provided which comprises an inverter made up of transistors connected between an internal node and a ground potential and an inverter made up of transistors connected between an internal node and the ground potential. These inverters are connected in loop form thereby to hold signals of nodes. Thus, even when input signals complementary to each other originally are both brought to a level “L”, the signals of the nodes are held at the immediately preceding level, thus making it possible to prevent through currents from flowing through the transistors respectively.10-09-2008
20110204953LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.08-25-2011
20120139607VOLTAGE LEVEL SHIFTER - Provided is a voltage level shifter changing an input voltage level and outputting the input voltage. There is provided the voltage level shifter, including: an operational amplifier having a first input having an applied input voltage thereto; a first MOSFET having a gate connected to an output of the operational amplifier, a source having an applied power thereto, and a drain outputting an output voltage; a voltage dividing resistor unit including a plurality of voltage dividing resistors sequentially connected to the drain of the first MOSFET in series, one connection node between the plurality of voltage dividing resistors being connected to the second input of the operational amplifier; and a second MOSFET having a source and a drain, respectively connected to both ends of at least one of the voltage dividing resistors, and a gate connected to the gate of the first MOSFET.06-07-2012
20080315937APPARATUS FOR GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage.12-25-2008
20080303578BOOST CIRCUIT AND LEVEL SHIFTER - A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.12-11-2008
20080265972OUTPUT CIRCUIT AND MULTI-OUTPUT CIRCUIT - An output circuit includes a high-side transistor, a low-side transistor, a gate protection circuit, a level shift circuit, and a pre-driver circuit. The level shift circuit interrupts a current path from an output terminal to the level shift circuit after a predetermined time has passed since the high-side transistor was switched OFF.10-30-2008
20110006828DIFFERENTIAL TYPE LEVEL SHIFTER - This patent discloses a differential type level shifter, comprising: a differential pair of transistors, having a pair of gate terminals, a pair of drain terminals and a common source terminal, with the pair of gate terminals coupled to a first clock signal and a second clock signal; a current source, coupled between the common source terminal and a reference ground, used to provide a bias current; and a pair of loading resistors, having a common end and a pair of output ends, with the common end coupled to a power line, the pair of output ends coupled to the pair of drain terminals; wherein the pair of drain terminals are used to generate a set signal and a reset signal in response to the first clock signal and the second clock signal.01-13-2011
20090108903LEVEL SHIFTER DEVICE - A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter.04-30-2009
20080246528Level shift device - The level shift device of the present invention comprises: a level shift circuit which converts a voltage level of a single input signal; and a duty correcting circuit which offsets a difference in the duty of an output signal of the level shift circuit with respect to the duty of the input signal.10-09-2008
20110204954Voltage Level Shifter - A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.08-25-2011
20090160523Receiving Higher-Swing Input Signals When Components Of An Integrated Circuit Are Fabricated Using A Lower-Voltage Process - An aspect of the present invention provides an input block which can receive input signals of a higher voltage swing when the internal components are fabricated using a lower voltage process. In an embodiment, the input block is designed to prevent current flow into an input signal path when the input signal is at a logic low level. In another embodiment, the input block is designed to recognize a logic value corresponding to a logic high level of input signals at a higher voltage level during a transition from logic low to logic high.06-25-2009
20100141324Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof - An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.06-10-2010
20090160525LEVEL SHIFT CIRCUIT - An amplifier including the transistors of a first set operates by a power source VCC06-25-2009
20090128215LEVEL SHIFTER, INTERFACE DRIVING CIRCUIT AND IMAGE DISPLAYING SYSTEM - The present invention relates to a level shifter for receiving a control signal to produce a driving voltage, comprising: a storage capacitor, one end of the storage capacitor coupled to the control signal and a reference voltage, another end of the storage capacitor coupled to the driving voltage and a assisting voltage; and a set of selecting switches for selecting one of the driving voltage and the assisting voltage to two ends of the storage capacitor, so that the storage capacitor is capable of boosting the voltage level of the control signal while the two ends of the storage capacitor coupled to the control signal and the driving voltage. The present invention further provides an interface driving circuit and an image displaying system.05-21-2009
20120068756Two-Terminal M2LC Subsystem and M2LC System Including Same - A two-level two-terminal modular multilevel converter subsystem. The subsystem includes a first capacitor and a second capacitor. The modular multilevel converter subsystem is configured to selectively place the first capacitor in series with the second capacitor. The modular multilevel converter subsystem is also configured to selectively place the first capacitor in parallel with the second capacitor relative to first and second output terminals of the modular multilevel converter subsystem.03-22-2012
20090002052SEMICONDUCTOR DEVICE - A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply.01-01-2009
20090027100LEVEL SHIFTER AND FLAT PANEL DISPLAY USING THE SAME - A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected.01-29-2009
20090251193LEVEL SHIFTER AND CIRCUIT USING THE SAME - A level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of third and fourth transistors respectively receive first and second input signals. First ends of the third and fourth transistors are respectively coupled to control ends of the second and first transistors, and are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first ends of the third and fourth transistors respectively output first and second output signals. A first end and a control end of the fifth transistor are coupled to the control ends of one and the other of the first and second transistors. A second end of the fifth transistor is coupled to the second supply voltage.10-08-2009
20080315936Level Shifting - Various aspects are described, such as a method for operating a level shifter, in which the level shifter is coupled to a first supply voltage and a second supply voltage different from the first supply voltage. The method may include detecting whether the first supply voltage is present, and decoupling an input of the level shifter from an output of the level shifter responsive to detecting that the first supply voltage is not present.12-25-2008
20090212841LEVEL SHIFT CIRCUIT AND METHOD FOR THE SAME - The present invention discloses a level shift circuit which comprises: an input driver circuit; a capacitor having a first end electrically connected with the output of the input driver circuit; an output driver circuit electrically connected with a second end of the capacitor; and a feedback latch circuit electrically connected between the output of the output driver circuit and the second end of the capacitor, for maintaining the voltage level at the second end of the capacitor.08-27-2009
20120194256LEVEL SHIFTER - A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.08-02-2012
20080265973Semiconductor Device Having Transmitter/Receiver Circuit Between Circuit Blocks - A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.10-30-2008
20090231015DRIVER CIRCUIT - An object is to provide a driver circuit as well as a level converting circuit, capable of reducing current consumption and accelerating an operation, and in the driver circuit that changes a voltage level of an output signal in correspondence with a change in voltage level of an input signal, when a transistor is turned on and a voltage level of an output signal changes, a positive feedback operation of raising a voltage of an output node of an input stage circuit that drives the transistor is performed, whereby a gate-source voltage of the transistor increases while an on-resistance thereof decreases, and a change in voltage level of the output node in the positive feedback operation is accelerated due to a bootstrap action in the input stage circuit.09-17-2009
20090231014LEVEL SHIFTER CIRCUIT - A level shifter circuit which amplifies the amplitude of an input signal, includes a CMOS inverter which is composed of a p-type transistor and an n-type transistor, a first and a second capacitor one electrode of each of which is connected to the gate of the p-type transistor and that of the n-type transistor, respectively, a first switch which supplies the input signal to the other electrodes of the first and second capacitors, a second switch which applies a direct-current voltage whose amplitude is nearly half of the amplitude of the input signal to the other electrodes of the first and second capacitors, and a third and a fourth switch which apply a first and a second preset voltage to one electrode of each of the first and second capacitors, respectively.09-17-2009
20100164592LEVEL SHIFT CIRCUIT - A level shift circuit. A level shift circuit may include a first voltage supply control unit connected to a first voltage terminal to control a supply of a first voltage via a first and/or second path according to statuses of first and/or second input signals inputted differentially, a second voltage supply control unit connected to a second voltage terminal to control a supply of a second voltage via a first and/or second path, a switching unit controlling a connection between first and second voltage supply control units on a first and/or second path, and/or a buffer unit outputting an output signal corresponding to a first voltage and/or a second voltage in response to a first potential outputted between a first voltage supply control unit and a switching unit and/or a second potential output between a second voltage supply control unit and a switching unit.07-01-2010
20090201069LEVEL SHIFTING CIRCUIT - A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal.08-13-2009
20090002051INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.01-01-2009
20090243697LEVEL SHIFT CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR CIRCUIT DEVICE HAVING THE SAME - A level shift circuit includes a level shift section for receiving a low potential signal oscillating between a high potential and a ground potential and converting it into a high potential signal oscillating between the high potential and the ground potential, the level shift section being connected to at least a high potential power supply for generating the high potential, a low potential power supply for generating the low potential, and a ground power supply for generating the ground potential, an inverter section for inverting-amplifying the high potential signal from the level shift section, and an N-type MOS transistor for supplying the ground potential to the inverter section, the N-type MOS transistor being connected in series to the inverter section between the high potential power supply and the ground power supply and having its gate electrode connected to the low potential power supply.10-01-2009
20090243693CIRCUIT FOR PROVIDING DETERMINISTIC LOGIC LEVEL IN OUTPUT CIRCUIT WHEN A POWER SUPPLY IS GROUNDED - A high voltage analog interface circuit capable of producing a determinate zero or other low voltage when the high voltage power supply is turned off or grounded.10-01-2009
20080211563Interface Circuit, Power Conversion Device, and Vehicle-Mounted Electric Machinery System - An interface circuit capable of reliably transmitting signal even when there is fluctuation in the potential difference in reference potentials between circuits between which signal transmission is carried out. An interface circuit 09-04-2008
20090243695BI-DIRECTIONAL LEVEL SHIFTED INTERRUPT CONTROL - The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.10-01-2009
20110227626LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT - In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.09-22-2011
20120194253High Voltage Tolerant Differential Receiver - A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.08-02-2012
20090256617VOLTAGE LEVEL SHIFTER - Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal.10-15-2009
20100013539COMMUNICATION CIRCUIT WITH SELECTABLE SIGNAL VOLTAGE - The disclosed embodiments relate to a communication circuit. An exemplary embodiment of the communication circuit comprises a first branch adapted to operate at a first signal voltage level, a first source voltage contact adapted to deliver a voltage corresponding to the first signal voltage level to the first branch, a second branch adapted to operate at a second signal voltage level that is higher than the first signal voltage level, a second source voltage contact adapted to receive a voltage corresponding to the second signal voltage level via an external connector and to deliver the voltage corresponding to the second signal voltage level to the second branch, and a voltage selection circuit coupled to the first source voltage contact and the second source voltage contact, the voltage selection circuit configured to provide the first signal voltage level to the first branch and the second signal voltage level to the second branch.01-21-2010
20090315610Integrated Circuit Devices Having Level Shifting Circuits Therein - Level shifting circuits generate multiple tracking signals that are in-phase with an input signal, but are also level-shifted with wider voltage swings relative to the input signal. These input tracking signals are provided as separate inputs to an inverter having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein. A level shifting circuit may include a differential input circuit, which is responsive to true and complementary input signals. A first load circuit is electrically coupled to the differential input circuit. This first load circuit is configured to generate first and second tracking signals at respective first and second nodes therein. These first and second tracking signals are in-phase, level-shifted versions of each other, and have respective voltage swings that are greater than a voltage swing of the complementary input signals. The inverter includes a pull-up transistor responsive to the first tracking signal and a pull-down transistor responsive to the second tracking signal.12-24-2009
20090315609Level shift circuit and power semiconductor device - A level shift circuit includes a drive transistor, a first PMOS transistor, and first and second clamp transistors of PMOS type. The drive transistor, which drives the gate of the high-side NMOS transistor in a power semiconductor device, has a source-drain path coupled between a boot potential generated by a bootstrap circuit provided in the semiconductor device and a source potential of the high-side NMOS transistor. The first PMOS transistor has a source coupled to the boot potential, and a drain coupled to the gate of the drive transistor. The first clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the drain of the first PMOS transistor. The second clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the gate of the first PMOS transistor.12-24-2009
20100156499LOGIC LEVEL CONVERTER - A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement.06-24-2010
20100156498LEVEL SHIFTER - A level shifter with high performance, low power and reduced duty cycle distortion. The level shifter includes an input stage having a first circuit coupled to a second circuit. The first circuit includes a first pull up transistor receiving an input signal coupled to a first pull down transistor. The second circuit includes a second pull up transistor coupled to a second pull down transistor. An output of the input stage coupled to a first node in the first circuit. The level shifter further includes an inverter receiving the input signal. An output of the inverter and the second pull down transistor coupled to a second node. An output stage of the level shifter generates an output signal. The output stage includes a first transistor coupled to the first node and a second transistor coupled to the second node.06-24-2010
20100176864LEVEL SHIFTER CIRCUIT - A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground. The current limiting mechanism may comprise a transistor having a source/drain terminal connected to the first internal node.07-15-2010
20100259311LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS - A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor.10-14-2010
20090085635HIGH FREQUENCY DIFFERENTIAL VOLTAGE LEVEL SHIFTER - A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.04-02-2009
20100188131LEVEL SHIFTER FOR CHANGE OF BOTH HIGH AND LOW VOLTAGE - A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.07-29-2010
20100156500SEMICONDUCTOR DEVICE, OUTPUT CIRCUIT AND METHOD FOR CONTROLLING INPUT/OUTPUT BUFFER CIRCUIT IN SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having an output circuit that may be used to advantage in case the semiconductor device may possibly be used under different power supply voltages. The semiconductor device includes a signal terminal having at least the function of an output terminal, a power supply terminal, and an output circuit having first and second output buffer circuits. The first and second output buffer circuits are supplied with a supply power voltage from the power supply terminal and receive an inner output signal to drive the signal terminal. The semiconductor device also includes a power supply voltage discrimination circuit that discriminates the potential level of the power supply voltage to control the operation of the output circuit based on the result of discrimination. A first output buffer circuit is activated and a second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential. Both of the first and second output buffer circuits are activated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a second potential.06-24-2010
20100001779Constant-ON State High Side Switch Circuit - An electrical switching circuit for controlling current flow to an electrical load from a primary power source with a first electrical potential difference relative to a circuit ground comprises: a primary electrical switch coupled between the primary power source and the electrical load with a control input that is responsive to a control signal of predetermined potential difference relative to the electrical load; a primary energy storage device with a low side coupled to the electrical load; a primary switch controller coupled to the primary energy storage unit with a controller output coupled to the primary switch control input that develops a controller output signal that approximates the potential difference across the primary energy storage unit in response to a controller input signal; a secondary electrical energy storage device with a high side and a low side; a controllable electrical switch that toggles the low side of the secondary energy storage device from the circuit ground to the low side of the primary energy storage device; a primary unidirectional current gate coupled between the high side of the secondary energy storage device and the high side of the primary energy storage device to let current flow from the secondary energy storage device to the primary energy storage device when the potential difference of the high side of the secondary energy storage device is higher than the high side of the primary energy storage device; a secondary unidirectional current gate coupled between a secondary power source with an electrical potential difference of at least the predetermined potential relative to the circuit ground and the high side of the secondary energy storage device to let current flow from the secondary power source to the high side of the secondary energy storage device when the potential difference of the secondary power source is higher than the high side of the secondary energy storage device; wherein periodic operation of the secondary electrical switch charges the secondary energy storage device when the secondary switch toggles its low side to the circuit ground and the secondary energy storage device charges the primary storage device when the secondary switch toggles its low side to the low side of the primary energy storage device.01-07-2010
20130187699TECHNIQUES FOR SWITCHING BETWEEN AC-COUPLED CONNECTIVITY AND DC-COUPLED CONNECTIVITY - A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates.07-25-2013
20100219874LEVEL SHIFT CIRCUIT AND SWITCHING CIRCUIT INCLUDING THE SAME - The level shift circuit that converts a level of an input signal into a level between a first and a second voltage, which is higher than the first voltage includes a select circuit that generates an oscillation signal, where at least a frequency or an amplitude of the oscillation signal changes according to an input signal, a filter circuit that removes a DC component of the oscillation signal output from the select circuit and outputs an AC component, a detect circuit that operates between the first voltage and an output side voltage of the filter circuit, and generates a control signal including a signal voltage that changes according to at least a frequency or an amplitude of the AC component of the oscillation signal, and an output circuit that generates an output signal having a level between the first voltage and the second voltage according to the control signal.09-02-2010
20090219074Capacitive Coupling Type Level Shift Circuit of Low Power Consumption and Small Size - Provided is a level shift circuit. The level shift circuit includes an inverter including a first transistor having a first polarity to which an input signal from an input port is applied through a gate and a second transistor having a second polarity which is an opposite polarity to the first polarity, the second transistor being connected in series to the first transistor between a positive source voltage and a negative source voltage and a connection node between the first and second transistors being an output port, a capacitor connected between a gate of the first transistor and a gate of the second transistor, and a voltage adjusting means for accurately adjusting a voltage applied to the gate of the second transistor according to an exact switching operation time of the second transistor, using a clock signal and an output port signal of the inverter. A stable and high-speed operation can be performed with a comparatively small size and low power consumption can be achieved.09-03-2009
20110057708Semicondutor Integrated Circuit Device - A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.03-10-2011
20120194254High Voltage Tolerant Receiver - A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.08-02-2012
20100219873SIGNAL SOURCE DEVICES - A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.09-02-2010
20090278586LEVEL SHIFT CIRCUIT - A level shift circuit for adjusting voltage level of an input signal includes a voltage dividing circuit coupled to a input terminal for outputting a first voltage signal in response to the input signal at the input terminal, and a buffer coupled to a first node for generating a second voltage signal by adjusting voltage level of the first voltage signal. The voltage dividing circuit includes a first load coupled between the first node and the first supply voltage, and a second load coupled between the input terminal and the first node.11-12-2009
20090212842Level Shifter with Memory Interfacing Two Supply Domains - A level-shifter circuit configured to transfer data between two voltage supply domains may eliminate crowbar current while simultaneously providing a valid output signal. The level-shifter circuit may transfer a data signal between the two voltage domains using a latch that is capable of maintaining its output level—based on the destination supply rail—to correspond to the same state to which the level of the input signal—based on the originating supply rail—corresponds, even when the originating supply is decreased to a zero-volt state, or to a voltage equivalent to a low state. During normal operation, when both power supplies are available, the signal at the output of the latch, and hence at the output of the level-shifter circuit may toggle to always track the input signal. Thus, the level of the signal at the output of the level-shifter may always represent the same state (e.g. binary value) as the level of the input signal, during normal operation and also when the originating power supply is powered down.08-27-2009
20090322402SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK12-31-2009
20090039942LEVEL SHIFTER - A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.02-12-2009
20090072879SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES - A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.03-19-2009
20090072880OUTPUT CIRCUIT, OUTPUT CIRCUIT GROUP, AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An output circuit group comprises at least one first output circuit that outputs a pair of differential signals, the first output circuit including a first reversing circuit operated by applying a first power supply potential and a second power supply potential to reverse a first driving signal so as to output a first reverse driving signal, a first signal level converting circuit operated by applying the first power supply potential and a third power supply potential to convert the first driving signal to a signal having a predetermined level to output, a second signal level converting circuit operated by applying the first and the third power supply potentials to convert the first reverse driving signal to a signal having a predetermined level to output, a first differential circuit operated by applying the first and the third power supply potentials to output a signal having a first polarity corresponding to a difference between the signal output from the first signal level converting circuit and the signal output from the second signal level converting circuit, a second differential circuit operated by applying the first and the third power supply potentials to output a signal having a second polarity that is opposite to the first polarity and corresponding to a difference between the signal output from the second signal level converting circuit and the signal output from the first signal level converting circuit, a first output signal generating circuit operated by applying the first and the third power supply potentials to generate a first output signal based on the signal having the first polarity output from the first differential circuit, and a second output signal generating circuit operated by applying the first and the third power supply potentials to generate a second output signal based on the signal having the second polarity output from the second differential circuit, the first and the second output signals being included in the differential signals; and at least one second output circuit that outputs a single forward or reverse signal, the second output circuit including a second reversing circuit operated by applying the first and the second power supply potentials to reverse a second driving signal so as to output a second reverse driving signal, a third signal level converting circuit operated by applying the first and the third power supply potentials to convert the second driving signal to a signal having a predetermined level to output, a fourth signal level converting circuit operated by applying the first and the third power supply potentials to convert the second reverse driving signal to a signal having a predetermined level to output, a third differential circuit operated by applying the first and the third power supply potentials to output a signal having a first polarity corresponding to a difference between the signal output from the third signal level converting circuit and the signal output from the fourth signal level converting circuit, a loading circuit connected to an output terminal of each of the third and the fourth signal level converting circuits to have a load capacitance approximately equal to a load capacitance of the third differential circuit, and a third output signal generating circuit operated by applying the first and the third power supply potentials to generate the forward or reverse signal based on the signal having the first polarity output from the third differential circuit.03-19-2009
20110032019LEVEL SHIFTER WITH OUTPUT LATCH - A level shifter for a microcontroller shifts an input voltage in a first power domain to an output voltage level consistent with a second power domain. The level shifter is enabled to shift the voltages when both power domains are operative.02-10-2011
20110032020Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.02-10-2011
20100308888Driver circuit - A driver circuit including a pre-driver B12-09-2010
20100301917LEVEL SHIFT CIRCUIT - The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift.12-02-2010
20100214000Systems and Methods for Driving High Power Stages Using Lower Voltage Processes - In today's environment class-D amplifiers are used to provide an integrated solution for applications such as powered audio devices due to their advantages in power consumption and size over more traditional analog amplifiers. Due to power output requirements, the output stages of power drivers such as class-D amplifiers require a supply voltage in excess of the technologically allowed voltage for the switches in the output stage. A level shifter is used to ensure voltages supplied to the output switches do not exceed the technological limits. An ideal level shifter should provide the optimal voltage swing to output switches under all process, supply voltage and temperature (PVT) variations. The ideal level shifter should also provide fast transitions when the control signal changes from high to low and low to high.08-26-2010
20090085636Pre-driver circuit and apparatus using same - In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.04-02-2009
20100164593FAST DIFFERENTIAL LEVEL SHIFTER AND BOOT STRAP DRIVER INCLUDING THE SAME - A boot strap driver including a fast differential level shifter are disclosed. The fast differential level shifter may include a first differential amplifier differentially amplifying a pulse width modulation signal and an inverted pulse width modulation signal and outputting a first differential amplification voltage and a second differential amplification voltage based on the amplified result. The fast differential level shifter may also include a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage, and shifting the differential amplification voltages to voltages having an output range between a first voltage and a second voltage based on the amplified result.07-01-2010
20110025398Level Shifting Circuit - A level shifting circuit including a driving circuit, a reset circuit, a coupling circuit and an output-stage circuit is provided. The driving circuit, controlled by the input signal, controls the first driving signal having a high voltage level in the first period and controls the first driving signal having a low reference level in the second period. The reset circuit, controlled by the first driving signal in the first period, resets the second driving signal having the low reference level. The coupling circuit, controlled by the falling edge of the input-inversed signal, controls the second driving signal having a low voltage coupling level in the second period. The output-stage circuit, controlled by the first and the second driving signal, controls the output signal having a high voltage level in the second period and controls the output signal having a low voltage level in the first period.02-03-2011
20090066396LEVEL SHIFTING CIRCUIT - A level shifting circuit is provided. Thin oxide devices are utilized to reduce the threshold, and thick oxide devices are utilized to protect the thin oxides from breakdown. An input voltage input voltage swings between a low supply voltage and ground. An output voltage swings between a high supply voltage and the ground. An inverter with input connected to the input voltage, outputs an inverted input voltage. The input voltage is subsequently between 0.5V to 2.5V, and the output voltage is subsequently between 3V to 10V.03-12-2009
20090066399Level shift circuit - A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.03-12-2009
20110109370Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.05-12-2011
20110025397DRIVER CIRCUIT FOR GALLIUM NITRIDE (GaN) HETEROJUNCTION FIELD EFFECT TRANSISTORS (HFETs) - A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.02-03-2011
20110109369Low voltage input level shifter circuit and method for utilizing same - According to one embodiment, a level shifter circuit operable with a low voltage input comprises first and second pull-down switches configured to receive the low voltage input as respective non-inverted and inverted control voltages, first and second pull-up switches coupled between the respective first and second pull-down switches and an output supply voltage, and a pull-up boost switching stage coupled to a node between the first pull-up switch and the first pull-down switch. The pull-up boost switching stage is configured to turn ON in response to the second pull-down switch turning ON, and to turn OFF before the first pull-up switch turns OFF. In one embodiment, the level shifter circuit may be implemented as part of an input/output (IO) pad of an integrated circuit (IC) fabricated on a semiconductor die.05-12-2011
20110043269Level shift circuit - In a level shift circuit in a high electric potential side driving circuit, a latch circuit and a transmission circuit located at the front stage of the latch circuit are provided. The transmission circuit makes its output impedance high when two inputs V02-24-2011
20110043268LEVEL SHIFTER WITH NATIVE DEVICE - A level shifter includes an inverter, a first native device, a second native device, a first transistor, and a second transistor. First ends of the first and the second transistors are coupled to a first voltage. A second end and a control end of the first transistor are respectively coupled to the first ends of the first and the second native devices. A second end and a control end of the second transistor are respectively coupled to the first ends of the second and the first native devices. A second end and a control end of the first native device are respectively coupled to an output end and an input end of the inverter. A second end and a control end of the second native device are respectively coupled to the input end and the output end of the inverter.02-24-2011
20110115542LEVEL SHIFT CIRCUIT AND SWITCHING POWER SOURCE APPARATUS - A level shift circuit includes a first resistor connected to a level shift power source, a first transistor having a drain connected to a second end of the first resistor and a source to the ground, a second resistor connected to the level shift power source, a second transistor having a drain connected to a second end of the second resistor and a source to the ground, a pulse generator controlling ON/OFF of the first and second transistors according to an input signal, a control part generating a set signal if the first transistor is ON, a reset signal if the second transistor is ON, and no signal if there is no voltage difference between a voltage at the drain of the first transistor and a voltage at the drain of the second transistor, and a flip-flop providing an output signal according to the set and reset signals.05-19-2011
20110115541APPARATUSES AND METHODS FOR A LEVEL SHIFTER WITH REDUCED SHOOT-THROUGH CURRENT - A level shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time.05-19-2011
20090051402MULTI-FUNCTION CIRCUIT MODULE HAVING VOLTAGE LEVEL SHIFTING FUNCTION AND DATA LATCHING FUNCTION - The present invention discloses a multi-function circuit module having voltage level shifting function and data latching function via switching a plurality of switch elements. The multi-function circuit module includes a first circuit module, a fourth switch element, and a fifth switch module, wherein the first circuit module further includes a first switch module, a second switch module, and a third switch module. The multi-function circuit module can substantially reduce the circuit layout area. For example, when the multi-function circuit module of the present invention is applied in a source driving chip circuit, the multi-function circuit module can replace the original low-to-high voltage level shifting circuit and data latching circuit, so as to attain the purpose of reducing the chip area.02-26-2009
20090033402LEVEL CONVERSION CIRCUIT - A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.02-05-2009
20100164591POWER DETECTION SYSTEM AND CIRCUIT FOR HIGH VOLTAGE SUPPLY AND LOW VOLTAGE DEVICES - A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.07-01-2010
20110074485SEMICONDUCTOR CIRCUIT - A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit 03-31-2011
20110128063SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.06-02-2011
20090085637Apparatus effecting interface between differing signal levels - An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.04-02-2009
20110241754LEVEL SHIFTER AND METHOD OF CONTROLLING LEVEL SHIFTER - A level shifter converts an input signal changing between a first potential level and a second potential level into an output signal changing between the first potential level and a third potential level. The level shifter includes: a first circuit configured to be able to hold a potential at an input terminal to which the input signal is input at the first potential level; and a second circuit configured to be able to hold a potential at an output terminal from which the output signal is output at the first potential level.10-06-2011
20090085640Level shift device and method for the same - The present invention discloses a level shift device which comprises: a level shift circuit for receiving an input with a first voltage level and generating a first signal and a second signal with a second voltage level; and an output circuit which generates an output according to the first signal and the second signal.04-02-2009
20110175664ELECTRONIC CIRCUIT - A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply. The electronic circuit generates a control signal for ensuring the rising of other power supply voltages for each of the other power supply voltages based on the first and second detection signals.07-21-2011
20090033403LEVEL CONVERTING CIRCUIT - A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled.02-05-2009
20110095804Apparatus and method providing an interface between a first voltage domain and a second voltage domain - An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal.04-28-2011
20100052763CMOS Level Shifter Circuit Design - A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output.03-04-2010
20100060339VOLTAGE LEVEL SHIFTER WITH VOLTAGE BOOST MECHANISM - A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage.03-11-2010
20100127753Level shift circuit and display device having the same - A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.05-27-2010
20100127751LEVEL SHIFTER ADAPTIVE FOR USE IN A POWER-SAVING OPERATION MODE - A level shifter adaptive for use in a power-saving operation mode is disclosed for interfacing two circuit units powered by a first supply voltage and a second supply voltage respectively. The level shifter includes a preliminary level shifting circuit and an output auxiliary circuit. With the aid of the two supply voltages, the preliminary level shifting circuit is employed to receive an input signal having a first operating voltage swing and functions to convert the input signal into a first output signal and a second output signal both having a second operating voltage swing. The first output signal and the second output signal have opposite voltage levels relative to each other. The output auxiliary circuit is utilized for retaining the voltage level of the first output signal based on the second supply voltage regardless of whether the level shifter is still powered by the first supply voltage or not.05-27-2010
20120268189LOW VOLTAGE ISOLATION SWITCH, IN PARTICULAR FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS - A switching circuit is electrically coupled between a connection terminal and an output terminal of a transmission channel and includes first and second switching transistors electrically coupled in series to each other and having respective body diodes in anti-series, between the connection terminal and the output terminal. The switching circuit comprises a bootstrap circuit connected to respective first and second control terminals of these first and one second switching transistors, as well as to respective first and second voltage references. The bootstrap circuit includes a first parasitic capacitance electrically coupled between the first control terminal and a first bootstrap node, and a second parasitic capacitance electrically coupled between the second control terminal and a second bootstrap node. The parasitic capacitances have value of at least one order of magnitude lower with respect to the gate-source capacitances of the first and second switching transistors.10-25-2012
20110181340Fast Voltage Level Shifter Circuit - A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.07-28-2011
20100301918Level Shifter and Level Shifting Method Thereof - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.12-02-2010
20100295596LEVEL SHIFT CIRCUIT - A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 11-25-2010
20100271105High Boosting-Ratio/Low-Switching-Delay Level Shifter - A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.10-28-2010
20110175663GAMMA VOLTAGE GENERATION CIRCUIT - A gamma voltage generation circuit is provided. An offset voltage generator generates a first offset voltage by dividing a voltage difference between a first input voltage and a second input voltage based on a first code. A first voltage shifting circuit of a voltage level shifter shifts down a first reference voltage by the first offset voltage to output a first level-shifted voltage. A second voltage shifting circuit of the voltage level shifter shifts down a second reference voltage by the first offset voltage to output a second level-shifted voltage. Each of resistors of a resistor string outputs one of the gamma voltages. A first end and a second end of the resistor string are respectively coupled to a first output terminal and a second output terminal of the voltage level shifter.07-21-2011
20110018606LEVEL SHIFTERS AND HIGH VOLTAGE LOGIC CIRCUITS - Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.01-27-2011
20110210781LEVEL SHIFTER - A level shifter (09-01-2011
20090108904Shifting of a voltage level between different voltage level domains - A voltage level shifter for receiving a digital signal from a first voltage domain and converting said signal to a digital signal in a second voltage domain is disclosed. The voltage level shifter comprises: an input for receiving said digital signal from said first voltage domain; a device connected to said input of said voltage level shifter for receiving said digital signal from said first voltage domain and for outputting a digital signal in said second voltage domain, said device being powered by said second voltage domain; a first switching device arranged to connect a high level voltage source of said second domain to an input of said device in response to said input digital signal having a high level and to isolate said high level voltage source of said second domain from said input of said device in response to said input digital signal having a low level; and a second switching device arranged between said voltage level shifter input and said input of said device for inhibiting current flow from said high level voltage source of said second domain to said voltage level shifter input in response to a high level signal at said voltage level shifter input and for allowing current flow in both directions between said voltage level shifter input and said input of said device in response to said voltage level shifter input having a low level signal.04-30-2009
20090091367LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driver including a first level shifter group and a second level shifter group is provided. The first level shifter group includes at least one first level shifter to receive a first input signal. The second level shifter group includes at least one second level shifter to receive a second input signal. The driver sequentially enables the first level shifter group and the second level shifter group to sequentially transfer voltage levels of the first input signal and the second input signal.04-09-2009
20090002049Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first node, a second node, a third node, a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a first diode, an inductor, a first capacitor, and a boost circuit.01-01-2009
20120146704CASCODED LEVEL SHIFTER PROTECTION - A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.06-14-2012
20100277215Wideband Voltage Translators - In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.11-04-2010
20100321083Voltage Level Translating Circuit - A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain.12-23-2010
20100321084Level shift circuit - A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the bias to the level shift voltage generation circuit and the replica circuit.12-23-2010
20110133811CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.06-09-2011
20110133810System and Method for a Semiconductor Switch - In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node.06-09-2011
20110260770METHOD AND SEMICONDUCTOR DEVICE FOR MONITORING BATTERY VOLTAGES - A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly.10-27-2011
20110169543SYSTEM AND METHOD OF CONTROLLING DEVICES OPERATING WITHIN DIFFERENT VOLTAGE RANGES - Semiconductor devices, systems, and methods are disclosed to facilitate power management. A semiconductor device includes a first voltage island configured to operate within a first voltage range, where the first voltage range has a first midpoint. A second voltage island of the semiconductor device is configured to operate within a second voltage range, where the second voltage range has a second midpoint. The first voltage range is different than the second voltage range, and the first midpoint is substantially equal to the second midpoint.07-14-2011
20100117709VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME - A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.05-13-2010
20110095806SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and includes a first level shifter and a second level shifter. The first level shifter is configured to output the first potential in response to input of high level and to output low level in response to input of low level. The second level shifter is configured to output the first potential in response to input of the first potential an output of the first level shifter and to output the second potential in response to input of low level of the output of the first level shifter. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator to be connected to the power supply terminal during a first period after supplying the power supply voltage to the power supply terminal and control the output of the voltage generator to be disconnected from the power supply terminal after expiration of the first period.04-28-2011
20110095805LEVEL SHIFTERS AND INTEGRATED CIRCUITS THEREOF - An integrated circuit includes a level shifter configured to receive a first voltage signal that swings between a first voltage level and a second voltage level, outputting a second voltage signal that swings between the first voltage level and a third voltage level. The third voltage level is higher than the second voltage level. An inverter is coupled with the level shifter. The inverter can receive the second voltage, outputting a third voltage signal that swings between the third voltage level and a fourth voltage level. The fourth voltage level is lower than the third voltage level and higher than the first voltage level.04-28-2011
20110175665INTEGRATED CIRCUIT CONNECTION DEVICE - The integrated circuit connection device (07-21-2011
20100214001Level Shift Circuit - A level shift circuit includes an inverter, a shifting circuit, a first transistor, and a second transistor. The inverter inverts an original input signal into an inverted input signal. The shifting circuit generates a control signal according to the original input signal, the inverted input signal, and a reference voltage. The first transistor has a gate, a source, and a drain, in which the gate of the first transistor receives the control signal, and the source of the first transistor is connected to a high supply voltage. The second transistor has a gate, a source, and a drain, in which the gate of the second transistor receives the inverted input signal, the drain of the second transistor is connected to the drain of the first transistor, and the source of the second transistor is connected to a ground terminal or a low supply voltage.08-26-2010
20100026366Low Leakage Voltage Level Shifting Circuit - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.02-04-2010
20100026365ROBUST CURRENT MIRROR WITH IMPROVED INPUT VOLTAGE HEADROOM - An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source.02-04-2010
20100026364HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.02-04-2010
20100026361LEVEL SHIFTER AND DRIVING CIRCUIT INCLUDING THE SAME - The present invention related to a driving circuit including a level shifter. The driving circuit according to exemplary embodiment of the present invention includes a first level shifter, a second level shifter, and a gate driver. The first level shifter includes a path along which a pulse-on current flows in response to an on-control signal and a path along which a pulse-off control flows in response to an off-control signal. The second level shifter includes a path along which an on-current flows in response to the on-control signal and a path along which an off-control flows in response to the off-control signal. The gate driver turns on the switch in response to the pulse-on current, maintains the turned-on switch in the turn-on state in response to the on-control current, turns off the switch in response to the pulse-off current, and maintains the turned-off switch in the turn-off state in response to the off-control current.02-04-2010
20100019825NOVEL SINGLE SUPPLY LEVEL SHIFTER CIRCUIT FOR MULTI-VOLTAGE DESIGNS, CAPABLE OF UP/DOWN SHIFTING - A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.01-28-2010
20100019824Low Power Level Shifting Latch Circuits With Gated Feedback for High Speed Integrated Circuits - Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.01-28-2010
20090243692Two Voltage Input Level Shifter with Switches for Core Power Off Application - A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal.10-01-2009
20090174458Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.07-09-2009
20090174457IMPLEMENTING LOW POWER LEVEL SHIFTER FOR HIGH PERFORMANCE INTEGRATED CIRCUITS - A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter. The path control transistor being activated responsive to the level shifted output signal.07-09-2009
20080258798ANALOG LEVEL SHIFTER - An analog level shifter is provided, receiving an input voltage to generate an output voltage. In the analog level shifter, a NMOS transistor has a gate coupled to an input node where the input voltage is input. A resistance device comprises a first end coupled to source of the NMOS transistor, and a second end coupled to an output node where the output voltage is output. A current source is coupled to the output node, sinking a first current therefrom to ground.10-23-2008
20090160524LEVEL SLIDER CIRCUIT - The invention relates to a level slider circuit having a first level slider (06-25-2009
20110001538Voltage level shifter - A voltage level shifter is provided for receiving an input signal from an input voltage domain and converting said signal to a shifted signal in a shifted voltage domain. The voltage level shifter has an input, switching circuitry, a pass transistor and an output. The switching circuitry is configured to isolate an output of said pass transistor from said supply voltage rail when said input voltage domain corresponds to a logical zero.01-06-2011
20090201070PRE-DRIVER CIRCUIT USING TRANSISTORS OF A SINGLE CHANNEL TYPE - A serial interface apparatus comprises a driver for generating a differential communication signal and a pre-driver for driving the driver circuit. The pre-driver receives an input signal that alternates between VDD and ground and produces an output signal that alternates between a lower limit that is greater than ground and an upper limit that is less than VDD. The pre-driver comprises input circuitry and actuation circuitry, and the actuation circuitry comprises transistors of a single channel type.08-13-2009
20120146705CONTROL-VOLTAGE OF PASS-GATE FOLLOWS SIGNAL - A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal.06-14-2012
20110050318HIGH VOLTAGE DIFFERENTIAL PAIR AND OP AMP IN LOW VOLTAGE PROCESS - A high voltage differential pair and op amp implemented in a low voltage semiconductor process. The high voltage differential pair expands the incoming common mode voltage of a differential pair to multiple times the normal operating voltage of the differential pair through the use of high voltage current sources, current sinks and stacks of transistors. The high voltage op amp includes a high voltage input stage and a high voltage common source amplifier to expand the output voltage range to multiple times the normal operating voltage of the op amp.03-03-2011
20110050317BOOTSTRAP CIRCUIT - A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.03-03-2011
20100097117Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.04-22-2010
20110316605CIRCUIT APPARATUS AND SYSTEM - A circuit apparatus includes an output circuit that outputs a signal to a host apparatus via a bus, and an output control circuit that controls the output circuit. The output circuit has a first conductive transistor provided between an output node and a first power source node, and a second conductive transistor provided between the output node and a second power source node. In a first output mode, the output control circuit controls one of the first conductive transistor and the second conductive transistor to go to off and controls the other transistor to go to on/off, whereas in a second output mode, the output control circuit controls the first conductive transistor to go to on and the second conductive transistor to go to off or vice versa.12-29-2011
20110316604INPUT BUFFER CIRCUIT - An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.12-29-2011
20100033227ANALOG SWITCH CONTROLLER - Methods and systems for implementing an analog switch controller to improve linearity of analog switches are described.02-11-2010
20120154014LEVEL SHIFT CIRCUIT AND SWITCHING POWER SUPPLY DEVICE - A level shift circuit includes a level changing unit which includes first and second MOS transistors connected in series between a first power supply voltage terminal and a grounding point, and receives a signal having a first amplitude which varies between a lower second voltage and a ground potential to convert the signal to a signal having a second amplitude, and an output stage which includes first and second MOS transistors connected in series between the first power supply voltage terminal and a third voltage terminal to which a third voltage lower than the first power supply voltage and higher than the ground potential is supplied, and which stage is connected to an output node of the level changing unit. A first MOS transistor is connected in series between the first MOS transistor and the second MOS transistor of the level changing unit.06-21-2012
20120044009Level-Shifting Latch - A level-shifting latch circuit is disclosed. The level-shifting latch circuit may provide a level-shifting function, a data state retention function, and a dynamic-to-static conversion function. The level-shifting latch may receive two input signals from a dynamic logic circuit that are driven to the same state during a precharge phase. During an evaluation phase, one of the input signals may evaluate to a logic state complementary to the other input. The level-shifting latch circuit may generate an output signal corresponding to the input signal. On a precharge phase of a next cycle, the level-shifting latch may retain the state of the output when the two inputs are again driven to the same state.02-23-2012
20120044008LEVEL SHIFTERS FOR IO INTERFACES - A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.02-23-2012
20120001672Apparatuses and methods for a voltage level shifting - Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal.01-05-2012
20080284485Method for determining a switch-on threshold and electronic circuit arrangement for carrying out the method - An electronic circuit arrangement is disclosed for converting an input voltage signal having a first voltage level into an output signal having a second voltage level. An input unit is provided for inputting the input voltage signal at the first voltage level, while an output unit is arranged for outputting the output signal at the output of the electronic circuit arrangement. A threshold value comparison unit serves for comparing the first voltage level of the input signal with a switch-on threshold value. The circuit arrangement furthermore contains an input impedance changeover unit for changing over an input impedance of the circuit arrangement from a low value to a high value after a predetermined delay duration after the first voltage level of the input voltage signal exceeded the switch-on threshold value.11-20-2008
20120056657INTERFACE CIRCUIT - An interface circuit according to one aspect of the present invention may include a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal, an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal, and an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit.03-08-2012
20120013386LEVEL SHIFTER - A level shifter includes an output stage transistor and a level controller. The level controller receives a selection signal and provides a reference voltage at a gate terminal of the output stage transistor based on the selection signal. The output stage transistor, on being enabled by the reference voltage, provides a first level shifted output based on a first output reference voltage.01-19-2012
20120056656LEVEL SHIFTER - A level shifter includes first and second NMOS transistors with gates connected to inverted circuit and circuit inputs, respectively, sources connected to the ground, and drains connected to circuit and inverted circuit outputs, respectively. First and second PMOS transistors have their gates connected to the inverted circuit and circuit outputs, respectively, and sources connected to the high voltage supply. A third PMOS transistor of the multiple independent gate type has its source connected to the drain of the first PMOS transistor, drain and back-gate connected to the circuit output, and front-gate connected to the inverted circuit input. A fourth PMOS transistor of the multiple independent gate type has its source connected to the drain of the second PMOS transistor, drain and back-gate connected to the inverted circuit output, and front-gate connected to the circuit input.03-08-2012
20090027102Low-Leakage Level-Shifters with Supply Detection - Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage is described, including a level-shifter configured to shift a voltage of an digital input signal based on a first supply voltage to a digital output signal based on a second supply voltage, comprising a first transistor and a second transistor configured to set the digital output signal based on the digital input signal, a supply detector configured to generate a detection signal based on the first supply voltage, a disabler configured to, based on the detection signal, set the digital output signal of the level-shifter to a predetermined state, and a leakage reducer configured to, based on the detection signal, electrically disconnect the first and second transistors from the level-shifter.01-29-2009
20120068755LEVEL SHIFTER - According to one embodiment, a level shifter includes a high-side switch and a low-side switch. The high-side switch is connected between a high-potential power supply and a connection point and turned on in accordance with an input signal. The low-side switch is connected between the connection point and a low-potential power supply and turned on in accordance with an input signal. A ratio between ON resistance of the high-side switch and ON resistance of the low-side switch is set in accordance with a signal difference between an output signal and the input signal. The output signal is outputted to the connection point.03-22-2012
20100097116HIGH SIDE DRIVER WITH SHORT TO GROUND PROTECTION - A protection circuit for a high side driver includes an exclusive-OR gate adapted to receive a first input and a second input, analyze each of the inputs and transmit an output in response to the analysis of the inputs, wherein the first input represents an electric power output of the high side driver and the second input represents a control signal for operating the high side driver, and a switching device adapted to control an electrical output of the high side driver in response to the output of the exclusive-OR gate.04-22-2010
20120206185LEVEL-DOWN SHIFTER - A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.08-16-2012
20090134930LEVEL SHIFT CIRCUIT - A level shift circuit prevents a through current in an output circuit connected to a high-voltage power supply, thereby reducing power consumption and noise and enabling a high-speed operation. The level shift circuit includes first and second bias generating circuits that supply a gate bias voltage to each of a PMOS transistor as a first transistor and a NMOS transistor as a second transistor. Each of the first and second bias voltage generating circuits includes a series connection of a diode-connected PMOS transistor and a diode-connected NMOS transistor. The discharge of a capacitor to the high-voltage power supply is prevented, and a through current is prevented when an output signal transitions from a high-level to a low-level and vice versa, whereby power consumption and noise can be reduced.05-28-2009
20090134931MULTIPHASE LEVEL SHIFT SYSTEM - Each of n level shifters (LS05-28-2009
20090134929Level shifter for high-speed and low-leakage operation - The present invention discloses a voltage level shifter capable of interfacing between two circuit systems having different operating voltage swings. The voltage level shifter comprises an input buffer having a low supply voltage for inverting an external input signal to an internal input signal, and an output buffer having a high supply voltage for inverting the internal input signal to an external output signal. The high level of the external input signal is lower than the high level of the external output signal. The voltage level shifter is designed such that the input buffer is operating to achieve a low-leakage and high-speed performance.05-28-2009
20120025892SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK02-02-2012
20090146723BUFFER CIRCUIT - Disclosed is a buffer circuit including a source follower circuit comprising a MOS transistor which is driven by a current source. The MOS transistor has a gate to which an input voltage is supplied, a source from which an output voltage is output and a back gate supplied with a back gate voltage for being controlled to provide for a desired value of the source voltage. There is provided a second MOS transistor, to a gate of which a bias voltage is supplied, and a source of which is connected to a non-inverting input terminal of an OP amp. An output voltage of the OP amp is supplied as the back gate voltage06-11-2009
20120154013Power Converter for a Memory Module - An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.06-21-2012
20120119812LEVEL SHIFTER WITH PRIMARY AND SECONDARY PULL-UP CIRCUITS - A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.05-17-2012
20120249211SEMICONDUCTOR DEVICE - A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.10-04-2012
20120249210SWITCH CIRCUIT AND SEMICONDUCTOR CIRCUIT - A T/R switch applicable to an ultrasonograph and capable of transmitting a signal reflected from a living body over a wide band with low noise without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes includes: a common source terminal commonly and serially coupling the source terminals of two MOS transistors; a common gate terminal commonly coupling the gate terminals of the two MOS transistors; a main switch, the drain terminals of which are connected to input/output terminals; and a floating voltage circuit which is connected to the common gate terminal and common source terminal, makes the common gate terminal potential follow, in phase, variation in the common source terminal potential, and sends a signal to turn the switch on or off to the common gate terminal.10-04-2012
20100289552SYSTEMS INCLUDING LEVEL SHIFTER HAVING VOLTAGE DISTRIBUTOR - An exemplary embodiment of such a system includes: a level shifter operative to transform an input signal into an output signal, the level shifter includes: a voltage distributor operative to receive the input signal and distribute potential levels at a first node and a second node to respectively output a first signal and a second signal, and the voltage distributor includes: a current limiter, operative to provide a limited current passing through the first node; a switch, operative to selectively establish an electrical connection between the first node and the second node; and a first transistor having a first electrode, a second electrode, and a first control electrode, wherein the first electrode is connected to the second node, the second electrode is utilized to receive the input signal, and the first control electrode is coupled to the first node; and an output circuit, operative to generate the output signal.11-18-2010
20100244923SEMICONDUCTOR DEVICE - A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.09-30-2010
20100244924SEMICONDUCTOR DEVICE - A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply.09-30-2010
20120313684WIDE RANGE LEVEL SHIFT SYSTEM - A wide range level shift system receives an input signal with a first voltage level and a second voltage level. The wide range level shift system transforms the input signal to an output signal with a third voltage level and a fourth voltage level, wherein the first voltage level is smaller than the second voltage level, the second voltage level is smaller than the third voltage level, and the fourth voltage level is smaller than the first voltage level. The wide range level shift system has six transistors for reducing the number of transistors required, the layout area of the transistors, and the power consumption.12-13-2012
20120126875SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a power supply section, a driver, and a switch section. The power supply section is configured to generate a first potential higher than a positive power supply potential, and a negative second potential. The driver is connected to the power supply section and configured to output a control signal. A potential of the control signal is set to the first potential at high level and set to the second potential at low level according to a terminal switching signal. The switch section is configured to receive the control signal and switch a connection between terminals. The driver has a first level shifter, a second level shifter and a first circuit. The first level shifter has a first high-side switch and a first low-side switch. The second level shifter has a second high-side switch and a second low-side switch.05-24-2012
20120212279Threshold Voltage Detection Apparatus - A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified.08-23-2012
20110181341PUSH-PULL DRIVER CIRCUIT - A push-pull driver circuit includes a control circuit which controls switching operations of a plurality of high-side transistors, a level-shift circuit which shifts a control signal, output by the control circuit when the control circuit performs turn-off control on the plurality of transistors, to a first voltage by which the plurality of transistors are turned off, and which inputs the shifted signal to a gate of one of the plurality of transistors, and a conduction-state selection circuit which, if an output of the level-shift circuit is the first voltage, inputs the output to gates of the rest of the transistors, and otherwise, according to the control by the control circuit, sets each of gate inputs of the rest of the transistors to either a high-impedance state or a second voltage by which the plurality of transistors are turned on.07-28-2011
20110181339LEVEL SHIFT CIRCUIT - A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.07-28-2011
20110181338Dual path level shifter - Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.07-28-2011
20120212280IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.08-23-2012
20120133416LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE - A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.05-31-2012
20120133413DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.05-31-2012
20120133415LEVEL SHIFTER - A level shifter includes a driving signal generating unit, a driving unit, and a current path forming unit. The driving signal generating unit is configured to generate a pull-up signal and a pull-down signal in response to an input signal, which may swing between a first high level and a first low level. The driving unit is configured to generate an output signal swinging between a second high level and a second low level in response to the pull-up signal and the pull-down signal. The current path forming unit is configured to form a current path between the pull-up signal and the pull-down signal in response to the pull-up signal and the pull-down signal.05-31-2012
20120133414COMPENSATING FOR WANDER IN AC COUPLING DATA INTERFACE - Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.05-31-2012
20120212281LEVEL SHIFTER - A level shifter is provided. The level shifter includes a signal converter connected to an external power source and a ground, first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source, and a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit including first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal.08-23-2012
20090058493Signal Level Converter - An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair.03-05-2009
20090058494HEAD SUBSTRATE, PRINTHEAD, AND HEAD CARTRIDGE - The following arrangement is added to a head substrate including a plurality of electrothermal transducers, a plurality of switching elements which drive the plurality of electrothermal transducers, and a logic circuit which drives the plurality of switching elements. That is, the head substrate includes a plurality of level converters which correspond to the respective switching elements, and apply a voltage obtained by boosting a logic voltage. Further, the head substrate includes a bias circuit which applies a bias voltage lower than the boosted voltage to the plurality of level converters.03-05-2009
20090058491HIGH-TO-LOW LEVEL SHIFTER - A high-to-low level shifter is disclosed, comprising a high voltage unit and a low voltage unit. The high voltage unit receives an input signal from an input node. The high voltage unit outputs a first output signal to an output node when the high voltage unit receives a low-voltage-level input signal. The low voltage unit outputs a second output signal to the output node when the high voltage unit receives a high-voltage-level input signal.03-05-2009
20090058492ELECTRONIC ISOLATOR - The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.03-05-2009
20120169395LEVEL SHIFTER - A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit.07-05-2012
20120169396VOLTAGE DOWN CONVERTER - A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage.07-05-2012
20100052764LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between an operation voltage and a power supply terminal of the first buffer for controlling a power-supplying time of the first buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.03-04-2010
20120313686LEVEL SHIFT CIRCUIT - A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.12-13-2012
20120075001LEVEL SHIFT CIRCUIT AND SWITCHING REGULATOR USING THE SAME - A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage.03-29-2012
20100271103SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.10-28-2010
20090066397LEVEL SHIFT CIRCUIT - In a level shift circuit, even when a power supply voltage of an input signal is reduced, a level shift operation is reliably performed without causing increase in circuit area and process costs. For a pair of n-type transistors which receive an input signal and a reverse signal of the input signal as a pair of complementary signals at their gates, respectively, a layout which allows reduction in unit gate width size is adopted. The layout configuration includes a plurality of divided rectangular doped regions which function as drains and sources and a plurality of gates arranged to align in a gate length direction with a gate width direction according with a short side direction of the doped regions. The gates are electrically connected with one another, the drains are electrically connected with one another, and the sources are electrically connected with one another.03-12-2009
20120313685LEVEL SHIFTER AND METHOD OF USING THE SAME - A level shifter and a method of operating a level shifter are provided. The level shifter includes a first-level shifter unit configured to convert an external input signal into a signal in a preset first-voltage range using a plurality of transistors and output the converted signal and a second-level shifter unit configured to convert the signal output from the first-level shifter unit into a signal in a preset second-voltage range using a plurality of transistors and output the converted signal.12-13-2012
20120187998MULTIPLE FUNCTION POWER DOMAIN LEVEL SHIFTER - A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.07-26-2012
20120256675INPUT REFERENCE VOLTAGE GENERATING METHOD AND INTEGRATED CIRCUIT USING THE SAME - An integrated circuit includes: a reference voltage generation unit configured to be driven in response to an enable signal, select one of a plurality of reference voltages generated by dividing a power supply voltage as an input reference voltage, and output the input reference voltage; and a reference voltage level compensation unit configured to be driven in response to the enable signal and change a level of the input reference voltage by an amount of change in a level of an external voltage.10-11-2012
20090021293Low-Power Integrated-Circuit Signal Processor With Wide Dynamic Range - An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.01-22-2009
20120229189HIGH SPEED LEVEL SHIFTERS AND METHOD OF OPERATION - A circuit comprising an inverter coupled to an input and receiving an input signal. A first pull-down transistor coupled to the inverter, pulling down an output when the input signal is low. A second pull-down transistor coupled to the input, pulling down a complementary output when the input signal is high. A first pull-up transistor coupled to the complementary output, pulling up the output when the input signal is high. A second pull-up transistor coupled to the output, pulling up the complementary output when the input signal is low. A first switch receiving a first control signal, coupled to the complementary output. A first strong pull-up transistor coupled to the first switch, assisting the pull up of the output. A second switch coupled to the output, receiving a second control signal. A second strong pull-up transistor coupled to the second switch, assisting the pull up of the complementary output.09-13-2012
20080297224Minimizing Static Current Consumption While Providing Higher-Swing Output Signals when Components of an Integrated Circuit are Fabricated using a Lower-Voltage Process - An aspect of the present invention minimizes static current consumption in an output block which receives a lower strength input signal and drives a corresponding output signal with a higher strength. Such a feature may be obtained while ensuring that no closed path exists between a first and second reference potentials (having voltage levels equaling upper and lower limits of the swing of the output signal) used by a circuit portion driving a pair of transistors operating as an inverter in the output block. In one embodiment, such a closed path is avoided during the steady state of the output signal, while in an alternative embodiment, the closed path is avoided during the transitions as well.12-04-2008
20080297223LEVEL SHIFT CIRCUIT WITH IMPROVED DV/DT SENSING AND NOISE BLOCKING - A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.12-04-2008
20110037509APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.02-17-2011
20110037508REGISTERS WITH REDUCED VOLTAGE CLOCKS - A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level.02-17-2011
20120268188VOLATGE LEVEL SHIFTING APPARATUS - A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.10-25-2012
20120126874INTEGRATED CIRCUIT - An integrated circuit includes a transfer unit configured to transfer an input signal having a first swing width between a first voltage and a second voltage, a driving unit configured to drive an output terminal to output an output signal having a second swing width in response to the input signal transferred from the transfer unit, and a control unit configured to control the driving unit in response to the output signal.05-24-2012
20120081167SEMICONDUCTOR DEVICE, AND METHOD OF DIAGNOSING ABNORMALITY OF BOOSTING CIRCUIT OF SEMICONDUCTOR DEVICE - The battery monitoring IC is provided with the short circuiting switch that includes the switching element that shorts the input side and the output side of the boosting circuit that boosts the power supply voltage to the driving voltage, that can drive the MOS transistor within the buffer amplifier in the saturated region, and supplies the driving voltage as the driving voltage of the buffer amplifier. An abnormality of the boosting circuit can be diagnosed by comparing the output voltage, that is measured when the short circuiting switch is turned off and the driving voltage boosted by the boosting circuit is supplied to the buffer amplifier, and the output voltage, that is measured when the short circuiting switch is turned on and the power supply voltage is, without going through the boosting circuit, supplied as is to the buffer amplifier.04-05-2012
20120081166Level Shifter Circuits and Methods - Some embodiments of the present disclosure relate to a level shifter that provides improved response time and/or low static power dissipation compared to conventional level shifters. In some embodiments, a level shifter circuit includes an input terminal coupled to a first semiconductor device, and an output terminal coupled to a second semiconductor device. The first semiconductor device is designed to operate over a first voltage range associated with an input signal, and the second semiconductor device is designed to operate over a second, different voltage range associated with an latched output signal. To transform the input voltage range to the output voltage range, the level shifter circuit includes a signal analyzer and an output latch, wherein the signal analyzer includes at least one state change element for setting a voltage level of the latched output signal.04-05-2012
20120280741SEMICONDUCTOR DEVICE - A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.11-08-2012
20120280740OUTPUT BUFFER CIRCUIT AND INPUT/OUTPUT BUFFER CIRCUIT - An output buffer circuit includes first and second output circuits, and those output terminals are coupled to each other. The first output circuit outputs a first signal having a voltage level of a first high potential power supply or a low potential power supply and includes a first output transistor at a high potential side. The second output circuit outputs a second signal having a voltage level of a second high potential power supply, which is lower than the first high potential power supply, or the low potential power supply and includes a second output transistor at a high potential side. A control circuit sets the gate and back gate of at least one of the first and second output transistor to the voltage level of the second high potential power supply when the first high potential power supply is deactivated and the second high potential power supply is activated.11-08-2012
20120280739SYSTEM AND METHOD FOR LEVEL-SHIFTING VOLTAGE SIGNALS USING A DYNAMIC LEVEL-SHIFTING ARCHITECTURE - A system and method to level-shift multiple signals from a first voltage domain to a second voltage domain with minimized silicon area. A level-shifting system may be organized by implementing a static level-shifter coupled to a plurality of dynamic level-shifters. The static level-shifter may provide a voltage control signal for each of the dynamic level-shifters. Each of the dynamic level-shifters may level-shift an individual input signal from a first voltage domain to a second voltage domain.11-08-2012
20110285449APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.11-24-2011
20120092058OPEN LOOP RAIL-TO-RAIL PRECHARGE BUFFER - A method and system that may include a pair of amplifier transistors and an output coupled to a load device. The precharge buffer may be controlled by an activation signal. The precharge buffer may also include a pair of level shifters. Each level shifter may be provided in association with a respective one of the transistors, and each may provide a respective level shift to an input signal at a common signal source based on a reference voltage. Outputs of the level shifters may be coupled to the respective transistors. The precharge buffer may also include a bypass signal path extending from the common signal source to the load device. A signal path may be controlled by another activation signal, and the precharge buffer and the bypass signal may be enabled during mutually exclusive states of the activation signal.04-19-2012
20100214002SIGNAL LEVEL CONVERSION CIRCUIT - A signal level conversion circuit includes three or more level shift circuits to output internal output signals upon receiving input signals, respectively. Each of the level shift circuits is formed of a common electrical element and an electrical element connected to the common electrical element. A voltage higher than that supplied to the common electrical element is supplied to the electrical element. A buffer circuit having an input tolerant function is provided in each of the common electrical elements. The internal output signals are set at lower level than the input signals by the buffer circuits, and the internal output signal outputted from one of the level shift circuits is further outputted via other level shift circuits.08-26-2010
20100201425LEVEL SHIFT CIRCUIT - A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor.08-12-2010
20100060338LEVEL SHIFTER WITH REDUCED LEAKAGE - The present invention relates generally to the level shifter circuits and more specifically to improved level shifter circuits providing for reduced leakage current and reduced power consumption. In one or more implementations, a method, apparatus and computer program product for level shifting input voltages by minimizing current leakage of a circuit coupled with an improved level shifting circuit is provided for. In one implementation the method includes providing a low voltage domain of the circuit, and providing for turning off the transistor if the low voltage domain of the circuit is not stable, and turning on the transistor if the low voltage domain of the circuit is stable.03-11-2010
20120139606MULTI-VOLTAGE INPUT BUFFER - In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).06-07-2012
20130021084LOW VOLTAGE SENSORS WITH INTEGRATED LEVEL TRANSLATORS - This disclosure provides techniques for integrating voltage level translators into sensors to provide compatibility between sensor output and inputs to devices that utilize the sensor outputs. According to these techniques, low voltage sensors may be integrated with voltage level translators into an integrated sensing unit that provides data outputs in both low voltage levels and high voltage levels. The integrated sensing unit may provide a selection pin for the output, which may allow utilizing a low voltage output and/or a high voltage output.01-24-2013
20130021085Voltage Level Translator Circuit for Reducing Jitter - A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.01-24-2013
20080238525High Speed Level Shifter - The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.10-02-2008
20080204109High-performance level shifter - A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.08-28-2008
20080231340Level shift circuit - A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.09-25-2008
20130169339LEVEL SHIFTING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage.07-04-2013
20080224755LEVEL-SHIFT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND LEVEL SHIFT METHOD - A level shift circuit that converts a level of an input signal having a logic level at a first input electric potential and a logic level at a second input electric potential and that generates an output signal having a logic level at a first output electric potential corresponding to the first input electric potential and a logic level at a second output electric potential corresponding to the second input electric potential. The level shift circuit includes a first power-supply node to which the first output electric potential is supplied, a second power-supply node to which the second output electric potential is supplied, a latch unit having an input node and an output node from which the output signal is output, the latch unit being configured to receive power from the first power-supply node and the second power-supply node and to maintain, if an electric potential of the input node is identical to one of the first output electric potential and the second output electric potential, an electric potential of the output node to be the other one of the first output electric potential and the second output electric potential, a switching element that is provided between the first power-supply node and the input node and controlled to be in an ON state or an OFF state, a control unit that controls the switching element to be in the ON state at a timing corresponding to the time when a level of the input signal changes from the first input electric potential to the second input electric potential, and a setting unit that changes an electric potential of the output node to the first output electric potential in a predetermined period just before the logic level of the input signal changes.09-18-2008
20110273219VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.11-10-2011
20130176066LEVEL SHIFT CIRCUIT - The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned ON when supply voltage is low and in a shut-down state with the power supply turned OFF to ensure the breakdown voltages of the elements when supply voltage is high. The high supply voltage level shift circuit is in a shut-down state with its power supply turned OFF when supply voltage is low and comes into an operating state with the power supply turned ON while ensuring the breakdown voltages of elements when supply voltage is high.07-11-2013
20080218240CURRENT CONTROL CIRCUIT USED FOR VOLTAGE BOOSTER CIRCUIT - When a low level voltage is inputted to an input terminal IN, a transistor EF09-11-2008
20130113541LOW POWER LEVEL SHIFTER WITH OUTPUT SWING CONTROL - A level shifter comprising a first driver transistor receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value.05-09-2013
20130113540ELECTRONIC DEVICE AND METHOD FOR PROVIDING A DIGITAL SIGNAL AT A LEVEL SHIFTER OUTPUT - An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level.05-09-2013
20130093492DEVICE - A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 04-18-2013
20130093491SEMICONDUCTOR DEVICE AND LEVEL SHIFTING CIRCUIT FOR THE SAME - A level shifting circuit includes an inverter inverting an input voltage of an input node and driving a first voltage of a first node, a first output driving unit driving an output voltage of an output node to a first level in response to the first voltage of the first node, a first connection unit electrically coupling the first node to a second node or electrically isolating the first node from the second node in response to the first voltage of the first node, an internal driving unit driving a second voltage of the second node to a second level in response to the input voltage of the input node and the output voltage of the output node, and a second output driving unit driving the output voltage of the output node to the second level in response to the second voltage of the second node.04-18-2013
20130099847INPUT CIRCUIT - An input circuit includes an inverter, a first path control circuit and a second path control circuit. An input of the inverter is connected with a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically connects an input terminal and the first node when the input potential is higher than the target inversion potential, and blocks off an electrical connection between the input terminal and the first node when the input potential is lower than the target inversion potential. The second path control circuit electrically connects a ground terminal and the first node when the input potential is lower than a second inversion potential which is lower than the target inversion potential and blocks off the electrical connection between the ground terminal and the first node when the input potential is higher than the second inversion potential.04-25-2013
20130113542OUTPUT BUFFER, OPERATING METHOD THEREOF AND DEVICES INCLUDING THE SAME - A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.05-09-2013
20130099846DRIVING CIRCUIT, SEMICONDUCTOR DEVICE HAVING DRIVING CIRCUIT, AND SWITCHING REGULATOR AND ELECTRONIC EQUIPMENT USING DRIVING CIRCUIT AND SEMICONDUCTOR DEVICE - Disclosed is a driving circuit that includes a switching element configured to be connected between an input terminal and an output node; a first power supply circuit configured to generate a first voltage; and a first driving circuit configured to drive the switching element with an output thereof using a voltage of the output node as a reference negative-side power supply voltage and the first voltage as a positive-side power supply voltage. The voltage of the output node is used as a reference negative-side power supply voltage of the first power supply.04-25-2013
20130127515VOLTAGE DIVIDING CIRCUIT - A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage.05-23-2013
20130135028HIGH VOLTAGE SUSTAINABLE OUTPUT BUFFER - An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.05-30-2013
20100277216I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (11-04-2010
20080204111HIGH-IMPEDANCE LEVEL-SHIFTING AMPLIFIER CAPABLE OF HANDLING INPUT SIGNALS WITH A VOLTAGE MAGNITUDE THAT EXCEEDS A SUPPLY VOLTAGE - A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms.08-28-2008
20080204110LEVEL SHIFT CIRCUIT - A level shift circuit for converting a first signal level into a second signal level, includes a load circuit connected to the second power supply voltage, a first high voltage-resistant transistor in which a drain is connected to the load circuit, and a predetermined constant voltage is applied to a gate, a source voltage control circuit controls a voltage level of the source of the first high voltage-resistant transistor in accordance with an input signal at the first signal level, and has a second low voltage-resistant transistor, and an output terminal which is connected between the drain of the first high voltage-resistant transistor and the load circuit for outputting an output signal at the second signal level. A gate insulating film of the low voltage-resistant transistor has a voltage resistance lower than that of a gate insulating film of the high voltage-resistant transistor.08-28-2008
20130127514LEVEL TRANSLATOR - A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.05-23-2013
20080197907DRIVER AMPLIFIER CIRCUIT - A driver amplifier circuit is provided which includes a voltage level shifting circuit and an Op-Amp. A positive power supply terminal and a negative power supply terminal of the Op-Amp receive a first reference voltage and a second reference voltage outputted from the voltage level shifting circuit, causing a DC voltage level of an output signal to be equal to 0V. Meanwhile, the absolute value of a voltage difference between the first reference voltage and the second reference voltage is equal to V08-21-2008
20080197906Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling - A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.08-21-2008
20110221502TESTABLE INTEGRATED CIRCUIT AND TEST METHOD THEREFOR - Disclosed is an integrated circuit (09-15-2011
20090085639OUTPUT BUFFER CIRCUIT - An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.04-02-2009
20130135027LEVEL SHIFTER CIRCUIT, INTEGRATED CIRCUIT DEVICE, ELECTRONIC WATCH - A first circuit receives input signals of the first electric potential system which uses a first high potential and a first low potential as the power supply electric potential, and outputs a first signal which is a signal of the first electric potential system, a second circuit which generates output signals according to the input signal of the second electric potential system which uses as the power supply electric potential a second high potential of the first electric potential system, wherein the second circuit includes an initial stage inverter that receives the second signals and outputs third signals, and an initial stage switch that switches between connecting and disconnecting the initial stage inverter and a power supply that supplies the second high potential or a power supply that supplies the second low potential based on the first signals, and generates the output signals based on the third signals.05-30-2013
20100308887APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS ON AN INTEGRATED CIRCUIT - An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.12-09-2010
20120274382LEVEL-SHIFTER CIRCUIT USING LOW-VOLTAGE TRANSISTORS - A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals.11-01-2012
20110234291Level shifter - A level shifter converts an input signal having an amplitude between a ground and a first power supply voltage into an output signal having an amplitude between the ground and a second power supply voltage. The level shifter includes an input unit, driven by the first power supply voltage, that raises a first pulse signal at a rise of the input signal and raises a second pulse signal having the same polarity as the first pulse signal at a fall of the input signal, and a level shift unit that converts a signal level of the first pulse signal into an amplitude level of the second power supply voltage, and converts a signal level of the second pulse signal into an amplitude level of the second power supply voltage.09-29-2011
20100315150VOLTAGE LEVEL SHIFTER FOR ARBITRARY INPUT SIGNALS - Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal.12-16-2010
20130154712Multiplexer with Level Shifter - A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.06-20-2013
20130154713VOLTAGE LEVEL SHIFTER - A level shifter includes a latch supplied at a first voltage, and first and second series connections of first and second switch elements and first and second biased elements in series with first and second branches of the latch respectively. Third and fourth switch elements are connected in parallel with the first and second series connections respectively. The input signal, at a voltage different from the first voltage, activates the third or fourth switch element during a transition period after a change of state of the input signal one way or the other to change the state of the latch, and deactivates the third or fourth switch element and activates the first or second switch element to maintain the state of the latch during a stabilization period following the transition period. The transition periods are shortened, reducing current consumption and transfer delay times.06-20-2013
20130181762CURRENT MIRROR MODIFIED LEVEL SHIFTER - A current mirror modified level shifter includes a pair of PMOS including a PMOS (M07-18-2013
20130181763LEVEL SHIFTER - A level shifter includes a resistor R07-18-2013
20110309873CIRCUIT HAVING GATE DRIVERS HAVING A LEVEL SHIFTER - A circuit comprises a first level shifting circuit. The level shifting circuit comprises a first and second latching differential pairs. The first latching differential pair has first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage. The second latching differential pair has first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage. In one embodiment, the level shifting circuit protects transistor gates of the circuit from an overvoltage.12-22-2011
20120019303DC - DC CONVERTER - The invention relates to a DC-DC converter adapted to supply a MEMS device comprising an input for receiving a DC voltage (Vs), an output for transmitting a supplied voltage (V01-26-2012
20120019302LOW MINIMUM POWER SUPPLY VOLTAGE LEVEL SHIFTER - A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.01-26-2012
20130194020LEVEL SHIFTING CIRCUIT - An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter.08-01-2013
20130194021CAPACITIVE COUPLING, ASYNCHRONOUS ELECTRONIC LEVEL SHIFTER CIRCUIT - An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.08-01-2013
20120044010SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.02-23-2012
20120299631Level shifting circuitry - Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal.11-29-2012
20120086495VOLTAGE LEVEL SHIFTER - An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.04-12-2012

Patent applications in class Interstage coupling (e.g., level shift, etc.)