Class / Patent application number | Description | Number of patent applications / Date published |
327310000 | Transient or signal noise reduction | 38 |
20080238520 | POWER ELECTRONIC MODULE INCLUDING DESATURATION DETECTION DIODE - A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts. | 10-02-2008 |
20090167404 | Semiconductor Device, Electronic Device Having the Same, and Driving Method of the Same - A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements. | 07-02-2009 |
20090201068 | Output circuit with overshoot-reducing function - Output circuit with reduced overshoot includes input end, output end, a circuit composed of PMOS and NMOS, rising and falling edge trigger bias circuits. The rising and falling edge trigger bias circuits output biasing voltages to the output end for clamping the voltage of the output signals respectively according to the rising edge and the falling edge of the input signal. In this way, the overshoot of the output signal is reduced. | 08-13-2009 |
20090261883 | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch - A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal. | 10-22-2009 |
20100164590 | SEMICONDUCTOR INTEGRATED CIRCUIT - An N-channel transistor is provided as a switch between a high potential power line and a low potential power line. A high-pass filter is constituted by a capacitor and a resistor. When a voltage between the high potential power line and the low potential power line is started to oscillate by a switching operation, the high-pass filter causes a high-pass component thereof to pass, thereby turning ON the N-channel transistor to reduce a ringing. | 07-01-2010 |
20100182067 | AC Clamp Circuit for Video Applications - This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch. | 07-22-2010 |
20100201424 | SAMPLING FILTER APPARATUS - The sampling filter apparatus | 08-12-2010 |
20130181761 | TRIMMING OF OPERATIVE PARAMETERS IN ELECTRONIC DEVICES BASED ON CORRECTIONS MAPPINGS - An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions, and means for forcing the application of the selected trimming action for the reference parameter. For each non-reference parameter different from the at least one reference parameter, the electronic device includes means for selecting one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter, and means for forcing the application of the selected trimming action for each non-reference parameter. | 07-18-2013 |
20130214842 | POWER SYSTEM, POWER MODULE THEREIN AND METHOD FOR FABRICATING POWER MODULE - A power system, a power module therein and a method for fabricating power module are disclosed herein. The power module includes a first and a second common pins, and a first and a second bridge arms. The first and the second common pins are symmetrically disposed at one side of a substrate. The first bridge arm includes a first and a second semiconductor devices, and the first and the second semiconductor devices are connected to each other through the first common pin and disposed adjacently. The second bridge arm includes a third and a fourth semiconductor devices, and the third and the fourth semiconductor devices are connected to each other through the second common pin and disposed adjacently. The first and the third semiconductor devices are disposed symmetrically, and the second and the fourth semiconductor devices are disposed symmetrically. | 08-22-2013 |
20130328610 | SEMICONDUCTOR DEVICE - The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value. | 12-12-2013 |
20140077861 | INTERFACE CIRCUIT - An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a switch circuit and a switch control circuit. The receiver has a first channel and a second channel. The first channel receives a first channel voltage, and the second channel receives a second channel voltage. According to the first channel voltage and the second channel voltage, the switch control circuit controls the switch circuit to discharge a common mode capacitor before the first terminal resistor or the second terminal resistor couple to the common mode capacitor. | 03-20-2014 |
20140145775 | OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS - Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages. | 05-29-2014 |
20140184298 | ELECTRIC CIRCUIT AND SEMICONDUCTOR DEVICE - An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied. | 07-03-2014 |
20150022255 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 01-22-2015 |
20150130527 | LOW POWER SCHEME TO PROTECT THE LOW VOLTAGE CAPACITORS IN HIGH VOLTAGE IO CIRCUITS - An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode. | 05-14-2015 |
20160006419 | ELECTRONIC SYSTEMS - An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal. | 01-07-2016 |
327311000 | By filtering | 11 |
20110279162 | Signal conditioning system with a sigma-delta modulator - A signal conditioning system includes a first filter, a signal processing module connected with the first filter, a second filter connected with the signal processing module, and a Σ-Δ modulator connected with the second filter. The signal processing module makes the saturation overflow treatment to the signal output by the first filter using the characteristics of the radix complement adder. The Σ-Δ modulator is a high order filter formed by a plurality of cascaded and inter-stage feedback second-order filters. Based on the performance of the Σ-Δ modulator and the whole system, the stability of the signal conditioning system is improved. | 11-17-2011 |
20120032723 | SYSTEM AND METHOD FOR SIGNAL LIMITING - A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may include low pass filtering. The limiting may include hard-limiting of the filtered signal. A phase difference between the limited signal and a reference signal may be detected. | 02-09-2012 |
20120044007 | COMMUNICATION DEVICE - A communication device is provided. The communication device includes a circuit for reducing low-frequency interference, and the circuit for reducing low-frequency interference includes a low-frequency filter circuit and a capacitor. The low-frequency filter circuit includes a terminal and a terminal, in which the terminal is connected to a power supply, and the terminal is connected to a load; the capacitor includes a terminal and a terminal, in which the terminal is connected to the load, and the terminal is connected to the power. By setting the circuit for reducing low-frequency interference in a communication device, an input current of the communication device may be maintained stable, as a result, low-frequency interference of the communication device to other communication devices is reduced. | 02-23-2012 |
20140028368 | PROGRAMMABLE RF NOTCH FILTER FOR ENVELOPE TRACKING - A parallel amplifier, a switching supply, and a radio frequency (RF) notch filter are disclosed. The parallel amplifier has a parallel amplifier output, such that the switching supply is coupled to the parallel amplifier output. Further, the RF notch filter is coupled between the parallel amplifier output and a ground. The RF notch filter has a selectable notch frequency, which is based on an RF duplex frequency. | 01-30-2014 |
20140132326 | PULSE NOISE SUPPRESSION CIRCUIT AND PULSE NOISE SUPPRESSION METHOD THEREOF - Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level. | 05-15-2014 |
20140152367 | NOISE FILTERING CIRCUIT AND OPERATING METHOD THEREOF - There are provided a noise filter circuit and an operating method thereof. A noise filter circuit includes a first delay circuit, and a second delay circuit connected to the first delay circuit in series, wherein the first delay circuit and the second delay circuit each include at least one inverter and at least one delay element for generating a predetermined delay, and the first delay circuit and the second delay circuit have different filtering characteristics. | 06-05-2014 |
20140253206 | SYSTEMS AND METHODS FOR PROVIDING LOW-PASS FILTERING - A low-pass filter circuit is described. The low-pass filter circuit includes a pseudo-resistor. The pseudo-resistor includes at least one metal-oxide-semiconductor field-effect transistor. The at least one metal-oxide-semiconductor field-effect transistor receives a digital power supply domain signal. The low-pass filter circuit also includes a capacitor. The capacitor is coupled to the pseudo-resistor. The capacitor provides a filtered signal. The low-pass filter circuit may pass digital signal transitions and provide low-pass filtering when there is no signal transition. | 09-11-2014 |
20140266381 | BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER - A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal. | 09-18-2014 |
20150042392 | ADJUSTABLE COMPENSATION RATIO FEEDBACK SYSTEM - Apparatus for implementing Adjustable Compensation Ratio (ACR) active shielding or control of physical fields (magnetic, electric, electromagnetic, acoustic, etc.), comprising the addition of a secondary internal feedback loop within a conventional primary closed feedback loop topology. Compensation-ratio transfer function order and coefficients adjustment permits accommodating frequency-dependent and frequency-independent effects within a Protected Volume when a system field sensor or sensor array is not at the exact location where external field interference must be optimally canceled. A Laplace polynomial term precisely sets this parameter in a supplementary feedback link by modeling the frequency-dependent characteristic of an Interacting Medium without deleterious effect on other desirable primary closed-loop characteristics. The inventive ACR can be used in advanced active cancellation for magnetic shielding purposes. | 02-12-2015 |
20150054561 | Semiconductor Device and Method of Cascading Matched Frequency Window Tuned LC Tank Buffers - A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength. | 02-26-2015 |
20160173064 | SPURIOUS FREQUENCY ATTENUATION SERVO WITHOUT TUNING FILTER | 06-16-2016 |
327312000 | By feedback limiting-clamping | 4 |
20100109741 | METHOD AND APPARATUS FOR ROBUST MODE SELECTION WITH LOW POWER CONSUMPTION - A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal. | 05-06-2010 |
20140028369 | Level Shifter Utilizing Bidirectional Signaling Through a Capacitive Isolation Barrier - According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal. | 01-30-2014 |
20140097881 | BALANCED AUXILIARY ON TIME GENERATOR FOR MULTIPHASE STACKABLE CONSTANT ON TIME CONTROL ARCHITECTURE - A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture. | 04-10-2014 |
20140210540 | POWER LINE CARRIER COMMUNICATION RECEPTION CIRCUIT - A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. | 07-31-2014 |
327313000 | Using 3 or more terminal type nonlinear devices only | 6 |
20080309394 | GUARDRINGED SCR ESD PROTECTION - Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less. | 12-18-2008 |
20100264974 | Input-output device protection - A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, whilst the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost. | 10-21-2010 |
20120293230 | RINGING SUPPRESSION CIRCUIT - An inter-line switching element formed of a MOSFET is provided between a pair of signal lines. When the level of a differential signal changes from high to low, a control circuit turns on the FET for a fixed period thereby to suppress ringing by decreasing the impedance between the signal lines when the level of the differential signal transitions, and causing the energy of the distortion of the differential signal waveform to be absorbed by the on-resistance of the FET. | 11-22-2012 |
20130321056 | BOOTSTRAP CIRCUIT - A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal. | 12-05-2013 |
20140145776 | HIGH FREQUENCY SWITCH - There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices; a second signal transferring unit including a plurality of second switching devices; a first shunting unit including a plurality of third switching devices; and a second shunting unit including a plurality of fourth switching devices. | 05-29-2014 |
20150008971 | NOISE CURRENT COMPENSATION CIRCUIT - Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal. | 01-08-2015 |
327314000 | Using diode type nonlinear devices only | 1 |
20140300401 | Methods of Circuit Construction to Improve Diode Performance - The present invention is a method by which diodes are connecting in a circuit such that they are more robust. The method involves placing two diodes of opposite directions in parallel and applying a DC bias such that a forward diode may then handle higher than normal voltages and a reverse diode provides a failsafe in the event of a reverse bias. | 10-09-2014 |