Entries |
Document | Title | Date |
20080204106 | SIGNAL ADJUSTMENT TECHNIQUES - An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC level of the received signal. From the filtered signal and an adjustment signal, the amplification module generates an amplified signal. The adjustment signal, which is provided by the adjustment signal source, may control (e.g., diminish) an effect of the level shift on a DC level of the amplified signal. | 08-28-2008 |
20080218238 | Input signal detecting circuit - An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator. | 09-11-2008 |
20080224754 | HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CANCELLATION AND METHOD - A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units. | 09-18-2008 |
20080246527 | Methods and systems for converting a single-ended signal to a differential signal - Methods and systems are described for converting single-ended signals to differential signals. In one exemplary embodiment, an input single-ended signal is received and converted into a differential signal having minimized jitter without using a DC-cancellation loop. | 10-09-2008 |
20080278212 | DC OFFSET CANCELING CIRCUIT - The present invention provides a circuit for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value. | 11-13-2008 |
20080303577 | ARRANGEMENT FOR CANCELING OFFSET OF DRIVER AMPLIFIER CIRCUITRY - In an offset canceling arrangement, an offset of an operational amplifier may be canceled even in case capacitive or resistive element is connected outside of the operational amplifier per se, and a signal may be output even during the offset canceling operation. IC chips include respective sets of plural output circuits. Each of the IC chips is provided with an offset canceling function, for which the respective sets of output circuits are grouped into plural groups. A reference signal for offset canceling is generated from a reference output circuit. One of the groups, each constituting one IC chip, is selected, and the reference signal for offset canceling generated by the group is used as a reference signal for offset canceling for the remaining group(s). | 12-11-2008 |
20090085632 | LOW-OFFSET INPUT CIRCUIT - In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit. In a signal receiver circuit having an input circuit, an automatic zero amplifier, an analog/digital converter circuit, an encoder circuit, and a signal holding circuit, an output error signal of the input circuit is amplified by the automatic zero amplifier, and the signal is digitalized or the digitalized signal is encoded as the occasion demands, and held by the holding circuit, and the circuit characteristic variation of the input circuit is adjusted by the held signal. | 04-02-2009 |
20090102536 | DATA TRANSMISSION SYSTEM - A data transmission system is made up from: a transmission circuit ( | 04-23-2009 |
20090121769 | OFFSET COMPENSATION CIRCUIT AND YAW RATE SENSOR EQUIPPED THEREWITH - An offset compensation circuit for a yaw rate sensor, having a subtracter, which is provided for subtracting a correction value from an input signal, the correction value being obtainable by dividing each of n measurements of the input signal by the constant n and subsequently integrating a number of n quotients into an integrator. Furthermore, a yaw rate sensor having such an offset compensation circuit. | 05-14-2009 |
20090140789 | CALIBRATION STRATEGY FOR REDUCED INTERMODULATION DISTORTION - The present disclosure relates to a circuit and method for reducing intermodulation distortion in a non-linear device having a differential output stage. A calibration circuit is provided for adding a calibration offset voltage to at least one of one output branch of the differential output stage and a bulk terminal of a transistor of one output branch of the differential output stage to obtain a desired output offset at the differential output stage. Thereby, a certain degree of asymmetry is introduced so that both output branches of the differential output stage are matched or optimized to improve the IIP | 06-04-2009 |
20090146722 | Systems and Arrangements to Provide Input Offset Voltage Compensation - In one embodiment a method is disclosed that includes applying a series of voltages to an input of an offset evaluation latch, detecting an offset voltage from the offset evaluation latch in response to the application of the series of voltages, and applying an offset compensation voltage to the input of a plurality of sampling latch in response to the detected offset voltage. In some embodiments a digital value can be assigned to the applied offset voltage. When the offset voltage is determined, it can be applied to a plurality sampling latches and a data stream can be received and clock and data recovery can be performed. | 06-11-2009 |
20090160522 | DC RESTORATION CIRCUIT ALLOWING SPARSE DATA PATTERNS - The present invention provides a device for restoring a DC component in a differential digital data stream. The device comprises a first and second peak detector for detecting peaks in the differential digital data stream, a memory element for storing an average of the first and second detected peak signals during rich data patterns, an error signal selector for error signal selection, and a regulator for negative feedback of a selected error signal. The selected error signal is either the average of the detected peak signals stored on the memory element minus the signal at the output of the first peak detector, or the signal at the output of the second peak detector minus the average of the detected peak signals stored on the memory element. | 06-25-2009 |
20090167402 | Dual barrel receiver equalization architecture - Methods and apparatus relating to dual barrel receiver equalization architectures are described. In an embodiment, a receiver logic may include an amplifier and two comparators to equalize frequency components of a received signal. The receiver logic may further include offset adjustment (or cancelation) logic to generate an offset adjustment (or cancelation) signal coupled to the amplifier. Other embodiments are also described. | 07-02-2009 |
20090174456 | DC Offset Correcting Device And DC Offset Correcting Method - A signal generator generates a test signal including a positive signal and a negative signal which have the same amplitude. The signal generator corrects a DC level of the test signal based on a DC offset correcting signal supplied thereto, and supplies the corrected test signal to a frequency converter. An amplitude detector detects the amplitudes of the positive and negative signals of the test signal processed by the frequency converter. A level compressor converts in level the amplitudes of the positive and negative signals which are detected by the amplitude detector, with a gain variable depending on an input level thereto. A comparator compares the amplitudes of the positive and negative signals which are converted in level by the level compressor, with each other. An offset adjuster supplies the DC offset correcting signal depending on a compared result from the comparator to the signal generator. | 07-09-2009 |
20090212839 | CIRCUIT FOR SETTLING DC OFFSET IN DIRECT CONVERSION RECEIVER - The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver. | 08-27-2009 |
20090212840 | DC CURRENT REDUCTION CIRCUIT - A DC current reduction circuit of the present invention that reduces a DC component in an output current of a current output element in which an AC current and a DC current are superimposed includes a low-pass filter for extracting a current component of a frequency lower than a cutoff frequency from the output current and a reduction unit that reduces the extracted current component from the output current. The low-pass filter has a frequency changing unit that changes the cutoff frequency from higher to lower as a continuous function over time. | 08-27-2009 |
20090261881 | Signal processing device having a variable current source - A signal processing device suppresses a DC offset without omission of a low-frequency component of a signal in a receiver in a direct conversion system. The signal processing device includes an input terminal | 10-22-2009 |
20090261882 | Skewed Double Differential Pair Circuit for Offset Cancelllation - A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system. | 10-22-2009 |
20090267675 | Offset compensation using non-uniform calibration - Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset. | 10-29-2009 |
20090302923 | TERMINATED INPUT BUFFER WITH OFFSET CANCELLATION CIRCUIT - A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input. | 12-10-2009 |
20100039158 | OFFSET CORRECTION DEVICE AND METHOD - A direct-current-offset correction device includes a digital-to-analog converter that converts a digital signal into an analog signal, a modulator that modulates the analog signal to generate a modulated signal, a direct-current-offset correction value calculation unit that calculates a direct-current-offset correction value as a reverse characteristic component of a carrier leak occurring in the modulated signal based on a demodulated signal which is demodulated by feeding back the modulated signal, a direct-current-offset correction unit that corrects a direct-current-offset on the digital signal based on the direct-current-offset correction value, a correction value detection unit that detects whether or not the direct-current-offset correction value is zero or a neighboring value of zero, and an offset generation unit that superimposes a direct-current-offset component on the analog signal based on a detection result of the correction value detection unit. | 02-18-2010 |
20100045356 | DATA PROCESSING SYSTEM FOR CLIPPING CORRECTION | 02-25-2010 |
20100066426 | BASELINE RESTORE BASED ON DIODE STAR CONFIGURATION AND TRANSFORMER COUPLING - A simple, low cost circuit with only passive components, and thus low power consumption, is provided for baseline restoration of an AC coupled signal. The circuit includes a passive network of diodes arranged in a star configuration and an RF-transformer. A differential signal strategy may be employed by including a differential amplifier at the input and output of the passive network. | 03-18-2010 |
20100090744 | OFFSET CANCELLATION CIRCUIT AND A METHOD THEREOF - An offset cancellation circuit includes a sense amplifier configured to receive an input signal and offset voltages and to generate an output signal. A compensation voltage generation section is configured to be inputted with the output signal, and the compensation voltage generation section increases or decreases compensation voltages until the voltage level of the output signal reaches a target voltage level. The voltage level of the compensation voltages is maintained and a control signal is enabled when the voltage level of the output signal reaches the target voltage level. A control loading section is configured to provide the compensation voltages as the offset voltages or maintains the current level of the offset voltages, according to the control signal. | 04-15-2010 |
20100127750 | SWITCHED CAPACITOR INPUT STAGE FOR IMAGING FRONT-ENDS - Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field. | 05-27-2010 |
20100148844 | System And Method For Common Mode Translation - System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels. | 06-17-2010 |
20100164588 | GENERATING A FULL RAIL SIGNAL - Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled to a common-mode pre-emphasis module, the center-swing signal generator to receive a low swing current mode logic (CML) signal and output a center-swing signal, and a full-swing cross-coupled inverter coupled to the center-swing signal generator, the full-swing cross-coupled inverter to receive the center-swing signal and output a full-rail single-ended swing signal. Additional apparatus, systems, and methods are disclosed. | 07-01-2010 |
20100164589 | OPERATIONAL AMPLIFIER - An operational amplifier capable of suppressing power consumption and noise generation includes an offset modifier including a differential amplification circuit, and an offset memory for storing an offset voltage using a latch circuit. The differential amplification circuit includes first and second NMOS transistors connected to an input terminal, first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors, a third NMOS transistor connected to sources of the first and second NMOS transistors, a third PMOS transistor connected to a source of the second PMOS transistor, a fourth NMOS transistor connected to the third PMOS transistor, to form an output to be applied to the offset memory, and left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel. | 07-01-2010 |
20100201423 | Low-noise DC Offset Calibration Circuit and Related Receiver Stage - A DC offset calibration circuit has a first resistor, a first switch, a second resistor, and a second switch. The first resistor is coupled to a first supply voltage. The first switch is coupled to the first resistor, to a first input of an amplifier, and to a first input resistor. A second end of the first input resistor is not coupled to the first supply voltage. The second resistor is coupled to a second supply voltage. The second switch is coupled to the second resistor, to a second input of the amplifier, and to a first end of a second input resistor. A second end of the second input resistor is not coupled to the second supply voltage. | 08-12-2010 |
20100231284 | Dynamic grounding system and method - Dynamic grounding including monitoring the floating DC outputs of a power amplifier, detecting an imbalance in the floating DC outputs, generating a compensation signal in response to a detected imbalance, and adjusting the power amplifier to re-balance the floating DC outputs and suppress transients. | 09-16-2010 |
20100308886 | OFFSET CANCELLING CIRCUIT - When a voltage is applied from outside such that a current flowing in a Hall element is switched, each of a plurality of capacitors is charged with an output voltage of the Hall element in each state. A dummy switching element is connected to a switching element which connects the plurality of capacitors in parallel to each other, the dummy switching element and the switching element being controlled to be switched ON and OFF exclusively with respect to each other. | 12-09-2010 |
20100315149 | High-speed data compared latch with auto-adjustment of offset - A high-speed data compared latch with auto-adjustment of offset, includes input pair transistors P, input pair transistors N, a compared latch module, an input control module, an output control module and a offset logic control module, the offset logic control module creates two control signals that regulate the number of input pair transistors P and input pair transistors N respectively according to reset signal RESET and the latched output of the compared latch module, and achieve self correcting of offset through regulating the number of the input pair transistors P and the input pair transistors N. The present invention is a feedback mechanism, automatically trimming the number of differential input pair to achieve the trimming differential pair operating point and the threshold voltage, eliminate the process variation, and latch on more precise control match the differential input pair transistors of the high-speed data compared latch in receiver accurately. | 12-16-2010 |
20110012665 | Systems and Methods for Lowering Interconnect Capacitance Through Adjustment of Relative Signal Levels - Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential. Regardless of the particular embodiment used, raising the midpoint-voltage level of the signals on the TWIs relative to the substrate decreases capacitance, which increases the frequency of the data which can propagate through the TWIs while potentially reducing the signaling power. | 01-20-2011 |
20110018605 | OFFSET-VOLTAGE CALIBRATION CIRCUIT - Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage. | 01-27-2011 |
20110032017 | SIGNAL RECEIVER AND VOLTAGE COMPENSATION METHOD - A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value. | 02-10-2011 |
20110037506 | DC OFFSET CALIBRATION FOR COMPLEX FILTERS - Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter. | 02-17-2011 |
20110037507 | MIXER WITH DIFFERENTIAL DC OFFSET CANCELLATION FUNCTION - A mixer with a differential DC offset cancellation function includes: a load unit including a first load unit and a second load unit; a mixing unit biased by current transferred from the load unit to mix inputs signal and oscillation signals; a first output voltage detection unit detecting an output voltage of the first output terminal; a second output voltage detection unit detecting an output voltage of the second output terminal; a first injection/extraction circuit unit injecting current into the first load unit or extracting current from the first load unit according to the size of a first detection voltage; a second injection/extraction circuit unit injecting current into the second load unit or extracting current from the second load unit according to the size of a second detection voltage; and a current regulation unit regulating an overall current flowing across the first and second injection/extraction circuit units. | 02-17-2011 |
20110050315 | POWER SUPPLY AND DC-DC-CONVERSION - In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator. | 03-03-2011 |
20110057704 | METHOD FOR DETECTING A CURRENT AND COMPENSATING FOR AN OFFSET VOLTAGE AND CIRCUIT - A method and circuit for detecting a current and compensating for an offset voltage. The circuit includes two comparators where one of the comparators has two input terminals and the other comparator has three input terminals. An input terminal of each of the two comparators are commonly connected together, the other input terminal of the two-input comparator is coupled for receiving a first reference voltage, and a second input terminal of the three-input comparator is coupled for receiving a second reference voltage. During a first portion of the period of a sense signal the two comparators operate in a sensing mode and during a second portion of the period of the sense signal the comparator having the three input terminals operate in a current nullification mode or an offset voltage compensation mode. An offset compensation signal is generated during the second portion of the sense signal. | 03-10-2011 |
20110080204 | DC offset cancel circuit, semiconductor device, and receiving device - A DC offset cancel circuit according to the present invention includes, in each of an I-channel side and a Q-channel side, a mixer and an ADC that output differential signals. This DC offset cancel circuit further includes a direct-current component extractor. The direct-current component extractor extracts direct-current components from a signal I and a signal Ib output from the mixer in the I-channel side and a signal Q and a signal Qb output from the mixer in the Q-channel side. The ADC in the I-channel side receives signals in which the direct-current components extracted from the signal Q and the signal Qb are fed forward to the signal I and the signal Ib. The ADC in the Q-channel side receives signals in which the direct-current components extracted from the signal I and the signal Ib are fed forward to the signal Q and the signal Qb. | 04-07-2011 |
20110102049 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE WITH COMPENSATION OF THE OFFSET VOLTAGE - An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current. | 05-05-2011 |
20110121880 | DC OFFSET CANCELLATION CIRCUIT - A DC offset cancellation circuit includes: a control signal generation unit generating i (i is a natural number) number of pulse signals having a pulse width corresponding to a DC offset amount; a current source supplying i number of currents each having a different current ratio; a switching unit determining a current quantity to be supplied to a feedback capacitor by adjusting a turn-on quantity of each of the i number of currents according to the pulse width of each of the i number of pulse signals; and an electric charge quantity regulation unit charging DC offset electric charges corresponding to current supplied from the switching unit through the feedback capacitor and transferring the DC offset electric charges charged in the feedback capacitor to a sampling capacitor through a rotary capacitor, to allow the sampling capacitor to primarily store the DC offset electric charges and then secondarily store electric charges corresponding to an input signal. s | 05-26-2011 |
20110133809 | Semiconductor device and method for cancelling offset voltage of sense amplifier - A semiconductor device includes first and second signal lines; a sense amplifier amplifying potential difference occurring in the first and second signal lines; a cancel charge generator circuit producing cancel charge that corresponds to offset voltage in the sense amplifier; a cancel charge storage circuit storing the cancel charge; and a cancel charge feed circuit feeding the cancel charge that has been stored in the cancel charge storage circuit to the first and second signal lines to cancel the offset voltage. | 06-09-2011 |
20110148500 | SAMPLE HOLD CIRCUIT AND METHOD THEREOF FOR ELIMINATING OFFSET VOLTAGE OF ANALOG SIGNAL - A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage. | 06-23-2011 |
20110156792 | SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames. | 06-30-2011 |
20110175661 | High-Resolution Parametric Signal Restoration - Provided are high-resolution parametric signal restoration systems, and applications thereof. Such systems include a multi-output module and a parametric compensator. The multi-output module provides a reference gain output signal and one or more higher gain output signals based on a single input signal. The parametric compensator independently responds to functional parameters of the one or more higher gain output signals to provide a compensation error signal. The single input signal is modified based on the compensation error signal. | 07-21-2011 |
20110215857 | DC OFFSET CANCELLER, RECEIVING APPARATUS AND DC OFFSET CANCELLATION METHOD - According to an embodiment, a DC offset canceller includes a first DA converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period. The successive approximation register is configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases. | 09-08-2011 |
20110241751 | DIFFERENTIAL OFFSET CALIBRATION CIRCUIT - A differential offset circuit adapted for an adaptive filter of a receiver front end is provided. The differential offset circuit includes four controllable current sources which are respectively coupled to two differential output terminals of the adaptive filter. The current magnitudes of the controllable current sources are capable of being adjusted according to design requirements so that the differential offset of the adaptive filter is mitigated to avoid that the adaptive filter outputs a distorted signal to affect the accuracy of signal transmission. | 10-06-2011 |
20110267129 | GENERATING A FULL RAIL SIGNAL - Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled to a common-mode pre-emphasis module, the center-swing signal generator to receive a low swing current mode logic (CML) signal and output a center-swing signal, and a full-swing cross-coupled inverter coupled to the center-swing signal generator, the full-swing cross-coupled inverter to receive the center-swing signal and output a full-rail single-ended swing signal. Additional apparatus, systems, and methods are disclosed. | 11-03-2011 |
20120025889 | ASSESSMENT OF ON-CHIP CIRCUIT BASED ON EYE-PATTERN ASYMMETRY - During an asymmetry testing mode of an integrated circuit, the asymmetry of an on-chip I/O circuit is tested. In particular, a transmitter circuit in the integrated circuit transmits electrical signals, which are associated with a predefined data pattern, to a receiver circuit in the integrated circuit via a communication channel (such as a differential pair of signal lines). Then the integrated circuit generates an eye pattern using the received electrical signals, and determines an asymmetry of the eye pattern about a common reference level of the received electrical signals. Furthermore, the integrated circuit performs remedial action based on the determined asymmetry. For example, the integrated circuit may compare the determined asymmetry with a predefined asymmetry criterion and, if the asymmetry exceeds the predefined asymmetry criterion, may output a result of the comparison that indicates a failure of the asymmetry test. | 02-02-2012 |
20120032722 | Offset Calibration for Amplifiers - An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (V | 02-09-2012 |
20120044006 | DC OFFSET CALIBRATION APPARATUS, DC OFFSET CALIBRATION SYSTEM, AND METHOD THEREOF - A DC offset calibration apparatus including a signal processing unit, a comparison unit, a first resistor array, a second resistor array, and a resistor array control unit is provided. The signal processing unit receives an input differential signal and generates an output differential signal. The comparison unit detects and determines a first DC output voltage and a second DC output voltage of the output differential signal and generates a DC offset signal. First ends of the first resistor array and the second resistor array are respectively coupled to a first input terminal and a second input terminal of the signal processing unit. The resistor array control unit adjusts resistances of the first and the second resistor array according to the DC offset signal and a bit code sequence until the DC offset signal enters a transient state, so as to calibrate a DC offset voltage in the output differential signal. | 02-23-2012 |
20120086494 | RECEIVER CIRCUITRY AND RELATED CALIBRATION METHODS - Apparatus and methods are provided for calibrating and operating a receiver circuit. An exemplary method comprises the steps of applying a first voltage offset to a first input of an amplifier circuit, generating an output signal at an output of the amplifier circuit based on the first voltage offset and a second voltage offset at a second input of the amplifier circuit, adjusting the second voltage offset based on the output signal, and maintaining the second voltage offset at a constant voltage when the output signal is indicative of the second voltage offset cancelling the first voltage offset. | 04-12-2012 |
20120133412 | Square Wave Signal Component Cancellation - Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component. | 05-31-2012 |
20120146703 | APPARATUS AND METHOD FOR CALIBRATING SIGNAL - Provided is an apparatus and method for calibrating a signal, which extracts a plurality of signal samples from sine-wave input signals; calculates a real root of a DC component calculating condition derived using simultaneous equations for values of the signal samples; calculates a value of a DC component from the simultaneous equations by using the calculated real root; and removes the DC component by applying the calculated value of the DC component to the sine-wave input signals, wherein the number of signal samples extracted in the signal sample extracting step is set according to the number of unknown quantities of the simultaneous equations. | 06-14-2012 |
20120194252 | METHOD OF SHIFTING AUTO-ZERO VOLTAGE IN ANALOG COMPARATORS - Aspects of the invention provide, inter alia, techniques for shifting auto-zero voltage in analog comparators. An embodiment of the invention may include at least one diode configured transistor to increase a drain voltage of at least one NMOS load transistor. A first switch and a second switch may be implemented to increase a voltage at a gate of a first PMOS input transistor and a voltage at a gate of a second PMOS input transistor when the first switch and the second switch are closed. | 08-02-2012 |
20120249208 | CLAMP CIRCUIT, SEMICONDUCTOR DEVICE, SIGNAL PROCESSING SYSTEM, AND SIGNAL CLAMPING METHOD - The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage. | 10-04-2012 |
20120274381 | OFFSET COMPENSATION APPARATUS FOR MAGNETIC DETECTION CIRCUIT AND METHOD THEREOF - Disclosed herein are an offset compensation apparatus for a magnetic detection circuit, and a method thereof. The offset compensation apparatus includes: an amplifying unit amplifying an output voltage, and outputting the amplified voltages; an offset detection unit detecting an offset; a comparison unit determining whether or not the offset output from the offset detection unit is greater than a pre-set positive reference value or smaller than a pre-set negative reference value; a counter unit; and a current supply. | 11-01-2012 |
20130049840 | IMPLEMENTING DIFFERENTIAL RESONANT CLOCK WITH DC BLOCKING CAPACITOR - A method and circuit for implementing differential resonant clocking with a DC blocking capacitor, and a design structure on which the subject circuit resides are provided. An on-chip inductor and an on-chip capacitor are connected between a pair of differential active clock load nodes to form a resonant tank circuit. The on-chip inductor has a selected value based upon a value of a load capacitor of the differential active clock load nodes to determine the resonant frequency. The on-chip capacitor has a selected value substantially greater than the value of the load capacitor. | 02-28-2013 |
20130069705 | SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE - Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed. | 03-21-2013 |
20130076427 | APPARATUS AND METHOD FOR REMOVING DC OFFSET IN POWER METER - Disclosed herein are an apparatus and a method for removing a DC offset in a power meter. The apparatus for removing a DC offset in a power meter according to exemplary embodiment includes: an ADC; a HPF removing the DC offset from the signal output from the ADC; a selector receiving the signals passing through the HPF and bypassing the HPF and outputting any one thereof; a determination block receiving a signal output from the ADC or from the selector and determining whether the received signal is a sinusoidal signal; an offset calculation block calculating the DC offset to be compensated from the signal input to the determination block or output from the selector; and an offset compensation unit disposed on a path bypassing the HPF, compensating the calculated DC offset value in the signal output from the ADC and outputting the compensated result to the selector. | 03-28-2013 |
20130088276 | DRIVER OUTPUT PAD LEAKAGE CURRENT COMPENSATION - A device includes a sense circuit configured to detect a leakage current from a driver output pad. A current mirror responds to the sense circuit and compensates for the leakage current detected at the driver output pad. A scaled compensation circuit can supply compensation current to the current mirror. | 04-11-2013 |
20130120048 | DC OFFSET CANCELATION CIRCUIT - There is provided a DC offset cancellation circuit including: a capacitor circuit unit including at least one capacitor connected between an input terminal and an input of an amplifier; a MOSFET circuit unit including a plurality of MOSFETs connected in series between a first connection node connected to a predetermined one of both terminals of the capacitor circuit unit and a ground and operating in a linear region; and a switching circuit unit including a plurality of switch elements for selecting several MOSFETs previously selected from among the plurality of MOSFETs of the MOSFET circuit unit, respectively. | 05-16-2013 |
20130234773 | FINE RF TRANSCEIVER DC OFFSET CALIBRATION - An implementation relates to compensating DC offset in a signal path. The signal path may have a plurality of stages, where for each stage a fine DC compensation is performed by introducing a fine DC compensation signal into the signal path of the stage by way of a compensation analog to digital converter. | 09-12-2013 |
20130300484 | OFFSET-COMPENSATED ACTIVE LOAD AND METHOD - In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load. | 11-14-2013 |
20130314141 | SIGNAL PROCESSING CIRCUIT - The present disclosure relates to a signal processing circuit. The signal processing circuit includes a signal selection module, an offset module, and an amplifier module. The signal selection module is configured to select one from a plurality of input signals for outputting at least one first output signal. The voltage offset module is configured to output an offset voltage. The amplifier module, coupled to the signal selection module and the voltage offset module, is configured to ample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal. | 11-28-2013 |
20130328609 | BACKGROUND TECHNIQUES FOR COMPARATOR CALIBRATION - A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted. | 12-12-2013 |
20140043085 | Feedback Control Circuit for a Hall Effect Device - A feedback control circuit comprises an adjustable element, a main signal path and a feedback control loop. The adjustable element is configured to offset a signal in accordance with an offset control signal and output an offset signal. The main signal path comprises a first comparator to process the offset signal to output a main signal. The feedback control loop comprises a second comparator to process the offset signal to output a tracking signal, a first signal evaluator to evaluate the tracking signal and a first controller to output the offset control signal based on the evaluated tracking signal. The feedback control loop further comprises a second signal evaluator to detect a difference between a signal property of the main signal and the tracking signal and a second controller to control one of the comparators or the adjustable element such that the difference is reduced. | 02-13-2014 |
20140062569 | CONTINUOUSLY SELF-CALIBRATED LATCHED COMPARATOR - A comparator apparatus includes an amplifier and one or more latched comparators connected to the amplifier that compares input voltage signals to predefined reference voltage signals. The comparator apparatus includes an offset that limits the minimum input differential voltage signal with respect to the predefined voltage signals. A calibration component is electrically connected to the latched comparator and assists in continuously measuring and compensating the offset. | 03-06-2014 |
20140077860 | METHOD AND APPARATUS FOR PERFORMING OFFSET ADJUSTMENT UPON DYNAMIC COMPARATOR - An offset adjustment circuit of a dynamic comparator has a detection unit and a control unit. The detection unit detects whether a comparator offset possessed by the dynamic comparator is deviated from a target offset setting, and accordingly generates a detection result. The control unit adjusts a voltage setting of at least one input received by the dynamic comparator when the detection result indicates that the comparator offset is deviated from the target offset setting. | 03-20-2014 |
20140118048 | Offset Cancel Circuit - An offset cancel circuit includes a first amplifying section, a second amplifying section, a third resistor connected between a non-inverting input terminal of the first amplifying section and a non-inverting input terminal of the second amplifying section, and a current source. In the offset cancel circuit, the current source causes a constant current to flow through the third resistor to cancel an offset voltage from output signals of first and second amplifying sections, the constant current corresponding to the offset voltage contained in first and second output signals output from a bridge resistance type sensor. | 05-01-2014 |
20140191790 | OFFSET CANCELLING CIRCUIT AND METHOD - When a voltage is applied from outside such that a current flowing in a Hall element is switched, each of a plurality of capacitors is charged with an output voltage of the Hall element in each state. A dummy switching element is connected to a switching element which connects the plurality of capacitors in parallel to each other, the dummy switching element and the switching element being controlled to be switched ON and OFF exclusively with respect to each other. | 07-10-2014 |
20140253205 | APPARATUS FOR CONTROLLING COMPARATOR INPUT OFFSET VOLTAGE - An apparatus to remove an input offset voltage of a comparator circuit includes an input voltage offset capacitor, control logic to charge and discharge the capacitor to provide an offset cancelation voltage. The offset cancellation voltage removes the input offset voltage of the comparator dependent upon an output of the comparator circuit. A switching arrangement controlled by the control logic switches signals between the capacitor and the control logic. | 09-11-2014 |
20140266378 | METHOD FOR SETTING OFFSET GAIN OF ANALOG OUTPUT MODULE - A method for setting an offset gain of analog output module configured to convert a digital signal outputted from an MPU (Micro Processing Unit) to an analog signal and to output the converted analog signal is proposed, the method including outputting, by the MPU, a digital signal value to the analog output module, calculating an offset gain by measuring, by the analog output module, an analog signal value outputted by receipt and conversion of the digital signal value, and entering the measured analog signal value to an offset gain inverse function preset by the MPU, and setting the offset gain of the analog output module as the calculated offset gain. | 09-18-2014 |
20140266379 | SEMICONDUCTOR DEVICE - A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized. | 09-18-2014 |
20140368250 | METHOD AND SYSTEM FOR DELTA DOUBLE SAMPLING - An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples. | 12-18-2014 |
20150054559 | DC RESTORATION FOR SYNCHRONIZATION SIGNALS - In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal. | 02-26-2015 |
20150054560 | DC Offset Correction with Low Frequency Signal Support Circuits and Methods - DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed. | 02-26-2015 |
20150077167 | ADAPTIVE ONLINE FILTER FOR DC OFFSET ELIMINATION - A phase angle detector with a PLL, a power converter, and a method for reducing offsets in an input signal, in which an adaptive offset processor selectively removes a DC offset component from the input signal to generate a modified signal including a fundamental frequency component and higher order harmonics of the input signal with the DC offset component removed, and the PLL provides a phase angle signal at least partially according to the modified signal. | 03-19-2015 |
20150091630 | RF POWER DETECTOR AND DETECTION METHOD - The invention provides an RF detection circuit and method using an envelope detector having an output connected to a first input of a differential amplifier and a reference storage capacitor to a second input of the differential amplifier. In a preferred implementation of the calibration mode, there is initial discharging of a reference storage capacitor, high speed charging of the reference storage capacitor until the differential amplifier output toggles, then slower discharging of the reference storage capacitor until the differential amplifier output toggles again. The resulting voltage is stored on the reference storage capacitor for use in a subsequent detection mode. This provides storage of an offset voltage which calibrates both the envelope detector differential amplifier functions. | 04-02-2015 |
20150097610 | METHOD AND SYSTEM FOR DELTA DOUBLE SAMPLING - An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples. | 04-09-2015 |
20150109044 | VARIABLE AMPLITUDE SIGNAL GENERATORS FOR GENERATING A SINUSOIDAL SIGNAL HAVING LIMITED DIRECT CURRENT (DC) OFFSET VARIATION, AND RELATED DEVICES, SYSTEMS, AND METHODS - Embodiments disclosed include variable amplitude signal generators for generating a sinusoidal signal having limited direct current (DC) offset variation and related devices and methods. Instead of employing a single pulse width modulation (PWM) signal to generate a sinusoidal signal, in one embodiment, a circuit is provided that generates two PWM signals. The first PWM signal is a high-to-low PWM signal, where the active state is a lower signal level. The second PWM signal is a low-to-high PWM signal where active state is a higher signal level. The first and second PWM signals are combined to provide a summed signal, which is filtered to generate a sinusoidal signal. The DC offset of the first PWM signal varies inversely to the DC offset of the second PWM signal. In this manner, distortions caused by variations in the DC offset present in the generated sinusoidal signal are limited (i.e., reduced or eliminated). | 04-23-2015 |
20150130526 | Compensated Temperature Variable Resistor - A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement DC gain compensation using a programmable variable resistance. A MOS transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations. An integrated CMOS-based variable resistor may be thereby used for an analog adjustable attenuator. Master and slave CMOS transistors may be operated in linear mode, and temperature effects on the linear transistors may be compensated for by using an integral loop controller (current controller) configured around the master MOS transistor. Circuits implemented with the compensated variable resistance have a wide range of adjustment with a control voltage, and may be used in the front-end (circuits) of an oscilloscope or digitizer, or in any other circuit and/or instrumentation benefitting from an adjustable attenuator. | 05-14-2015 |
20150303903 | AUTOMATIC GAIN AND OFFSET COMPENSATION FOR AN ELECTRONIC CIRCUIT - Gain offset and voltage offset compensation for a controllable gain element of a circuit is effected in response to a gain offset value and voltage offset value. A current operating condition of the circuit is sensed and compared to a nominal operating condition. If the current operating condition is outside the nominal operating condition by more than a threshold, a calibration operation to set the gain and voltage offset values is performed. The gain offset value is selected as a function of the sensed current operating condition. With respect to the voltage offset, differential input terminals of the controllable gain element are shunted and the output is measured. The measured output value of the controllable gain element is applied as the voltage offset value. The operating conditions at issue may be one or more of supply voltage and temperature. | 10-22-2015 |
20150303904 | SYSTEMS AND METHODS FOR GAIN AND OFFSET CONTROL - A method for setting an initial gain and an initial offset for an automatic gain and offset controller (AGOC) is described. The method includes determining a gain level at which a signal does not under-saturate or over-saturate an input to an analog-to-digital converter (ADC) by performing a binary search over a fixed set of gain levels while an offset is fixed. The method also includes determining an offset correction to bring an unmodulated carrier level at an output of the ADC to a target level. The method may also include updating the gain and the offset in response to changes in a signal level. | 10-22-2015 |
20150358006 | METHOD FOR DETECTING HYSTERESIS CHARACTERISTIC OF COMPARATOR AND SEMICONDUCTOR DEVICE - A method for detecting a hysteresis characteristic of a comparator, include: causing a controller to control an offset adjuster configured to adjust an offset amount of the comparator; causing the controller to change the offset amount from a first value toward a second value and detect a third value when a logic level of a signal output from the comparator is changed; causing the controller to change the offset amount from the second value toward the first value and detect a fourth value when the logic level is changed; and causing the controller to detect the hysteresis characteristic of the comparator based on a first difference between the third value and the fourth value. | 12-10-2015 |
20160065181 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system includes a first semiconductor device including an offset signal generation circuit configured to compare at least one sensing code and a temperature code and generate an input offset signal, and a second semiconductor device including a temperature code generation circuit configured to be inputted with the input offset signal, compare a reference voltage controlled according to the input offset signal and a temperature signal, and generate the temperature code. | 03-03-2016 |
20160094209 | METHOD AND CIRCUIT FOR ELIMINATING TRANSFORMER SATURATION IN THE PRESENCE OF DC OFFSET VOLTAGE - A DC offset voltage in an AC input voltage to a transformer and associated saturation current are eliminated by the placement of an anti-parallel diode pair circuit in series between a source of the AC input voltage and a primary winding of the transformer. The anti-parallel diode pair circuit has an input coupled to an output by parallel connected oppositely biased branch diode circuits. Each branch diode circuit has at least one diode where the diode of one such branch diode circuit is biased in one direction and the diode of the other such branch diode circuit is biased in an opposite direction and each branch diode circuit has the same number of diodes as the other branch diode circuit. | 03-31-2016 |
20160098047 | VOLTAGE MONITORING SYSTEM - An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal. | 04-07-2016 |
20160112037 | CONTROL CIRCUIT FOR USE WITH A SENSOR, AND MEASUREMENT SYSTEM INCLUDING SUCH A CONTROL CIRCUIT - A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals. | 04-21-2016 |
20160142047 | SEMICONDUCTOR DEVICE - A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized. | 05-19-2016 |