Class / Patent application number | Description | Number of patent applications / Date published |
327295000 | Plural outputs | 75 |
20080265967 | INTEGRATED CIRCUIT FOR CLOCK GENERATION FOR MEMORY DEVICES - A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK | 10-30-2008 |
20080303575 | PULSE GENERATING CIRCUIT AND UWB COMMUNICATION SYSTEM - A pulse generating circuit includes a starting circuit which generates m (two or larger integer) starting signals at predetermined time intervals based on a generation starting signal, and m pulse wave generating sub circuits which have the same characteristics and generate pulse waves having pulse width Pw for n cycles (n: 1 or larger integer) based on the respective m starting signals. | 12-11-2008 |
20080315933 | PULSE SYNTHESIS CIRCUIT - A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node. | 12-25-2008 |
20090009228 | CLOCK GENERATING APPARATUS - A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator. | 01-08-2009 |
20090072877 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a first subordinate clock tree | 03-19-2009 |
20090102535 | CLOCK SIGNAL CIRCUIT FOR MULTIPLE LOADS - A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2. | 04-23-2009 |
20090115486 | Apparatus and method for generating multi-phase clocks - An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal. | 05-07-2009 |
20090121767 | SIGNAL PROCESSING APPARATUS - The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f | 05-14-2009 |
20090128213 | INTEGRATED CIRCUIT CLOCK STRUCTURE - An integrated circuit includes first and second circuits, and a clock structure. The clock structure consists of a crystal oscillation circuit, a plurality of buffers, and a plurality of clock generating modules. An input of each of the plurality of buffers is coupled to receive a reference clock signal from the crystal oscillation circuit. Each of the plurality of clock generating modules is coupled to a corresponding one of the plurality of buffers and, when enabled, generates a clock signal. | 05-21-2009 |
20090134926 | MULTI-PHASE NEGATIVE DELAY PULSE GENERATOR - A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have a first negative delay property respectively and of which an even number is ring-coupled; and a second delay block including second unit blocks which have a second negative delay property respectively and of which even number is ring-coupled. The number of the first unit block and the number of the second unit block are the same. A plurality of output nodes is formed based on one-to-one sharing between the first unit block and the second unit block having output signals of different level. Each output node outputs a pulse generated by racing the output signals of different level to each other which are provided from the first unit block and the second unit block connected to the each output node. | 05-28-2009 |
20090146720 | PULSE GENERATOR - A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent. | 06-11-2009 |
20090153215 | Clock Distribution Circuit - A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values. | 06-18-2009 |
20090174455 | EXPLICIT SKEW INTERFACE FOR MITIGATING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE - Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise. | 07-09-2009 |
20090179680 | METHOD AND APPARATUS FOR IMPLEMENTING BALANCED CLOCK DISTRIBUTION NETWORKS ON ASICS WITH VOLTAGE ISLANDS FUNCTIONING AT MULTIPLE OPERATING POINTS OF VOLTAGE AND TEMPERATURE - A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island. | 07-16-2009 |
20090243690 | SINGLE-CLOCK-BASED MULTIPLE-CLOCK FREQUENCY GENERATOR - In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency. | 10-01-2009 |
20090267674 | Clock control circuit and semiconductor memory device using the same - A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control signal. | 10-29-2009 |
20090302921 | APPARATUS AND METHOD FOR GENERATING CLOCK SIGNALS OF SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for generating a clock signal of a semiconductor Integrated circuit includes a first clock driver block configured to generate a plurality of first clock signals, a second clock driver block configured to generate a plurality of second clock signals, and a controller configured to stop an operation of at least one of the first clock driver block and the second clock driver block when the semiconductor Integrated circuit is in a predetermined operational state. | 12-10-2009 |
20090322399 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 12-31-2009 |
20100001778 | A/B-Phase Signal Generator, RD Converter and Angle Detection Unit - An A/B-phase signal generator wherein an up/down count unit | 01-07-2010 |
20100019823 | Semiconductor integrated circuit and control signal distributed method - A semiconductor integrated circuit includes a plurality of areas, each of which generates phase clocks in accordance with an external clock and control signals and performs a predetermined process assigned to each of the phase clocks. The semiconductor integrated circuit includes a control signal distributing unit that adjusts a timing at which the control signal is turned ON or OFF for each of the areas and distributes the adjusted control signals to the plurality of areas so that the plurality of areas do not perform a same process at a same timing. | 01-28-2010 |
20100085099 | MULTI-PHASE SIGNAL GENERATOR AND METHOD - Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals. | 04-08-2010 |
20100085100 | Low-Power Clock Generation and Distribution Circuitry - A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal. | 04-08-2010 |
20100109738 | Gate driver and method for making same - A gate driver for use in a liquid crystal display has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line pulse to a row of pixels in the liquid crystal display. The gate-line pulse has a front pulse and a rear pulse and the shift register has a front-pulse generating part and a rear-pulse generating part for generating to corresponding pulse. Each of the pulse generating parts has a first pull-up circuit to generate a voltage level to keep a switching element in a second pull-up circuit conducting so as to generate a front or rear pulse, in response to a corresponding clock signal, and two pull-down circuits, in response to the voltage level, to allow the front or rear pulse to be generated only at a pull-down period. | 05-06-2010 |
20100134171 | CLOCK GENERATION CIRCUIT AND INTEGRATED CIRCUIT - A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal. | 06-03-2010 |
20100148841 | Multiphase clock for superconducting electronics - A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc. | 06-17-2010 |
20100148842 | MULTI-PHASE CLOCK SIGNAL GENERATING CIRCUIT HAVING IMPROVED PHASE DIFFERENCE AND A CONTROLLING METHOD THEREOF - A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals. | 06-17-2010 |
20100164587 | DIGITAL SYNCHRONOUS CIRCUIT - A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays. | 07-01-2010 |
20100182066 | Clock Generating Circuit - A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value, a first (second) charge/discharge-control circuit to output a first (second) control signal for switching between the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or second (fourth) reference voltage higher than the first (third) reference voltage, and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal, the first capacitor having one end connected to a first potential, the second capacitor having one end to which the main clock is input. | 07-22-2010 |
20100253409 | CLOCK GENERATION SYSTEM AND CLOCK DIVIDING MODULE - A clock gating system includes a clock divider, a first clock gating unit and a second clock gating unit. The clock divider is employed to generate clock signals with different frequencies. The first clock gating unit is configured for generating a gated clock to a first functional block, while the second clock gating unit is configured for generating a gated clock to a second functional block. Logically the first clock gating unit and the second clock gating unit are included in the first functional block and the to second functional block, respectively, and in physical layout the first clock gating unit and the second clock gating unit are disposed close to the clock divider. | 10-07-2010 |
20100321080 | PULSE WIDTH MODULATION CONTROL SYSTEM - A PWM control system includes a multi-phase PWM controller and at least one single-phase PWM controller. The multi-phase PWM controller is capable of generating a multi-phase PWM signal. The at least one single-phase PWM controller is capable of generating a single-phase PWM signal. A phase difference between the single-phase PWM signal and the multi-phase signal is greater than 0 degree and less than 180 degree. | 12-23-2010 |
20100327938 | SYSTEM AND METHOD FOR CLOCK CONTROL FOR POWER-STATE TRANSITIONS - Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement ( | 12-30-2010 |
20110012662 | SUB-BEAM FORMING TRANSMITTER CIRCUITRY FOR ULTRASOUND SYSTEM - Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals. | 01-20-2011 |
20110089987 | MULTI-PHASE SIGNALS GENERATOR - A multi-phase signals generator is disclosed. The multi-phase signals generator mentioned above includes a frequency divider and N delay circuits. The frequency divider receives a clock signal and divides a frequency of the clock signal to generate a divided frequency clock signal. The N delay circuits are connected in series. The delay circuit connected in a first stage receives the divided frequency clock signal. The delay circuit connected in an i | 04-21-2011 |
20110109367 | MULTI-PHASE DUTY-CYCLE CORRECTED CLOCK SIGNAL GENERATOR AND MEMORY HAVING SAME - Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals. | 05-12-2011 |
20110215855 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit has: an operational amplifier, first to third voltage generating units, a first resistor and a second resistor. The operational amplifier generates a control signal depending on first and second voltages that are input thereto. The first voltage generating unit generates the first voltage depending on the control signal and outputs the first voltage from a first node. The second voltage generating unit generates the second voltage depending on the control signal and outputs the second voltage from a second node. The third voltage generating unit generates a third voltage as a reference voltage depending on the control signal and outputs the third voltage from a reference voltage output node. The first resistor is connected between the first node and the reference voltage output node. The second resistor connected between the second node and the reference voltage output node. | 09-08-2011 |
20110234286 | Three-Phase Generator for Motor Control - A pulse generator that can generate pulses separated by 120 degrees phase on each of three separate phase output leads for use with a 3-phase motor power driver. These output pulses can be of any desired frequency and voltage. In a particular embodiment of the invention, the phase output pulses take a logic level of 0-12 volts (12 volts peak) with an adjustable frequency of around 250 Hz and a duty cycle of around 50%. This combination of parameters is ideal for driving a 3-phase motor in a vehicle application. Any combination of pulse width or duty cycle, output level and frequency is within the scope of the present invention. | 09-29-2011 |
20110241749 | Clock Distribution Circuit - A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values. | 10-06-2011 |
20110248763 | CHARGE PUMPING CIRCUIT - A charge pumping circuit is provided to regulate the amount of charge to be pumped according to a driving voltage to reduce the loss of power and increase charge pumping efficiency. The charge pumping circuit includes: a driving voltage sensing unit sensing a driving voltage to generate one or more sensing signals for determining the amount of charge to be pumped; a multi-level clock generation unit generating a pair of clock signals each having an amplitude corresponding to a signal value of each of the one or more sensing signals; and a charge pumping unit charging the pair of clock signals to generate a charged voltage, adding the charged voltage to the driving voltage, and outputting the same. | 10-13-2011 |
20120013380 | APPARATUS FOR GENERATING A PLURALITY OF DIFFERENT VOLTAGE LEVEL CLOCK SIGNALS - A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level. | 01-19-2012 |
20120086491 | INTEGRATED JITTER COMPLIANT CLOCK SIGNAL GENERATION - Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals. | 04-12-2012 |
20120092054 | Charge pump with low noise and high output current and voltage - The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time. | 04-19-2012 |
20120146701 | CLOCK SYSTEM AND METHOD FOR COMPENSATING TIMING INFORMATION OF CLOCK SYSTEM - A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered. | 06-14-2012 |
20120176175 | APPARATUS AND SYSTEM TO SUPPRESS ANALOG FRONT END NOISE INTRODUCED BY CHARGE-PUMP - An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal. | 07-12-2012 |
20120182058 | NEGATIVE CHARGE PUMP - A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node. | 07-19-2012 |
20120212275 | Gate Driving Circuit - A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses. | 08-23-2012 |
20140002167 | DIFFERENTIAL CLOCK SIGNAL GENERATOR | 01-02-2014 |
20140152366 | CONCURRENT TRUE AND COMPLEMENT SIGNAL GENERATION - A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal. | 06-05-2014 |
20140247080 | MULTI-LEVEL CLOCK SIGNAL DISTRIBUTION NETWORK AND INTEGRATED CIRCUIT - A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one. | 09-04-2014 |
20140266377 | HYBRID ANALOG/DIGITAL POINT-OF-LOAD CONTROLLER - In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain. | 09-18-2014 |
20140292391 | SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING DEVICE AND IAMGE FORMING APPARATUS - A semiconductor integrated circuit includes an identification information storage, an intermediate clock generator and an operating clock generator. The identification information storage stores identification information of the semiconductor integrated circuit. The intermediate clock generator generates an intermediate clock having a frequency higher than that of a reference clock using the reference clock input to the semiconductor integrated circuit from the outside of the semiconductor integrated circuit. The operating clock generator generates the operating clock having a frequency higher than that of the reference clock and lower than that of the intermediate clock in synchronization with a timing allotted according to the identification information stored in the identification information storage, using the intermediate clock. | 10-02-2014 |
20140333364 | TUNABLE CLOCK DISTRIBUTION SYSTEM - A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented. | 11-13-2014 |
20150070067 | 3D CLOCK DISTRIBUTION CIRCUITS AND METHODS - An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via. | 03-12-2015 |
20160098062 | TIMING CONTROL WITH BODY-BIAS - Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased. | 04-07-2016 |
20160173075 | CLOCK GENERATOR AND METHOD OF ADJUSTING PHASES OF MULTIPHASE CLOCKS BY THE SAME | 06-16-2016 |
327296000 | Plural clock outputs with multiple inputs | 11 |
20080278211 | USE OF MULTIPLE VOLTAGE CONTROLLED DELAY LINES FOR PRECISE ALIGNMENT AND DUTY CYCLE CONTROL OF THE DATA OUTPUT OF A DDR MEMORY DEVICE - A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data. | 11-13-2008 |
20090015311 | LOW SKEW CLOCK DISTRIBUTION TREE - A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized. | 01-15-2009 |
20090251189 | Multi-Phase Phase Interpolator - A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator. | 10-08-2009 |
20100090742 | MULTIPLE PHASE PULSE GENERATOR - In one embodiment of the present invention, a multiple phase pulse generator includes n stages, where each stage includes a first sub-stage and a second sub-stage. The first sub-stage includes a first memory element and the second sub-stage includes a second memory element. The first memory element of each stage is arranged to be set by the preceding stage. The first sub-stage is arranged to supply a stage output pulse while the first memory element is set. The second memory element is arranged to be set by the stage output pulse. The second sub-stage is arranged to hold the first memory element reset after the stage output pulse while the second memory element is set. | 04-15-2010 |
20100134172 | CHARGE-SHARING METHOD AND DEVICE FOR CLOCK SIGNAL GENERATION - A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low. | 06-03-2010 |
20100271101 | Master Clock Generation Unit for Satellite Navigation Systems - A master clock generation unit for satellite navigation systems, comprises a plurality of frequency inputs for receiving a respective atomic clock signal, each having a first or a second reference frequency, and a number of frequency converters each having an input connected to one of the frequency inputs and an output. Each of the frequency converters receives an offset frequency (selected according to the first and second reference frequency at the assigned frequency input) from at least one frequency synthesizer, for providing the same intermediate frequency at each of the converter outputs. A switching matrix is connected to each of the converter outputs for selecting one of the intermediate frequencies as a primary clock provided at a first matrix output, and another of the intermediate frequencies as a secondary clock provided at a second matrix output. A frequency generator having an input connected to the first matrix output and connected to a number of frequency outputs of the master clock generation unit, derives an output reference frequency from the primary clock, and provides it at the frequency outputs. A phase meter having a first meter input connected to the first matrix output and a second meter input connected to the second matrix output, determines a phase difference between the primary and the secondary clock for detecting abnormal behavior. | 10-28-2010 |
20130135023 | PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER - A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply potential is applied to one of transistors connected to a second output terminal. Thus, power consumed by discharge and charge of the transistor included in the second output terminal can be reduced. Further, since a potential is supplied from a power source to the second output terminal, sufficient charge capability can be obtained. | 05-30-2013 |
20130162316 | PULSE GENERATION CIRCUIT, BURST ORDER CONTROL CIRCUIT, AND DATA OUTPUT CIRCUIT - A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses. | 06-27-2013 |
20140002168 | SIGNAL TRANSMISSION CIRCUIT, INTEGRATED CIRCUIT AND ELECTRIC DEVICE INCLUDING THEREOF FOR TRANSMITTING A PLURALITY OF SIGNALS EACH HAVING DIFFERENT TRANSMISSION SPEED | 01-02-2014 |
20140070865 | DEVICE AND METHOD FOR A MULTIPLEXOR/DEMULTIPLEXOR RESET SCHEME - Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted. | 03-13-2014 |
20140300399 | PULSE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed. | 10-09-2014 |
327297000 | Clock bus | 10 |
20080238519 | Signaling circuit and method for integrated circuit devices and systems - Integrate circuit systems and semiconductor devices for generating, transmitting, receiving, and manipulating clock and/or data signals. A semiconductor device including a clock circuit having field effect transistors and a clock driver circuit having bipolar junction transistors is disclosed. The clock circuit may provide a first clock output having a first voltage swing. The clock driver circuit may receive the first clock output and provide a second clock output having a second voltage swing substantially less than the first voltage swing. The field effect transistors can be junction field effect transistors or insulated gate field effect transistors, or the like. The system/devices further including a translator circuit, for translating signals with a lower voltage swing into signals with a higher voltage swing, and a circuit block, for operating at such higher voltage swing. Further included are global and local wiring networks for communicating the signals between and among the individual circuits or system components. | 10-02-2008 |
20090079488 | SEMICONDUCTOR DEVICE - Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located. | 03-26-2009 |
20090140788 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a plurality of clock tree cells arranged in a tree structure on clock signal lines transmitting a clock signal, the plurality of clock tree cells forming a clock tree. The clock tree cells include first power supply lines connected to the clock tree cells, second power supply lines connected to logic circuits receiving a clock signal supplied from the clock tree, and a plurality of power supply pads connected to the first power supply lines and the second power supply lines. | 06-04-2009 |
20100148843 | BOW TIE CLOCK DISTRIBUTION - A clock distribution network includes: a primary clock signal and a distribution tree coupled to the primary clock signal. The distribution tree derives a plurality of separate clock signals from the primary clock signal and provides each of the plurality of separate clock signals to each of a plurality of loads. The distribution tree comprises a plurality of bow tie elements. | 06-17-2010 |
20100188130 | LOW RC LOCAL CLOCK DISTRIBUTION - A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors. | 07-29-2010 |
20100231282 | System and Method of Clock Tree Synthesis - In a particular embodiment, a method of generating an advanced gating cell clock tree includes determining a timing margin for a path between a clock gating cell and a digital data storage element such as a latch or flip flop. The circuit contains a clock source and when the timing margin for the path meets a predetermined threshold, the clock gating cell is automatically moved closer to the clock source. In a particular embodiment, the timing margin is automatically determined. A clock tree synthesis is performed to insert one or more buffers into the path and create an advanced gating cell clock tree. | 09-16-2010 |
20100308885 | METHOD AND SYSTEM FOR CLOCK DISTRIBUTION UTILIZING LEAKY WAVE ANTENNAS - Methods and systems for clock distribution utilizing leaky wave antennas (LWAs) in a wireless device are disclosed and may include configuring voltage-controlled oscillators (VCO) to generate one or more clock signals at desired clock frequencies and configuring LWAs at a resonant frequency corresponding to the clock frequencies, which may be generated at the desired clock frequencies utilizing the VCO. The clock signals may be communicated via LWAs in the wireless device and may be amplified utilizing one or more low-noise amplifiers. A resonant frequency of the LWAs may be configured utilizing micro-electro-mechanical systems (MEMS) deflection. LWAs may be configured to enable beamforming. One or more of the LWAs may comprise microstrip or coplanar waveguides, wherein a cavity height of the LWAs is dependent on spacing between conductive lines in the waveguides. The LWAs may be integrated in one or more integrated circuits, integrated circuit packages, and/or printed circuit boards. | 12-09-2010 |
20120032721 | CLOCK TREE FOR PULSED LATCHES - The invention concerns a computer implemented method of circuit conception of a clock tree ( | 02-09-2012 |
20130194019 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING DEVICE INCLUDING THE SAME - The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks. | 08-01-2013 |
20140240021 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |