| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327237000 | Variable or adjustable | 46 |
| 20090195286 | PHASE SHIFTING USING ASYMMETRIC INTERPOLATOR WEIGHTS - Illustrative embodiments provide an apparatus for phase shifting to produce uniform phase steps in a predictable manner to improve the linearity of conversion. The apparatus comprises a phase selector for selecting two or more phases to create selected phases and a phase interpolator capable of receiving the selected phases. The apparatus further comprises a set of digital to analog converter cells connected to the phase interpolator, wherein interpolator weight distribution among the set of digital to analog converter cells is non-linear, and a thermometer code in communication with the set of digital to analog converter cells, wherein the thermometer code adjusts output of the set of digital to analog converter cells to phase shift the selected phases. | 08-06-2009 |
| 20130033296 | PHASE SHIFTER - A 0-to-90-degree phase shifter ( | 02-07-2013 |
| 20100066424 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock. | 03-18-2010 |
| 20090115483 | PHASE JUMP SEQUENCER ARCHITECTURE - A method for controlling an output phase of a phase interpolator, by forming an M bit control word, designating N bits of the control word as a fractional number portion, designating M-N bits of the control word as a whole number portion, adjusting a phase jump of the phase interpolator at a designated clock cycle by a first number of phases as designated by the whole number portion plus a second number of phases as designated by the fractional number portion. The designated clock cycle can be identified by numbering clock cycles with a count value from counter having a repeating period of 2 | 05-07-2009 |
| 20130063196 | PHASE INTERPOLAR, RECEPTION CIRCUIT AND INFORMATION PROCESSING APPRATUS - A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range. | 03-14-2013 |
| 20110291727 | DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. | 12-01-2011 |
| 20100123502 | SYSTEM FOR PROVIDING A SUBSTANTIALLY UNIFORM POTENTIAL PROFILE - A system for providing at least two output signals to produce a substantially uniform potential profile includes a signal generator adapted to emit a frequency at least about 30 megahertz, a splitter in communication with the signal generator, and a signal manipulator in communication with the splitter. The splitter is adapted to split the signal of the signal generator into the two output signals, and the signal manipulator is adapted to manipulate a phase, a gain, or an impedance of the two output signals. The signal manipulator manipulates the two output signals so that the two output signals produce the substantially uniform potential profile. | 05-20-2010 |
| 20110193606 | RADIO FREQUENCY MODULATOR AND METHOD THEREOF - A radio frequency (RF) modulator includes: converting means for up-converting a first and second baseband signals into a first and second up-converted signals with a reference clock, wherein a phase difference between the first and second baseband signals substantially equals 180°/N; and combining means for combining the first and second up-converted signals to generate an output signal. | 08-11-2011 |
| 20120119807 | PHASE INTERPOLATOR, SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF - Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value. | 05-17-2012 |
| 20090033395 | MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT - Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal. | 02-05-2009 |
| 20090231009 | HIGH-RESOLUTION LOW-INTERCONNECT PHASE ROTATOR - High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed. | 09-17-2009 |
| 20100188127 | SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD - A signal adjusting system includes: a signal generating device for generating a plurality of output signals according to a plurality of pre-output signals, a plurality of signal transmitting paths being coupled to the signal generating device for transmitting the plurality of output signals; and a controlling device coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to a first output signal and a second transmitted signal corresponding to a second output signal, and detecting a phase different between the first transmitted signal and the second transmitted signal to generate a detected result to the signal generating device, wherein the signal generating device adjusts the phase difference between the first output signal and the second output signal according to the detected result. | 07-29-2010 |
| 20090108898 | METHODS AND APPARATUS FOR IMPROVED PHASE SWITCHING AND LINEARITY IN AN ANALOG PHASE INTERPOLATOR - Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal. | 04-30-2009 |
| 20100148838 | WIDE RANGE DELAY CELL - A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits. | 06-17-2010 |
| 20110050312 | MULTI-PHASE CLOCK GENERATION CIRCUIT - A multi-phase clock generation circuit including a phase interpolation circuit that generates and outputs an interpolation signal based on first and second clock signals, the interpolation signal interpolating a phase between output clock signals corresponding to the first and the second clock signals, and a control circuit that generates a first control signal to adjust a phase of the interpolation signal and outputs the first control signal to the phase interpolation circuit, in which the control circuit includes a timing detection circuit that detects a timing of a change in a logic value of the interpolation signal, and a control signal generation circuit that generates the first control signal according to a detection result in the timing detection circuit. | 03-03-2011 |
| 20100301916 | CLOCK DISTRIBUTION CIRCUIT AND LAYOUT DESIGN METHOD USING SAME - A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit. | 12-02-2010 |
| 20090322395 | TRANSMISSION PATH DRIVING CIRCUIT - A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit | 12-31-2009 |
| 20100283525 | PHASE CONTROL DEVICE AND DATA COMMUNICATION SYSTEM USING IT - A phase control device that adjusts a phase of a clock receives a first clock, a second clock and a control code. The phase control device includes phase adjusters (PI- | 11-11-2010 |
| 20100019816 | MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES - Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay. | 01-28-2010 |
| 20120062299 | FREQUENCY DETECTION DEVICE, FREQUENCY DETECTION METHOD, CIRCUIT CONTROL DEVICE, CIRCUIT CONTROL METHOD, DELAY CIRCUIT CONTROL METHOD, AND DELAY CIRCUIT SYSTEM - Disclosed are a device and a method for comparing a detected frequency signal (first frequency signal) and a second frequency signal which is obtained by delaying the detected frequency, to determine whether the frequency transitioned to a predetermined area on high frequency side or reached a predetermined value on the upward direction side. The frequency detection device ( | 03-15-2012 |
| 20110187432 | SEMICONDUCTOR DEVICE - A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. | 08-04-2011 |
| 20120176174 | Systems and methods for precise generation of phase variation in digital signals - Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal. | 07-12-2012 |
| 20120299629 | PHASE EXCURSION/CARRIER WAVE FREQUENCY EXCURSION COMPENSATION DEVICE AND PHASE EXCURSION/CARRIER WAVE FREQUENCY EXCURSION COMPENSATION METHOD - In a phase excursion/carrier wave frequency excursion compensation device, increasing compensation processing speed using parallel processing deteriorates the transmission property. Thus, provided is a phase excursion/carrier wave frequency excursion compensation device comprising a signal dividing unit, a preprocessing compensation circuit, a plurality of post-processing compensation circuits, a signal combination unit, a correction amount calculation unit, and a signal correction unit, wherein the preprocessing compensation circuit and the post-processing compensation circuits calculate a phase compensation amount with respect to the input signal, and output the phase compensation amount and a compensation circuit output signal wherein the input signal is compensated by the phase compensation amount, the signal combination unit outputs rearranged signals by rearranging the compensation circuit output signals acquired from the post-processing compensation circuits in the order input to the signal dividing unit, the correction amount calculation unit calculates a correction amount on the basis of the phase compensation amount acquired from the preprocessing compensation circuit and the post-processing compensation circuits, and a signal correction unit corrects the phase of the rearranged signals using the correction amount. | 11-29-2012 |
| 20100231279 | Phase Shift Generating Circuit - A phase shift generation circuit has an edge detector, which receives an input pulse signal and outputs a first and a second edge signal denoting the time of occurrence of the first and second edges of the input pulse signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal, said a second clock signal having a frequency equal to the frequency of said first clock signal divided by the number N. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer, which receives the number of second clock pulses, the first edge signal and the first clock signal, and outputs a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The group is spaced by the number of second clock pulses. The circuit also has a second recycling timer, which receives the number of second clock pulses, the second edge signal and the first clock signal, and outputs a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The group is spaced by the number of second clock pulses. The circuit also comprises at least one flip flop with set and reset inputs. The set input receives a pulse from the second recycling timer, while the reset input receives a corresponding pulse from the first recycling timer. The flip flop generates a phase shifted output pulse. | 09-16-2010 |
| 20110248761 | Phase Adjustment Apparatus and Method for a Memory Device Signaling System - Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system. | 10-13-2011 |
| 327238000 | Quadrature related (i.e., 90 degrees) | 4 |
| 20110074482 | OSCILLATION SIGNAL GENERATOR FOR COMPENSATING FOR I/Q MISMATCH AND COMMUNICATION SYSTEM INCLUDING THE SAME - An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch and a communication system including the same are provided. The oscillation signal generator includes a first latch configured to generate an I oscillation signal, a second latch that is cross-coupled with the first latch and generates a Q oscillation signal, and a phase compensator connected to at least one of the first latch or the second latch. The phase compensator complementarily adjusts bias currents of the first and second I differential transistor pairs of the first latch and/or complementarily adjusts bias currents of the first and second Q differential transistor pairs of the second latch. Accordingly, the I/Q mismatch is compensated for without an additional device, so that the phase match between an I signal and a Q signal is improved in the communication system. | 03-31-2011 |
| 20090045861 | System and method for effectively implementing an IQ generator - A system and method for effectively implementing an IQ generator includes a master latch that generates an I signal and a slave latch that generates a Q signal. The master latch includes a master data circuit, a master latch circuit, and a master clock circuit. The slave latch includes a slave data circuit, a slave latch circuit, and a slave clock circuit. A cross-coupled current-source technique is used to compensate for certain device mismatches. A current source A generates an operating current A for the master clock circuit, the master data circuit, and the slave data circuit, and a current source B generates an operating current B for the slave clock circuit, the master latch, and the slave latch. In addition, resistors are utilized to provide fixed impedances to compensate for device mismatches between certain components in the master clock circuit and the slave clock circuit. | 02-19-2009 |
| 20110068843 | BAND ADJUSTMENT DEVICE OF POLYPHASE FILTER AND BAND ADJUSTMENT METHOD OF POLYPHASE FILTER - Provided is a base adjustment device and method of a polyphase filter that can reduce an area and power consumption, and operate at a high speed. The band adjustment device of the polyphase filter according to the present invention includes a voltage-controlled oscillator (VCO), a polyphase filter that inputs an output from the VCO, a mixer that receives an output from the polyphase filter, an envelope detection circuit (envelope detector) that inputs an output from the mixer, and a band control signal generation circuit that inputs an output from the envelope detector. | 03-24-2011 |
| 20120256673 | PHASE ADJUSTMENT CIRCUIT AND PHASE ADJUSTMENT METHOD - There is provided a circuit for adjusting phases of IQ local signals. As to a local signal A and a local signal B generated by a local signal generating unit for the purpose of generating IQ quadrature local signals, the local signal B in which the gain is adjusted is added to the output of the local signal A to obtain the local signal A | 10-11-2012 |
| 327239000 | Non-overlapping multiple outputs | 2 |
| 20090302918 | CLOCK SIGNAL GENERATION APPARATUS - A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components. | 12-10-2009 |
| 20110210778 | CLOCK GENERATION CIRCUIT AND INTEGRATED CIRCUIT - A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first delay element, and correlates with the propagation delay time of a second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal. | 09-01-2011 |
| 327240000 | Maintaining invariant amplitude | 1 |
| 20120286839 | Systems and Methods for a Continuous, Linear, 360-Degree Analog Phase Shifter - Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift. | 11-15-2012 |
| 327241000 | With counter or shift register | 2 |
| 20130027104 | LEVEL SHIFT CIRCUIT AND DISPLAY DEVICE PROVIDED WITH THE SAME - An object of the present invention is to provide a level shift IC with a reduced number of input signals over the conventional case. A level shift IC includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits. The different-phase signal generating unit generates, by the delay circuits, first and second delayed input signals from first and second input signals of different phases. Therefore, four input signals of different phases are obtained, and the amplitude converting unit increases the amplitudes of the input signals by the amplitude converting unit and thereby generates first to fourth output signals with different phases and increased amplitudes. | 01-31-2013 |
| 20090284295 | Timer for Low-Power and High-Resolution - The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals. | 11-19-2009 |
| 327243000 | With feedback | 4 |
| 20100060336 | SEMICONDUCTOR CIRCUIT - A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor. | 03-11-2010 |
| 20110006825 | Phase Control Circuit and Method for Optical Receivers - This invention relates to a phase control circuit for an optical receiver (1). The phase control circuit ( | 01-13-2011 |
| 20110148498 | DIGITAL QUADRATURE PHASE CORRECTION - Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal. | 06-23-2011 |
| 327245000 | Having multiple outputs | 1 |
| 20120262212 | MULTIPLE-PHASE CLOCK GENERATOR - A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2 | 10-18-2012 |
| 327246000 | With differential amplifier | 2 |
| 20100201421 | JITTER GENERATING CIRCUIT - A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit | 08-12-2010 |
| 20080265963 | CASCADED PHASE SHIFTER - The invention relates to a phase shifter which has at least two cascaded delay stages ( | 10-30-2008 |
| 327250000 | With active time delay element | 3 |
| 20100327931 | Wideband programmable phase shifting circuit - The wideband programmable phase shifting circuitry includes a charge pump, a comparator, and a voltage reference generator block. An input signal controls the charge pump which charges and discharges a capacitor connected to an output of the charge pump. The comparator continuously compares the voltage across the capacitor with a reference voltage, ratio of V | 12-30-2010 |
| 20100039152 | METHOD AND APPARATUS FOR ADAPTIVE CLOCK PHASE CONTROL FOR LSI POWER REDUCTION - Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit. | 02-18-2010 |
| 20120313683 | PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR - A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line. | 12-13-2012 |
| 327252000 | With passive time delay element | 3 |
| 20110291728 | PHASE SHIFTER AND POWER AMPLIFIER AND MAGNETIC RESONANCE IMAGING APPARATUS - A phase shifter is provided. The phase shifter includes a first phase shifter that is continuously adjustable within a range of 0 degrees to 90 degrees, two 4-way switches each configured to selectively switch on one of a capacitance, an inductance, an open circuit, and a short circuit under control of a control voltage, and a bridge. A first input end and a first output end of said bridge are respectively connected to a first 4-way switch of the two 4-way switches. A second input end of said bridge is connected to an output end of said first phase shifter or a second output end of said bridge is connected to an input end of said first phase shifter. | 12-01-2011 |
| 20110199141 | PHASE SHIFTER AND CONTROL METHOD THEREOF - Provided is a phase shifter having a high phase difference in a microwave band. The phase shifter includes a first phase shifting unit configured to receive an input signal having a predetermined frequency, receive a first control signal and a second control signal operating contrary to the first control signal, output the input signal as it is when the first control signal is activated, and output the input signal to have a lead phase as much as a predetermined phase, and a second phase shifting unit configured to receive a second signal outputted from the first phase shifting unit, receive the first control signal and the second control signal, output the second signal to have a lagged phase as much as a predetermined phase when the first control signal is activated, and output the second signal as it is when the second control signal is activated. | 08-18-2011 |
| 20100001776 | DIFFERENTIAL SIGNAL TRANSMITTING APPARATUS AND A TEST APPARATUS - Provided is a differential signal transmission apparatus that transmits a differential signal expressed by a potential difference between a positive signal and a negative signal, including a positive signal transmission line that transmits the positive signal; a negative signal transmission line that transmits the negative signal; and a delay compensating circuit that compensates for a time difference between the positive signal and the negative signal with a variable compensation time. | 01-07-2010 |
