Class / Patent application number | Description | Number of patent applications / Date published |
327210000 | CMOS | 36 |
20080284480 | SCAN FLIP-FLOP WITH INTERNAL LATENCY FOR SCAN INPUT - A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits. | 11-20-2008 |
20090039937 | Semiconductor Integrated Circuit with a Logic Circuit Including a Data Holding Circuit - A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit. | 02-12-2009 |
20090096501 | APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS - A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on. | 04-16-2009 |
20090128211 | NOISE FILTER CIRCUIT, NOISE FILTERING METHOD, THERMAL HEAD DRIVER, THERMAL HEAD, ELECTRONIC INSTRUMENT, AND PRINTING SYSTEM - A noise filter circuit includes a latch circuit that receives an input signal. The latch circuit includes first and second logic circuits (e.g., NAND circuits). The first and second NAND circuits are configured so that the capability of a P-type transistor that receives a set signal or a reset signal is lower than the capability of an N-type transistor that receives the set signal or the reset signal and the capability of an N-type transistor connected in series with the N-type transistor that receives the set signal or the reset signal (total capability). The noise filter circuit may include a waveform adjusting circuit that receives an output signal from the latch circuit. | 05-21-2009 |
20090134925 | APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES - A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor. | 05-28-2009 |
20090237136 | Pulse-Based Flip-Flop Having Scan Input Signal - A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal. A second pulse signal generator generates a second pulse signal in response to the scan enable signal and a scan input signal. A signal transmitter receives a data signal and transmits the data signal to a first node in response to either one of the first and second pulse signals. A signal latch unit receives the data signal transmitted to the first node, and latches and outputs the data signal in response to another one of the first and second pulse signals. | 09-24-2009 |
20090295447 | APPARATUS AND METHODS FOR A HIGH-VOLTAGE LATCH - Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described. | 12-03-2009 |
20100237921 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 09-23-2010 |
20110148497 | SEMICONDUCTOR DEVICE - An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies. | 06-23-2011 |
20110187431 | Voltage Level Translator Circuit - A voltage translator circuit ( | 08-04-2011 |
20130200935 | SEMICONDUCTOR DEVICE HAVING CMOS TRANSFER CIRCUIT AND CLAMP ELEMENT - A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal. | 08-08-2013 |
20130214838 | HIGH SPEED LEVEL SHIFTER FOR CONVERTING LOW INPUT VOLTAGE INTO WIDE-RANGE HIGH OUTPUT VOLTAGE - A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal. | 08-22-2013 |
20140111262 | SEMICONDUCTOR DEVICE - An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies. | 04-24-2014 |
20140375367 | PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES - In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low. | 12-25-2014 |
20150123723 | REDUNDANT CLOCK TRANSISTION TOLERANT LATCH CIRCUIT - Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described. | 05-07-2015 |
20150349769 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 12-03-2015 |
20150365075 | CIRCUIT SKEW COMPENSATION TRIGGER SYSTEM - A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew. | 12-17-2015 |
20160020754 | INTEGRATED CIRCUIT - An integrated circuit includes a latch block suitable for storing a signal through four or more even-numbered coupling lines inverted and driven alternately with each other, wherein the coupling lines are divided into two or more coupling line groups each including coupling lines inverted and driven to the same logic level, and a charge buffer block coupled between two or more coupling lines included in one of the coupling line groups and suitable for slowing down a charge movement speed therebetween. | 01-21-2016 |
20160079981 | HIGH-SPEED INVERTER AND METHOD THEREOF - A CMOS (complementary metal oxide semiconductor) inverter includes a PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first input signal via a first input terminal and output a first output signal via a first output terminal, an NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second input signal via a second input terminal and output a second output signal via a second output terminal, and a resistor configured to provide an isolation between the first output signal and the second output signal. In an embodiment, the first input signal is of a fast high-to-low transition but a slow low-to-high transition, and the second input signal is of a fast low-to-high transition but a slow high-to-low transition. A comparative method is also provided. | 03-17-2016 |
20160164504 | LATCH CIRCUIT - A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on. | 06-09-2016 |
327211000 | With clock input | 16 |
20080297220 | Method of forming a CMOS structure having gate insulation films of different thicknesses - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 12-04-2008 |
20090237137 | Flip-Flop Capable of Operating at High-Speed - A flip-flop is provided for minimizing an input-output (D-Q) delay. The flip-flop includes a pull-up unit that receives a signal from a first node, is connected between a power voltage source and a second node, and pulls-up a voltage of the second node. A pull-down unit receives the signal from the first node, is connected between a ground voltage source and the second node, and pulls-down the voltage of the second node. A latch unit is connected to the second node and latches and outputs a signal transferred to the second node. The pull-up unit pulls-up the second node in response to one of a clock signal and a pulse signal, and the pull-down unit pulls-down the second node in response to the other one of the clock signal and the pulse signal. | 09-24-2009 |
20090295448 | Radiation Hardened CMOS Master Latch With Redundant Clock Input Circuits and Design Structure Therefor - A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch. | 12-03-2009 |
20100315144 | Flip-Flop Circuits and System Including the Same - Flip-flop circuits including a dynamic input unit and a control clock generator are provided. The dynamic input unit precharges an evaluation node to a power supply voltage in a first phase of a clock signal, selectively discharges the evaluation node based on input data in a second phase of the clock signal, and compensates for voltage drop of the evaluation node in response to a first control clock signal. The control clock generator generates the first control clock signal and a second control clock signal based on at least the clock signal. | 12-16-2010 |
20110001536 | STATIC LATCH - A static latch includes a clock-based driver, an actuation circuit, and a weak latched unit. The clock-based driver includes first node, second node, a driving unit, first pass switch, and second pass switch. The driving unit drives the first node corresponding to first voltage in response to first level of an input signal and drives the second node having second voltage in response to second level of the input signal. The first pass switch drives an output node having a latched signal corresponding to the first voltage in response to the clock signal. The second pass switch drives the output node corresponding to the second voltage in response to the inverted clock signal. The actuation circuit drives the output node corresponding to the second voltage in response to the clock signal. The weak latch unit keeps the level of the latched signal when the static latch is disabled. | 01-06-2011 |
20110095800 | FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION - A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node. | 04-28-2011 |
20110248760 | Flip-Flop for Low Swing Clock Signal - The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node. | 10-13-2011 |
20120098582 | Flip-Flop Circuit Design - A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal. | 04-26-2012 |
20120169393 | PROCESSING CLOCK SIGNALS - A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal. | 07-05-2012 |
20140015582 | SLICER AND METHOD OF OPERATING THE SAME - This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal. | 01-16-2014 |
20140070861 | Flip-Flop Circuit and Semiconductor Device - A flip-flop circuit consuming lower power than a conventional flip-flop circuit is provided. Further, a flip-flop circuit having a smaller number of transistors than a conventional flip-flop circuit to have a reduced footprint is provided. An n-channel transistor is used as a transistor which is to be turned on at a high level potential and a p-channel transistor is used as a transistor which is to be turned on at a low level potential, whereby the flip-flop circuit can operate only with a clock signal and without an inverted signal of the clock signal, and the number of transistors that operate only with a clock signal in the flip-flop circuit can be reduced. | 03-13-2014 |
20140132323 | LATCH APPARATUS AND APPLICATIONS THEREOF - A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage. | 05-15-2014 |
20140152363 | PULSE-BASED FLIP FLOP - A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a first clock signal and the second clock signal. The pulse-based flip-flop includes a pulse generator and a data latch. The pulse generator includes a first inverter and a signal delay circuit to receive the first clock signal and generate the second clock signal; the data latch includes a delivery circuit, a latch circuit and a control circuit. The data latch is used to latch the data input signal and output the data output signal in response to the first and the second clock signals. | 06-05-2014 |
20140266369 | LOW POWER ARCHITECTURES - Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a clock path comprising a plurality of transistors, wherein the clock signal has a high state corresponding to a high voltage that is above threshold voltages of the transistors in the clock path. The method also comprises sending a data signal to the flop via a data path comprising a plurality of transistors, wherein the data signal has a high state corresponding to a low voltage that is below threshold voltages of the transistors in the data path. The method further comprises latching the data signal at the flop using the clock signal. | 09-18-2014 |
20160134265 | FLIP FLOP CIRCUIT - A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal. | 05-12-2016 |
20170237434 | PULSE-GENERATOR | 08-17-2017 |