Entries |
Document | Title | Date |
20090027097 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool. | 01-29-2009 |
20090102532 | Latch circuit - A latch circuit includes: a first terminal; a second terminal; a first data-gating circuit coupled to the first terminal and the second terminal, the first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal; a second data-gating circuit coupled to the first terminal and the second terminal, the second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal; a third terminal receiving a fifth signal; a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, the selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and a bistable circuit coupled to the selector circuit, the bistable circuit holding one of the third signal and the fourth signal. | 04-23-2009 |
20090121765 | LATCH CIRCUIT AND FLIP-FLOP CIRCUIT - A latch circuit includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits is connected with at least two of the three or more second nodes, and controls the voltage of the first node based on the voltages of the at least two second modes. Each of the second node voltage control circuits is connected with at least two of the three or more first nodes and controls the voltage of the second node based on the voltages of the at least two first nodes. | 05-14-2009 |
20090167395 | HIGH PERFORMANCE LATCHES - An integrated circuit includes at least one latch circuit ( | 07-02-2009 |
20100079183 | Low voltage, high speed data latch - Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during setting of the latch when the latch is enabled. | 04-01-2010 |
20100164582 | DRIVING CONFIGURATION OF A SWITCH - A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch. | 07-01-2010 |
20100244918 | SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR - A clock signal is received at a clock node of a latch module, and a data signal is received at a data node of the latch module. The data signal including information to be latched at a first latch of the latch module and at a second latch of the latch module. A first representation of the data signal to a first data node of the first latch is delayed relative to a second representation of the data signal to a corresponding first data node of the second latch to obtain a first timing requirement between the data signal and the clock signal relative to the first latch that is substantially different than a second timing requirement. An error signal is generated in response to different data being latched at the first latch than at the second latch. | 09-30-2010 |
20110050310 | LEVEL SHIFTER CIRCUIT - The present invention relates to a level shifter circuit ( | 03-03-2011 |
20110095799 | FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION - A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node. | 04-28-2011 |
20110133805 | DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD - A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal. | 06-09-2011 |
20110181330 | FLIP-FLOP, FREQUENCY DIVIDER AND RF CIRCUIT HAVING THE SAME - A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples. | 07-28-2011 |
20110199140 | Semiconductor device - Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal. | 08-18-2011 |
20120025885 | MULTI-BIT INTERLACED LATCH - A multi-bit interlace latch includes a first and second latch that each have redundant active feedback paths to reduce the incidence of soft-errors. The first and second latches have active circuitry that includes nodes that are susceptible to radiation-induced soft errors. Active circuitry from the second latch is interlaced between active circuitry of the first latch to increase the isolation between critical nodes of the first latch. While the second latch circuit increases isolation between critical nodes of the first latch, the first latch may also benefit the second latch by increasing the isolation between critical nodes of the first latch as well. | 02-02-2012 |
20120274378 | MEMORY CIRCUIT, SIGNAL PROCESSING CIRCUIT, AND ELECTRONIC DEVICE - A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided. | 11-01-2012 |
20120274379 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor. | 11-01-2012 |
20120319754 | TRANSISTOR SWITCH CONTROL CIRCUIT - A synchronous driving circuit in the arts may cause a short through pheromone when a duty cycle of a duty cycle control signal is too short. The present invention sets a delay time with a suitable period when the duty cycle of the duty cycle control signal is too short to avoid the short through phenomenon. | 12-20-2012 |
20130002326 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 | 01-03-2013 |
20130043922 | SUPPLY COLLAPSE DETECTION CIRCUIT - A supply collapse detection circuit is described. The supply collapse detection circuit includes threshold detection circuitry coupled to a first power supply and to a second power supply that provides a second voltage. The supply collapse detection circuit also includes supply collapse output circuitry coupled to the threshold detection circuitry to receive a detection signal when the second voltage drops. The supply collapse output circuitry includes an output node to provide an output signal indicating the drop. The supply collapse detection circuit additionally includes feedback circuitry coupled to the first power supply, to the threshold detection circuitry and to the supply collapse output circuitry. The feedback circuitry reduces leakage when the second voltage drops. | 02-21-2013 |
20130169332 | Family of Multiplexer/Flip-Flops with Enhanced Testability - A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter. | 07-04-2013 |
20130241615 | HIGH VOLTAGE SWING DECOMPOSITION METHOD AND APPARATUS - A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit. | 09-19-2013 |
20130241616 | Keeper Circuit And Electronic Device Having The Same - A keeper circuit includes a first latch and a second latch, each of the first latch and the second latch being configured to latch output data determined by input data during an evaluation phase, and the second latch, during a high-impedance phase, being configured to maintain output data of the second latch using output data of the first latch. | 09-19-2013 |
20130278315 | DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT - One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the dock. | 10-24-2013 |
20130314139 | SEMICONDUCTOR DEVICE, AND DISPLAY DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal. | 11-28-2013 |
20140021995 | D Flip-Flop with High-Swing Output - A D flip-flop includes a first switch, a level shifter, and a second switch therein. The first switch includes a first input and a first output. The level shifter includes a second input coupled to the first input, and a second output. The second switch includes a third input coupled to the second output, and a third output. The first input and the third output form an input and an output of the D flip-flop. | 01-23-2014 |
20140125393 | LATCH CIRCUIT WITH A BRIDGING DEVICE - One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors. | 05-08-2014 |
20140240018 | CURRENT MODE LOGIC LATCH - A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor. | 08-28-2014 |
20140266367 | SEMICONDUCTOR DEVICE - To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node. | 09-18-2014 |
20140266368 | LIGHT RECEIVING CIRCUIT - The light receiving circuit includes: a photoelectric conversion element for causing a current corresponding to an amount of incident light to flow; a MOS transistor including a source connected to the photoelectric conversion element and a drain connected to a node, for causing the current of the photoelectric conversion element to flow to the node while maintaining a voltage of the source to a first voltage; a reset circuit for causing a current to flow from the node to a GND terminal so that a voltage of the node becomes a second voltage lower than the first voltage; a control circuit for outputting a reset signal to the reset circuit; and a voltage increase detection circuit for detecting a fluctuation in the voltage of the node and outputting a detection result. | 09-18-2014 |
20140368247 | NOVEL LOW OVERHEAD HOLD-VIOLATION FIXING SOLUTION USING METAL-PROGRAMABLE CELLS - Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops. | 12-18-2014 |
20150070064 | INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. | 03-12-2015 |
20150116020 | LATCH COMPARATOR CIRCUITS AND METHODS - The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit. | 04-30-2015 |
20150303901 | FLIP-FLOP CIRCUIT - A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node, and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged. | 10-22-2015 |
20150371705 | METHOD FOR PROGRAMMING A BIPOLAR RESISTIVE SWITCHING MEMORY DEVICE - An electronic circuit including a bipolar switching memory device including first and second electrodes at terminals of which a programming voltage can be applied, the circuit including: a first mechanism applying, to the first electrode, a data signal having, during a time period d, a constant state 0 or 1; a second mechanism applying, to the second electrode, a control signal that alternates, during time period d, between state 1 and state 0, the control signal being same regardless of the state in which the memory device is programmed; a selection device allowing a current to flow into the memory device during a programming time included in time period d; and a change of state of the control signal taking place during the programming time. | 12-24-2015 |
20160182024 | Thyristor-Based Optical Flip-Flop | 06-23-2016 |