Class / Patent application number | Description | Number of patent applications / Date published |
327205000 | Using hysteresis (e.g., Schmitt trigger, etc.) | 34 |
20080238513 | Hysteresis Circuit Without Static Quiescent Current - A hysteresis circuit including a comparator and capacitive voltage divider circuit. The capacitive voltage divider circuit includes a first capacitor coupled between an input terminal and a positive comparator input, a second capacitor coupled between ground and the positive comparator input, and a third capacitor coupled between the comparator output and positive comparator input. A reference voltage is applied to the negative comparator input. The comparator is powered by the input signal provided on the input terminal. When the voltage on the positive comparator input is less than the reference voltage, the third capacitor is effectively coupled in parallel with the first capacitor. When the voltage on the positive comparator input is greater than the reference voltage, the third capacitor is effectively coupled in parallel with the second capacitor. | 10-02-2008 |
20090237135 | SCHMITT TRIGGER HAVING VARIABLE HYSTERESIS AND METHOD THEREFOR - A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger. | 09-24-2009 |
20090284294 | CROSS-CORRELATION OF SIGNALS USING EVENT-BASED SAMPLING - A sub-circuit for facilitating the synchronization of event-based samples of signals in a cross-correlation circuit utilizing event-based sampling is provided. The sub-circuit alternatively integrates one of the signals to be cross-correlated and alternates between the signals in response to the output of a hysteretic comparator. The invention extends to a method of manipulating the input signals to a cross-correlation circuit utilizing event-based sampling so-as to facilitate the synchronization of the event-based samples of the signals. | 11-19-2009 |
20110156787 | ENABLE PIN USING PROGRAMMABLE HYSTERESIS IMPROVEMENT - An apparatus for providing programmable hysteresis control using an enable pin of a device is disclosed. An enable pin is configured to receive an input signal to enable and disable an associated device responsive to the input signal. A current sink is attached to the enable pin and is responsive to circuitry that disables the current sink responsive to application of the input signal at a first voltage level and enables the current sink responsive to application of the input signal at a second voltage level. | 06-30-2011 |
20110210776 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 09-01-2011 |
20120032720 | METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period. | 02-09-2012 |
20120068750 | SWITCHING CIRCUITS, LATCHES AND METHODS - Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level. | 03-22-2012 |
20130021077 | AUTOMATIC CLOCK-ACTIVITY BASED CHIP/IO RING DESIGN - A NOVEL ARCHITECTURE TO REDUCE STANDBY CONSUMPTION - A circuit including an input configured to receive a clock signal. Detection circuitry may be configured to detect if the clock signal is present on the input. An output is configured to provide a control signal having a first level if the clock signal is present on the input and a second level if the clock signal is absent from the input. | 01-24-2013 |
20130099841 | NOISE REDUCTION DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage. | 04-25-2013 |
20130154709 | SYSTEMS AND METHODS FOR OUTPUT CONTROL - The present disclosure provides an output control circuit including a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to compare an output voltage with a set output voltage threshold and to output a disable signal to an enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. | 06-20-2013 |
20130222032 | ADAPTIVE CLOCK SIGNAL GENERATOR WITH NOISE IMMUNITY CAPABILITY - An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases. | 08-29-2013 |
20140002162 | APPARATUS FOR IMPROVED SIGNAL COMMUNICATION IN ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS | 01-02-2014 |
20160028382 | SCHMITT TRIGGER CIRCUIT AND POWER SUPPLY MONITORING APPARATUS - A Schmitt trigger circuit according to an embodiment includes a voltage dividing circuit that divides an input voltage and outputs a divided voltage, and a basic Schmitt trigger circuit that includes a transistor as a current controlling element and controls current flowing through a light emitting diode (LED) included in an external photocoupler on the basis of the output voltage of the voltage dividing circuit proportional to the input voltage. The voltage dividing circuit has a positive temperature coefficient. | 01-28-2016 |
20160028397 | RADIATION HARDENED DIGITAL CIRCUIT - This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal. | 01-28-2016 |
327206000 | Including field-effect transistor | 20 |
20080204101 | Hysteresis characteristic input circuit including resistors capable of suppressing penetration current - In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage. | 08-28-2008 |
20080272816 | Inverter with Four-Transistor Schmitt Trigger - A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region. | 11-06-2008 |
20090066388 | Schmitt Trigger Circuit - A Schmitt trigger circuit having at least eight transistors is provided. The first transistor can have a source connected to a power terminal, and the second transistor can have a source connected to a drain of the first transistor. The third transistor can have a source connected to the drain of the first transistor, and the fourth transistor can have a source connected to a drain of the third transistor and a drain electrically connected to a ground terminal. The fifth transistor can have a drain connected to a drain of the second transistor, gates of the third and fourth transistors, and an output terminal. The sixth transistor can have a drain connected to a source of the fifth transistor and a source connected to the ground terminal. The seventh transistor can have a source connected to the source of the fifth transistor and a gate connected to the output terminal. The eighth transistor can have a source connected to a drain of the seventh transistor, a gate connected to the output terminal, and a drain electrically connected to the power terminal. | 03-12-2009 |
20090189665 | SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT - A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D. | 07-30-2009 |
20090302914 | Pad input signal processing circuit - A pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal. | 12-10-2009 |
20100117703 | MULTI-MODE SINGLE-ENDED CMOS INPUT BUFFER - Techniques reduce the effects of power supply noise on a signal provided by a single-ended complementary metal-oxide semiconductor (i.e., CMOS) input buffer circuit capable of receiving an input signal having one of a variety of acceptable formats, while generating the signal to have substantially the same duty cycle as the input signal. The techniques include one or more of AC coupling, hysteresis, and voltage biasing applied to the input buffer circuit. | 05-13-2010 |
20100117704 | Four-Transistor Schmitt Trigger Inverter with Hysteresis - A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region. | 05-13-2010 |
20100327930 | SCHMITT TRIGGER WITH GATED TRANSITION LEVEL CONTROL - A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level. | 12-30-2010 |
20110043265 | REDUCED AREA SCHMITT TRIGGER CIRCUIT - A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter. | 02-24-2011 |
20110109364 | INPUT CIRCUIT - Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors ( | 05-12-2011 |
20110133804 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20120074999 | SCHMITT TRIGGER CIRCUIT OPERATED BASED ON PULSE WIDTH - There are provided a Schmitt trigger circuit that has hysteresis characteristics in which a release point and an operating point are determined based on a width of an inputted pulse. The Schmitt trigger circuit may include a signal/pulse conversion unit that receives an analog signal to generate an input pulse having a width corresponding to a magnitude of the analog signal, a pulse width determination unit that compares the width of the input pulse generated in the signal/pulse conversion unit with a predetermined first threshold width and a second threshold width greater than the first threshold width to output state information indicating the compared result, and an output determination unit that outputs a high signal, when the width of the input pulse is changed from a state of being smaller than the second threshold width to a state of being greater than the second threshold width based on the state information, and outputs a low signal when the width of the input pulse is changed from a state of being greater than the first threshold width to a state of being smaller thali the first threshold width based on the state information. | 03-29-2012 |
20120161841 | CAPACATIVE ISOLATOR WITH SCHMITT TRIGGER - High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal. | 06-28-2012 |
20130120046 | Analog rail-to-rail comparator with hysteresis - According to a novel aspect, operating an analog rail-to-rail comparator circuit with common mode detection of differential input signals includes generating a hysteresis current for the comparator circuit based on a common mode voltage used for the common mode detection. The hysteresis current is added to a differential output of a comparator in the comparator circuit, such that a hysteresis voltage at an output of the comparator circuit is substantially independent of the common mode voltage. | 05-16-2013 |
20140062561 | SCHMITT RECEIVER SYSTEMS AND METHODS FOR HIGH-VOLTAGE INPUT SIGNALS - Presented systems and methods facilitate efficient switching operations for components operating at different voltage level than a received signal voltage level. In one embodiment, the components of a presented system are operable to perform switching operations for signals with a voltage level swing larger than the power rail of the circuit receiving the signals. In one embodiment a system includes an input component, a transition component, a transition point feedback component and an output component. The input component is operable to receive an input signal. The transition component is operable to transition the input signal. The transition point feedback component is operable to adjust a point at which a transition in the input signal occurs in the transition component. The output component is operable to forward an output signal from the transition point feedback component. | 03-06-2014 |
20140091846 | INTEGRATED COMPARATOR WITH HYSTERESIS, IN PARTICULAR PRODUCED IN AN FD SOI TECHNOLOGY - A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor. | 04-03-2014 |
20140132322 | INPUT CIRCUIT - An input circuit includes a first P-channel MOS transistor including a first terminal supplied with a high-potential power supply voltage and a second terminal coupled to a first node, a second P-channel MOS transistor including a first terminal coupled to the first node and a second terminal coupled to a second node, a first N-channel MOS transistor including a first terminal coupled to the second node and a second terminal coupled to a third node, and a second N-channel MOS transistor including a first terminal coupled to the third node and a second terminal supplied with a low-potential power supply voltage. An input signal is supplied to gate terminals of the P-channel MOS transistors and the N-channel MOS transistors. A control circuit controls the potential at the first node and the potential at the third node based on the input signal and the potential at the second node. | 05-15-2014 |
20140266366 | COMPENSATED HYSTERESIS CIRCUIT - A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit. | 09-18-2014 |
20150349757 | Hysteresis Circuit - A hysteresis circuit includes a current comparator arranged to receive an input current signal. A reference current source is coupled to the current comparator and arranged to provide a reference current. A hysteresis current source is arranged to provide a hysteresis current. A switch is coupled between the reference current source and the hysteresis current source. At least one buffer is coupled to the current comparator and arranged to provide an output voltage signal. The output voltage signal has a first voltage if the input current signal is greater than a sum of the reference current and the hysteresis current and the output voltage signal has a second voltage if the input current signal is less than the reference current. | 12-03-2015 |
20160182022 | CMOS SCHMITT TRIGGER CIRCUIT AND ASSOCIATED METHODS | 06-23-2016 |