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Duty cycle control

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327172000 - Rectangular (e.g., clock, etc.) or pulse waveform width control

Patent class list (only not empty are listed)

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Entries
DocumentTitleDate
20080272814PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL - A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.11-06-2008
20090195283DELAY LOCKED LOOP - The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.08-06-2009
20090195282Semiconductor integrated circuit device having standard cell including resistance element - A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.08-06-2009
20090128207Clock Circuitry for Generating Multiple Clocks with Time-Multiplexed Duty Cycle Adjustment - Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal.05-21-2009
20100164581PULSED WIDTH MODULATED CONTROL METHOD AND APPARATUS - A pulse width modulated (PWM) controller has an input terminal for receiving a pulsed input signal having a first duty cycle, a power supply terminal for receiving a power supply voltage. a minimum duty cycle reference voltage signal, and a control circuit for providing a pulse-width-modulated (PWM) output signal having a second duty cycle related to the first duty cycle of the pulsed input signal. The PWM output control signal having a minimum duty cycle that is adjustable in response to a change in the power supply voltage. In an embodiment, the second duty cycle and the first duty cycle are correlated in a substantially linear relationship. In an embodiment, the PWM control circuit also has a triangle wave generation circuit for generating a triangle wave signal configured to oscillate between an upper limit voltage and a lower limit voltage, which are adjustable in response to a change in the power supply voltage.07-01-2010
20100164580HIGH SPEED CLOCK SIGNAL DUTY CYCLE ADJUSTMENT - A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.07-01-2010
20080258787Power Supply Controller - A parallel circuit 10-23-2008
20110193605DUTY TRANSITION CONTROL IN PULSE WIDTH MODULATION SIGNALING - A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process that generates a series of groups of PWM cycles that gradually transition from the original duty to the new duty. Each group includes a corresponding set of a predetermined number of PWM cycles that is repeated one or more times over a predetermined duration for the group. Each set has a certain proportion of PWM cycles having the new duty to PWM cycles having the original duty, whereby the proportion increases for each successive group of the series. This gradual transition in the PWM signal from the original duty to the new duty effectively provides an effective higher duty resolution for the PWM signal generator during the duty transition.08-11-2011
20100117702DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.05-13-2010
20100073059Duty control circuit and semiconductor device having the same - A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.03-25-2010
20100073057DUTY CYCLE CORRECTOR AND CLOCK GENERATOR HAVING THE SAME - A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configured to receive the positive clock and the negative clock, to detect duty ratios of the positive clock and the negative clock and to generate the one or more control signals.03-25-2010
20100073058CLOCK/DATA RECOVERY CIRCUIT - A clock/data recovery circuit includes a data duty correction circuit (03-25-2010
20130076420DIGITALLY CONTROLLED PULSE WIDTH MODULATOR UTILIZING REAL TIME CALIBRATION - A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.03-28-2013
20130033294COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME - A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.02-07-2013
20100045353SELECTIVE EDGE PHASE MIXING - Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.02-25-2010
20100109730PWM CONTROL CIRCUIT HAVING ADJUSTABLE MINIMUM DUTY CYCLE - A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in response to changes in the power supply voltage. A pulse generation circuit is coupled to the triangle wave generation circuit and a minimum duty cycle setting voltage, and is configured to generate a PWM pulse signal with a minimum duty cycle determined by the relative magnitude of the triangle wave signal and the minimum duty cycle reference voltage. In an embodiment, the minimum duty cycle is increased when the power supply voltage is lower than a predetermined reference voltage.05-06-2010
20100109729DUTY DETECTING CIRCUIT AND DUTY CYCLE CORRECTOR INCLUDING THE SAME - A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code.05-06-2010
20100109731APPARATUS AND METHOD FOR DUTY CYCLE CORRECTION - There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calculation, a comparison unit comparing the moving sum signal with a predetermined threshold voltage, outputting a high signal or low signal, a mean value calculation unit calculating the mean value of an output signal outputted from the comparison unit, the output signal being included in a section having a period integer times greater than that of the square-wave signal, and a threshold voltage control unit comparing the mean value with a middle value, increasing the threshold voltage when the mean value is greater than the middle value, and decreasing the threshold voltage when the mean value is less than the middle value.05-06-2010
20130069701PHASE INTERPOLATION CIRCUIT - A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.03-21-2013
20130069702PWM SIGNAL OUTPUT CIRCUIT - A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.03-21-2013
20100134167COMPENSATION OF DEGRADATION OF PERFORMANCE OF SEMICONDUCTOR DEVICES BY CLOCK DUTY CYCLE ADAPTATION - The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required.06-03-2010
20090302912DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals.12-10-2009
20110006824WAKE-UP RECEIVER AND WAKE-UP METHOD USING DUTY CYCLING AND POWER OFF TECHNIQUE - Provided is a low-power wake-up receiver that is sensitive to electric waves, by which power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN) is minimized. A wake-up receiver waking up a main transceiver includes a duty cycle signal generation unit controlling a duty cycle of a duty cycle signal; a burst signal detection unit receiving an input signal including a burst signal and a data signal based on the duty cycle signal, amplifying the input signal, and, if the amplified input signal is the burst signal, outputting a control signal; and a data signal detection unit re-amplifying the amplified input signal based on the control signal, and, if the re-amplified input signal is the data signal, outputting a wake-up signal. Power supplied to the duty cycle signal generation unit is interrupted based on the control signal and power is re-supplied to the duty cycle signal generation unit based on the wake-up signal.01-13-2011
20090091365METHODS FOR GENERATING PWM-SIGNALS - In a method for generating a PWM-signal to drive the power transistors of a half-bridge of a converter with the aid of a digital circuit, a digital reference value is compared to the counter content of a digital counting ramp, and a logic state of the PWM-signal is dependent upon whether the reference value is greater than the counter content of the counting ramp. In this context, at least two counters count counter contents of the counting ramp following one another in alternation, and the logic state of the PWM-signal is dependent upon whether the reference value is greater than the counter contents of counting ramps of each of the at least two counters.04-09-2009
20090091364Semiconductor circuit - A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; a load resistance section to output a voltage according to a current output by the differential input section; differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section; a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section.04-09-2009
20090289679Duty correction circuit - A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.11-26-2009
20090066383Apparatus and method for generating clock signal - An apparatus, including: a circuit which operates according to a clock signal, the circuit operating with a delay, and a clock generator which generates the clock signal with a duty ratio, the duty ratio being adapted to the delay.03-12-2009
20120112811GENERATION OF ADJUSTABLE PHASE REFERENCE WAVEFORM - One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.05-10-2012
20120326760PROGRAMMABLE DUTY CYCLE SELECTION USING INCREMENTAL PULSE WIDTHS - A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.12-27-2012
20110279159CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION - Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.11-17-2011
20080204098Current sharing for multiphase power conversion - Current sharing scheme based on input power and/or the power efficiency for a power stage with multiple phases and/or paralleled modules is described. According to the scheme, duty cycles of different phases/modules may be adaptively adjusted until the minimum input power and/or the maximum power efficiency is achieved. For certain input voltages, the minimum input power exists at the minimum total input current. Thus, input power and/or the input current may be used as an indicator of the maximized power efficiency of the power stage and hence be used to track the optimal current sharing ratio among the multiple phases/modules.08-28-2008
20110285441CLOCK ADJUSTMENT CIRCUIT, SHIFT DETECTION CIRCUIT OF DUTY RATIO, IMAGING DEVICE AND CLOCK ADJUSTMENT METHOD - A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.11-24-2011
20110298513DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT AND METHOD OF CORRECTING DUTY - The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.12-08-2011
20110291724DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.12-01-2011
20110291726DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT INCLUDING THE CIRCUIT, AND METHOD OF CORRECTING DUTY - A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.12-01-2011
20110291725DUTY DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.12-01-2011
20100225372DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.09-09-2010
20110267123CLOCK DUTY CORRECTION CIRCUIT - A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.11-03-2011
20090153208Pulse Width Modulation Driver for Electroactive Lens - An electroactive lens driver generates a variable root-mean-square drive voltage for controlling an electroactive lens by controlling the duty cycle of a modified square wave.06-18-2009
20080265961CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.10-30-2008
20110063007DELAY CIRCUIT WITH DELAY EQUAL TO PERCENTAGE OF INPUT PULSE WIDTH - A delay circuit with a delay equal to the percentage of the input pulse width is described. In one embodiment, the ratio of the discharge current to the charge-up current of a timing capacitor is used to determine the percentage of the input pulse width used for the output delay. In a first timing phase, the input pulse width is stored as a voltage on the timing capacitor. In a second timing phase, the output is delayed by a percentage of the input pulse width. In a third timing phase, the circuit is restored to the trip point to remove sensitivity to process variation or applied conditions variation such as voltage or temperature (P-V-T variation), and be ready for the next timing cycle.03-17-2011
20100079182METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION - A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.04-01-2010
20100079181SAMPLE-POINT ADJUSTMENT IN A SWITCHING CONVERTER - An apparatus and method of generating a drive signal for a switch in a switching converter having input terminals for applying an input voltage, output terminals for providing an output signal, and at least one inductive storage element coupled to the switch. The method includes sampling the output signal to provide a sampled output signal, and generating a pulsewidth modulated drive signal having a duty cycle that is dependent on the sampled output signal, wherein the output voltage is sampled at sampling times that are dependent on the duty cycle.04-01-2010
20090206900DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.08-20-2009
20090273382CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.11-05-2009
20120194244SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CORRECTING DUTY THEREOF - A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.08-02-2012
20090289680SEMICONDUCTOR DEVICE - A semiconductor device includes a first duty determining circuit (11-26-2009
20090295446DUTY CYCLE CORRECTING CIRCUIT AND METHOD OF CORRECTING A DUTY CYCLE - A duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal.12-03-2009
20090261877Duty cycle correction circuit with wide-frequency working range - A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with the duty cycle of 50%. The pulse generator includes a NAND gate, a modulation device, and an inverter. The inverter is coupled between the second input end of the NAND gate and the modulation device. The modulation device modulates the low-level status of the input clock signal and accordingly outputs to the inverter. The first input end of the NAND gate receives the input clock signal. The NAND gate operates NAND calculation to the signals received on the input ends of the NAND gate and accordingly outputs a periodic low-level pulse signal.10-22-2009
20130099840DUTY ADJUSTMENT CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal.04-25-2013
20080246524Duty Cycle Correction Circuit Whose Operation is Largely Independent of Operating Voltage and Process - A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.10-09-2008
20080246523PULSE WIDTH MODULATION WAVE OUTPUT CIRCUIT - A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.10-09-2008
20080278209METHOD OF PULSE WIDTH MODULATION SIGNAL PROCESSING AND DEVICE INCLUDING SIGNAL PROCESSING FOR PULSE WIDTH MODULATION - A method and system process a signal for PWM modulation. An amplitude control signal adjusts the amplitude of an input signal, and an offset is added to the amplitude-adjusted signal to produce an offset-adjusted signal. The offset is selected according to the amplitude adjustment applied to the input signal. The offset-adjusted signal is pulse-width modulated the to produce a pulse-width modulated signal, and the pulse-width modulated signal is filtered to reduce high frequency components thereof.11-13-2008
20080284479METHOD OF FORMING A PWM CONTROLLER AND STRUCTURE THEREFOR - In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency.11-20-2008
20080290920DUTY CYCLE CORRECTION CIRCUIT AND METHOD THEREOF - A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.11-27-2008
20080252349DUTY CYCLE CORRECTING CIRCUIT - A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.10-16-2008
20080238509BOUNDING A DUTY CYCLE USING A C-ELEMENT - A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element.10-02-2008
20120293225DUTY CORRECTION CIRCUIT - A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.11-22-2012
20120105122DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.05-03-2012
20090146715DUTY CYCLE CALIBRATION FOR RECEIVER CLOCK - Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.06-11-2009
20090128208APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT - Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals.05-21-2009
20090128206Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler - An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.05-21-2009
20090066382Digital Pulse-Width-Modulator with Discretely Adjustable Delay Line - A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. In another implementation, a digital pulse-width-modulator with a digital phase-locked loop is also provided.03-12-2009
20110267124CLOCK SIGNAL DUTY CORRECTION CIRCUIT - A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.11-03-2011
20090160515Auto-tracking clock circuitry - A system and method for generating a clock signal is disclosed. In various embodiments of the invention disclosed herein, a global clock signal is generated and provided as an input to local clock circuitry operable to generate a local clock signal therefrom. The local clock circuitry comprises logic components that are susceptible to negative bias thermal instability (NBTI) effects resulting in degradation of the local clock signal. Clock propagation adjustment circuitry is used to modify the duty cycle of the global clock signal to compensate for the degradation resulting from NBTI effects thereby providing an optimized local clock signal.06-25-2009
20090160516DUTY CYCLE CORRECTION CIRCUIT FOR HIGH-SPEED CLOCK SIGNALS - The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.06-25-2009
20110204948DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.08-25-2011
20090284293DUTY CORRECTION CIRCUIT - A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.11-19-2009
20080315930DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT - A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.12-25-2008
20090051398METHOD AND DELAY CIRCUIT WITH ACCURATELY CONTROLLED DUTY CYCLE - A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.02-26-2009
20110227624DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.09-22-2011
20090085624FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME - A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.04-02-2009
20110227623DUTY CYCLE CORRECTING CIRCUIT AND DUTY CYCLE CORRECTING METHOD - A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock. A clock selecting unit selectively outputs the first corrected clock or the second corrected clock as an output clock in response to the detection signal. A duty ratio detecting unit detects a duty ratio of the output clock, thereby generating the detection signal.09-22-2011
20090002043System, Method and Apparatus Having Improved Pulse Width Modulation Frequency Resolution - Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.01-01-2009
20090002042System and method for conditioning differential clock signals and integrated circuit load board using same - A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.01-01-2009
20090206901DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION - A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.08-20-2009
20090102529SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals.04-23-2009
20090251184DUTY CYCLE CORRECTION CIRCUIT APPARATUS - A duty cycle correction circuit apparatus includes a flip-flop, a feedback unit connected between an input node and an output node of the flip-flop to invert an output signal of the flip-flop and to output the inverted signal as an output signal of the feedback unit, and a selection unit to select and output one of a first clock signal and a second clock signal to the flip-flop in response to the output signal of the feedback unit, wherein the first clock signal has a half-period phase difference with respect to the second clock signal. Using clock signals with a half-period phase difference therebetween and a simple digital circuit, the duty cycle correction circuit can correct a duty ratio to 50:50 regardless of an initial condition.10-08-2009
20090140785Duty detector and duty cycle corrector including the same - A duty detector includes a clock converter, a hold pulse generator, a first logic operator, and an up/down counter. The clock converter receives a clock signal to generate an up clock signal and a down clock signal having phases opposite to each other. The hold pulse generator generates a hold pulse signal that is deactivated during a counting interval corresponding to first through (N−1)-th period intervals of the clock signal and is activated during a holding interval corresponding to an N-th period interval. The first logic operator outputs a counting clock signal by performing a first logic operation on the hold pulse signal and a sampling clock signal. The up/down counter determines a logic level of the up clock signal and a logic level of the down clock signal at an edge timing of the counting clock signal, increases or decreases a counting value in response to the determination result, and outputs duty information of the clock signal, based on a final counting value.06-04-2009
20120194245PULSE WIDTH MODULATOR - Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.08-02-2012
20100148835Duty control buffer circuit and duty correction circuit - The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs.06-17-2010
20090121763ADJUSTABLE DUTY CYCLE CIRCUIT - Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transitors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.05-14-2009
20100156492SYSTEM AND METHOD FOR THERMAL LIMIT CONTROL - This disclosure relates to a system and method for pulse generation. A system in accordance with the present disclosure may include a power dissipating element configured to receive power from a power source. At least one of the power source and the power dissipating element may be configured to generate a first signal. The system may further include a measuring instrument in communication with the power source. The measuring instrument may be configured to measure the first signal and to provide an input corresponding to a measured signal to a duty cycle limiter. The system may also include a pulse controller operatively connected to the power source. The pulse controller may be configured to control a duty cycle of the first signal and to receive a second signal from the duty cycle limiter. The pulse controller may be configured to disable at least one of the power source and the power dissipating element if the duty cycle limiter has determined that a maximum condition has been exceeded. Other embodiments are also within the scope of the present disclosure.06-24-2010
20100188126Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation - A method, system and apparatus for controlling the duty cycle of a clock to optimize duty cycle correction and non over-lapping clock generation. The first system generates a reference voltage and one or more clock signals. A comparison is made between the DC level of an output clock and the reference voltage. A correct duty cycle of the clock signal is equal to a predetermined ratio of high time to low time, within an acceptable margin, wherein the ratio of high time to low time is derived from a first resistor and a second resistor. A second system is developed to generate non-overlap clock signals with non-overlap gap control, wherein a reference voltage of a first circuit network is the reference voltage of a second circuit network; thereby generating a single reference signal for the non-overlap circuit network.07-29-2010
20100259308Clock Circuit and Method for Pulsed Latch Circuits - Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.10-14-2010
20100085097Pulse-Elimination Pulse-Width Modulation - Instead of reducing the pulse widths of all pulses simultaneously in order to reduce the output power of a switched-mode amplifier linearized by a pulse-width modulator, the width of every other (or every n-th) pulse is reduced. When the widths of the selected pulses have been reduced to zero, the amplifier's output power can be further reduced by selecting further pulses from the remaining non-zero-width pulses, and reducing the widths of those pulses. For example, after every other pulse of an original output signal has been removed, every other pulse of the remaining pulses can be reduced to obtain still lower amplifier output power. In this way, the number of pulses (and thus the number of switching transitions) is reduced for small signals, and therefore the amplifier's switching losses are reduced and efficiency is improved.04-08-2010
20110128059DUTY CORRECTION CIRCUIT - A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.06-02-2011
20100219870DUTY RATIO CORRECTION CIRCUIT AND DUTY RATIO CORRECTION METHOD - A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.09-02-2010
20090072873Circuit Arrangement and Method for the Provision of a Clock Signal with an Adjustable Duty Cycle - The circuit arrangement (03-19-2009
20080315929AUTOMATIC DUTY CYCLE CORRECTION CIRCUIT WITH PROGRAMMABLE DUTY CYCLE TARGET - A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.12-25-2008
20100301913CMOS Clock Receiver with Feedback Loop Error Corrections - A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the cross point error correction signal.12-02-2010
20100134168SYSTEM, METHOD AND APPARATUS HAVING IMPROVED PULSE WIDTH MODULATION FREQUENCY RESOLUTION - Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.06-03-2010
20110025392Duty cycle correction method and its implementing circuit - A duty cycle correction method comprises detecting independently a relative delay time of two input differential signals; equating the sum of two relative delay time with the cycle of the input differential signals; and adjusting the two delay time to the same value. A corresponding implementation circuit comprises two time delay units; two correlation phase detectors connecting simultaneously with each of the two time delay units; a charge pump connecting with the output of each of the two correlation phase detectors, with its output connecting to the two time delay units in order to form a loop; and a synthesis output unit connecting with both the time delay units, thereby generating output signals. The adjusting range of duty cycle becomes much wider. The implementation circuit is absolutely symmetrical, so a duty cycle with high accuracy can be obtain.02-03-2011
20100327929PREDETERMINED DUTY CYCLE SIGNAL GENERATOR - Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.12-30-2010
20090033393METHOD AND APPARATUS FOR REGULATING A DIODE CONDUCTION DUTY CYCLE - A power converter control method and apparatus is disclosed. A control circuit for use in a power converter according to aspects of the present invention includes a clock signal generator coupled to generate a clock signal to control switching of a power switch to be coupled to the control circuit. Feedback circuitry is coupled to receive a feedback signal, which is representative of an output of a power converter during a feedback portion of an off time of the power switch. The feedback circuitry is coupled to respond to the feedback signal to control the clock signal generator to regulate a duty cycle of the feedback portion of the off time of the power switch as a proportion of a total power switch switching cycle period.02-05-2009
20100253407APPARATUS AND METHOD OF GENERATING REFERENCE CLOCK FOR DLL CIRCUIT - An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.10-07-2010
20120200331DIGITAL CONTROL UNIT HAVING A TRANSIENT DETECTOR FOR CONTROLLING A SWITCHED MODE POWER SUPPLY - A switched mode power supply (SMPS) comprising a feedback unit, voltage feed forward (VFF) compensation signal generator and a transient detector. A VFF compensation signal is only applied to the output of the feedback unit when a transient is detected by the transient detector on the input voltage of the SMPS, thereby saving power and computation time. The transient detector comprises a first comparator to detect that a positive transient has occurred if a difference signal is greater than a positive threshold level; a second comparator to determine if the difference signal is within a predetermined range of positive values and output a result that indicates if the difference signal is within the predetermined range of positive values; and a first calculator to detect that a positive transient has occurred if, out of a first predetermined number of consecutive results of the output of the second comparator, there is at least a second predetermined number of results indicating that the difference signal is within the predetermined range of positive values. The transient detector comprises further features for similarly detecting a negative transient.08-09-2012
20110175657DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS - Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.07-21-2011
20100127744DUTY CORRECTION CIRCUIT, DUTY CORRECTION SYSTEM, AND DUTY CORRECTION METHOD - A duty correction circuit is provided which includes a level shifter receives complementary differential input signals having a duty ratio and controls levels of the differential input signals; a TrTf control circuit receives output signals of the level shifter and controls edge angles of the output signals; a waveform shaping circuit receives output signals of the TrTf control circuit and shapes waveforms of the output signals; a first common mode comparator extracts common modes of the output signals of the TrTf control circuit and compares the common modes; and a second common mode comparator extracts common modes of output signals of the waveform shaping circuit and compares the common modes. The level shifter controls the levels based on outputs of the first common mode comparator and the TrTf control circuit controls the edge angles based on outputs of the second common mode comparator.05-27-2010
20110102040SEMICONDUCTOR DEVICE - A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.05-05-2011
20110102039APPARATUS AND METHOD FOR CORRECTING DUTY CYCLE OF CLOCK SIGNAL - A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.05-05-2011
20110102038DUTY RATIO CONTROL APPARATUS AND DUTY RATIO CONTROL METHOD - There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.05-05-2011
20090243685SIGNAL PROCESSING DEVICE - A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1.10-01-2009
20090243684METHOD AND DEVICE FOR GENERATING A DIGITAL DATA SIGNAL AND USE THEREOF - In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data10-01-2009
20080252350CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.10-16-2008
20080252351Generating a Pulse Signal with a Modulated Duty Cycle - Generating an output pulse signal (Y), which has an output signal period (T10-16-2008
20110001532SEMICONDUCTOR DEVICE - A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.01-06-2011
20080204099Clock generator and clock duty cycle correction method - A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal.08-28-2008
20110163789DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE AND SEMICONDUCTOR DEVICE INCLUDING THE DUTY CYCLE CORRECTION CIRCUIT - Provided are a duty cycle correction circuit and method for correcting a duty cycle, and a semiconductor device including the duty cycle correction circuit. The duty cycle correction circuit includes a code generator configured to generate a first and a second duty code for adjusting the duty cycle of a clock to a target duty cycle, and a duty cycle corrector including a plurality of inverter circuits connected in series and whose driving capabilities are adjusted in response to the first and second duty code, wherein the duty cycle corrector is configured to correct the duty cycle of the clock based on the driving capabilities of the inverter circuits and to output a corrected clock.07-07-2011
20090058482Duty detection circuit - Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.03-05-2009
20080197903Clock Pulse Duty Cycle Control Circuit for a Clock Fanout Chip - A clock pulse duty cycle control circuit for receiving an input clock signal and for providing an output clock signal having a desired duty cycle. An error signal generator includes a differential integrator that is connected to receive the output clock signal. The differential integrator integrates the output clock signal to produce a time-varying DC error signal representative of a difference between the output clock signal duty cycle and the desired duty cycle. A duty cycle corrector includes a differential integrator connected to receive the input clock signal and the error signal. The differential integrator integrates the input clock signa to produce a correction stage clock signal. The differential integrator causes the slopes of the input clock signal edges to be adjusted as a function of the error signal. A buffer including a high gain amplifier is connected to receive the correction stage clock signal and squares the edges of the clock signal to produce the output clock signal.08-21-2008
20090015305DIGITIZED METHOD FOR GENERATING PULSE WIDTH MODULATION SIGNALS - A digitized method for generating pulse width modulation (PWM) signals is disclosed. In the digitized method, multiphase PWM signals are generated by altering the reference levels so that fully on duty cycle or fully off duty cycle of each phase PWM signal can be achieved. Therefore, the digitized PWM signal generation method in the present invention can be applied to any application apparatus having boost/buck converter.01-15-2009
20120146696PULSE-WIDTH MODULATION CIRCUIT, A DEVICE INCLUDING THE SAME AND A METHOD FOR PULSE-WIDTH MODULATION - A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.06-14-2012
20120038404DUTY CYCLE BASED PHASE INTERPOLATORS AND METHODS FOR USE - Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.02-16-2012
20120306555Duty cycle adjusting system - A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.12-06-2012
20110304371INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING - Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.12-15-2011
20080204097INVERTER BASED DUTY CYCLE CORRECTION APPARATUSES AND SYSTEMS - Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits.08-28-2008
20110050307CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION - Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.03-03-2011
20100007393Method and Apparatus for Achieving 50% Duty Cycle on the Output VCO of a Phased Locked Loop - Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier. According to another embodiment, a CML-to-CMOS converter circuit is described, including a limiting differential amplifier for generating a single ended clock signal from a differential common mode clock signal, wherein the single ended clock signal has a duty cycle, a low-pass filter for generating a measurement of the duty cycle of the single ended clock signal, and a second differential amplifier for (i) comparing the measurement with a reference voltage and (ii) generating a differential bias current signal in response to the comparison.01-14-2010
20100097112DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES - A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.04-22-2010
20100315143CIRCUIT AND METHOD FOR REDUCING POPPING SOUND - A circuit for reducing popping sound comprises a waveform generator, a voltage accumulator, and a comparator. The waveform generator is configured for generating a periodic waveform, and the voltage accumulator is configured for generating an increased voltage. The comparator is configured for comparing the periodic waveform with the increased voltage for generating a successive pulse signal. A percentage of a duty cycle in the successive pulse signal is increased gradually.12-16-2010
20110316603DUTY COMPENSATION CIRCUIT - A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.12-29-2011
20120007647DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code.01-12-2012
20120206180LEVEL-UP SHIFTER CIRCUIT - A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.08-16-2012
20120154006DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.06-21-2012
20120154005PULSE WIDTH MODULATED SIGNAL GENERATION METHOD AND APPARATUS - Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed.06-21-2012
20110089986METHOD AND APPARATUS FOR PULSE WIDTH MODULATION - An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. A circuit according to aspects of the present invention includes a capacitor to convert a first current to a first voltage on the capacitor during a first time duration and to discharge a second current from the capacitor to change the first voltage to a second voltage during a second time duration. A comparator is also included and is coupled to an output of the capacitor to compare a voltage on the capacitor to a reference voltage during the second time duration to change a pulse width of a periodic output signal in response to an input current.04-21-2011
20100289547PULSE-WIDTH MODULATION (PWM) WITH INDEPENDENTLY ADJUSTABLE DUTY CYCLE AND FREQUENCY USING TWO ADJUSTABLE DELAYS - A pulse width modulation circuit may generate an adjustable output signal that periodically transitions between a first and a second state with an adjustable duty cycle. A first pulse generator circuit may be configured to generate a first pulse signal that periodically transitions at an adjustable delay with respect to a periodic reference signal. A second pulse generator circuit may be configured to generate a second pulse signal that periodically transitions at an adjustable delay with respect to the periodic reference signal. A logic circuit may be configured to generate the adjustable output signal based on both the first and the second pulse signals.11-18-2010
20100207675Semiconductor device - A device includes a first circuit unit performing a detecting operation to detect a ratio of a first time period in which an input signal takes a first logic level to a second time period in which the input signal takes a second logic level. The first circuit unit includes a storing unit and storing a detection result of a detection thereby to the storing unit thereof. The device includes a first control circuit controlling the first circuit unit in response to the input signal. The device includes a current source circuit coupled to the first control circuit at a first circuit node thereof. The device includes an initialization circuit performing an initializing operation to initialize the detection result of the storing unit of the first circuit unit. The device includes a second control circuit controlling the first control circuit such that a voltage level of the first circuit node at a timing at which the initializing operation is terminated is equal to the voltage level of the first circuit node in the detecting operation following the initializing operation.08-19-2010
20090058483DUTY CYCLE CORRECTING CIRCUIT AND METHOD - A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.03-05-2009
20090058481Semiconductor memory device and method for driving the same - A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.03-05-2009
20090115480Clock control circuit and data alignment circuit including the same - A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.05-07-2009
20100271098LOW-OFFSET CHARGE PUMP, DUTY CYCLE STABILIZER, AND DELAY LOCKED LOOP - A charge pump circuit can include a first pair of transistors having connected sources and gates configured to receive a first pump signal and an inverse first pump signal and a second pair of transistors having connected drains and gates configured to receive a second pump signal and an inverse second pump signal, sources of the second pair of transistors being connected to drains of the first pair of transistors at first and second connection nodes, wherein the first and second pair of transistors are all of the same transistor type and provide an output current in response to the first and second pump signals. The charge pump circuit can also include a voltage stabilizer circuit connected to the second connection node and configured to regulate the second connection node to have a voltage within a predetermined range about a selectable voltage. Duty cycle stabilizers and control loops such as delay locked loops can include the charge pump circuit.10-28-2010
20120256669DUTY CYCLE CORRECTION - Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.10-11-2012
20120256670Techniques for Reducing Duty Cycle Distortion in Periodic Signals - A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.10-11-2012
20120081163RF DUTY CYCLE CORRECTION CIRCUIT - A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.04-05-2012
20120280734METHOD AND APPARATUS FOR PULSE WIDTH MODULATION - An integrated control circuit according to aspects of the present invention includes an oscillator, a capacitor, and a logic gate. The oscillator generates a periodic timing signal that cycles between a first logic state for a first time duration and a second logic state for a second time duration. The capacitor receives a charge current in response to the periodic timing signal transitioning to the first logic state, where a voltage on the capacitor increases for the first time duration to an initial value. The logic gate generates a periodic output signal having a duty ratio that is responsive to a time that it takes the capacitor to discharge from the initial value to a reference voltage. A period of the periodic output signal is the period of the periodic timing signal.11-08-2012
20120280733Adjusting circuit of duty cycle and its method - An adjusting circuit of duty cycle includes an edge detecting circuit, a flip-flop connected to the edge detecting circuit, a feedback control circuit connected to the flip-flop and a charge pump circuit connected to the feedback control circuit. The edge detecting circuit detects an edge of an inputted clock signal. The flip-flop sets an outputting terminal thereof at a first level according to a clock signal outputted by the edge detecting circuit. The charge pump circuit controls a duration of the first level outputted the outputting terminal of the flip-flop by charging and discharging a capacitor. The flip-flop sets the outputting terminal thereof at a second level contrary to the first level according to a clock signal outputted by the feedback control circuit. An adjusting method of duty cycle is also disclosed. The adjusting circuit of duty cycle has a simple structure, a stable performance and a fast speed.11-08-2012
20120280732APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT - Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.11-08-2012
20120242387ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT - An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.09-27-2012
20080272815DUTY CYCLE CORRECTION CIRCUITS INCLUDING A TRANSITION GENERATOR CIRCUIT FOR GENERATING TRANSITIONS IN A DUTY CYCLE CORRECTED SIGNAL RESPONSIVE TO AN INPUT SIGNAL AND A DELAYED VERSION OF THE INPUT SIGNAL AND METHODS OF OPERATING THE SAME - A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.11-06-2008
20080231335CIRCUIT TO REDUCE DUTY CYCLE DISTORTION - A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.09-25-2008
20130169330DUTY CYCLE CONTROLLING CIRCUIT, DUTY CYCLE ADJUSTING CELL, AND DUTYCYCLE DETECTING CIRCUIT - A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal.07-04-2013
20110273212SELECTIVE EDGE PHASE MIXING - Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.11-10-2011
20110273211CIRCUIT AND METHOD FOR PROVIDING A CORRECTED DUTY CYCLE - A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.11-10-2011
20130120044DUTY CYCLE DISTORTION CORRECTION CIRCUITRY - Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.05-16-2013
20130141149APPARATUS AND METHOD FOR DUTY CYCLE CALIBRATION - An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.06-06-2013
20100277214DEVICE AND METHOD FOR SIGNAL GENERATION - A signal generator and a method thereof for generating signals are provided. The signal generator includes a pulse width signal generation module and a signal generating module. The pulse width signal generation module generates a first pulse width signal according to a first pulse signal and a second pulse signal. A first signal with a first duty ratio is generated by the signal generating module based on the first pulse width signal. The first duty ratio is equal to a product of a duty ratio of the first pulse signal and a duty ratio of the second pulse signal.11-04-2010
20080197902METHOD AND APPARATUS TO REDUCE PWM VOLTAGE DISTORTION IN ELECTRIC DRIVES - Methods and apparatus are provided for reducing voltage distortion effects at low speed operation in electric drives. The method comprises receiving a first signal having a duty cycle with a range between minimum and maximum achievable duty cycles, producing a second duty cycle based on the minimum achievable duty cycle if the duty cycle is within a distortion range and less than a first clipping value, producing a second duty cycle based on the closer of minimum and maximum pulse widths if the duty cycle is within the distortion range and between the first and a second clipping value, producing a second duty cycle based on the maximum achievable duty cycle if the duty cycle is within the distortion range and greater than the second clipping value, and transmitting a second signal to the voltage source inverter having the second duty cycle.08-21-2008
20080197901Multiple Pulse Width Modulation - A method of generating a MPWM signal for a portable device such as a cellular telephone. For a first duty cycle that includes a MPWM frequency having N magnitude levels, the method generates a first waveform comprising a first and a second On pulse during a first MPWM frequency period. The first and second On pulses are separated by an Off period.08-21-2008
20100283522ALL-DIGITAL SELECTABLE DUTY CYCLE GENERATION - All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.11-11-2010
20120256671SWITCH LEVEL CIRCUIT WITH DEAD TIME SELF-ADAPTING CONTROL - A switch level circuit (10-11-2012
20110309869DUTY CYCLE CORRECTION IN A DELAY-LOCKED LOOP - Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.12-22-2011
20120019299Clock Signal Correction - In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.01-26-2012
20130200934DUTY CYCLE ADJUSTMENT CIRCUIT - A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.08-08-2013
20120086489ADAPTIVE QUADRATURE CORRECTION FOR QUADRATURE CLOCK PATH DESKEW - Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.04-12-2012
20120086488DIFFERENTIAL AMPLIFIERS, CLOCK GENERATOR CIRCUITS, DELAY LINES AND METHODS - A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.04-12-2012

Patent applications in class Duty cycle control