Class / Patent application number | Description | Number of patent applications / Date published |
327165000 | Regenerating or restoring rectangular (e.g., clock, etc.) or pulse waveform | 25 |
20080218232 | TIMING CONTROLLER, DISPLAY DEVICE INCLUDING TIMING CONTROLLER, AND SIGNAL GENERATION METHOD USED BY DISPLAY DEVICE - A display device includes a timing controller and a display unit. The timing controller receives an external clock signal, reads signal generation information, and generates and outputs an internal clock signal based on the read signal generation information. The display unit receives the internal clock signal and displays an image. When the internal clock signal is abnormal, the timing controller rereads the signal generation information and generates and outputs the internal clock signal based on the reread signal generation information. | 09-11-2008 |
20080284478 | DUTY CORRECTION CIRCUIT OF DIGITAL TYPE FOR OPTIMAL LAYOUT AREA AND CURRENT CONSUMPTION - The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase as that of an input clock signal with a distorted duty, and a clock signal having an inverted phase of the phase; a delay line delaying the phase of the clock signal having the inverted phase and generating a feedback clock signal; a phase comparator comparing the phase of the clock signal having the same phase with the phase of the feedback clock signal and generating a delay control signal according to the phase difference between the phases of the clock signal having he same phase and the feedback clock signal; a delay controller controlling the amount of delay of the delay line according to the delay control signal; and a phase mixer performing half-phase blending on the clock signal having the same phase and the feedback clock signal and outputting a clock signal having a corrected duty. | 11-20-2008 |
20090027095 | THRESHOLD CORRECTION CIRCUIT, INTEGRATED CIRCUIT WITH THRESHOLD CORRECTION FUNCTION, AND CIRCUIT BOARD WITH THRESHOLD CORRECTION FUNCTION - In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination without being affected by these noises even if the amplitude of a signal is reduced for higher-speed transmission and lowered electric power, there is provided a configuration comprising a signal generation unit generating a noise monitor signal; a noise monitor signal line receiving and propagating the noise monitor signal; a noise detection unit detecting a noise which has been introduced into that noise monitor signal propagated through the noise monitor signal line and which affects a state discrimination using a threshold; and a threshold adjustment unit, if the noise detection unit detects the noise, adjusting the threshold such that the state discrimination is not affected by the noise. | 01-29-2009 |
20090179677 | CIRCUIT FOR GENERATING OVERLAPPING SIGNALS - A circuit for generating overlapping signals from a single input signal includes a pair of complementary MOS transistors. The complementary MOS transistors have interconnected gates and are connected in series between opposite supply terminals by a chain of successive reciprocal delay stages. The input signal is applied to the interconnected gates, and the drains of the MOS transistors and taps between successive delay stages each form a node that provides one of the overlapping signals. | 07-16-2009 |
20090179678 | Spread Spectrum Clock Interoperability Control and Inspection Circuit - A spread spectrum clock generator (SSCG) control and inspection circuit provides a system and method for inspecting and controlling an external SSCG, and for verifying the modulation profile waveform of an external SSCG. An electronic circuit is included that can check for the presence of an optimal SSCG modulation profile in product subsystems, and in attached modular systems, including electronic plug-in features such as internal network adapters and cartridges. In one mode of the invention, an electronic circuit ensures continued radiated emissions compliance for field replaceable units or consumable parts within a product, such as a printer, a scanner, or a combination (or all-in-one) printer/scanner. In another mode of the invention, an electronic circuit may also act as a secondary security device for consumable products, such as toner cartridges or ink jet cartridges. In yet another mode of the invention, an electronic circuit may also adjust the attached SSCG clock. | 07-16-2009 |
20090237134 | MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A MULTI-LEVEL DE-SKEWING TECHNIQUE - Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction. | 09-24-2009 |
20100052754 | INPUT-SIGNAL RECOVERY CIRCUIT AND ASYNCHRONOUS SERIAL BUS DATA RECEPTION SYSTEM USING THE SAME - An input-signal recovery circuit receives a received data signal and a delay control signal and processes the received data signal. The input-signal recovery circuit includes a data switch detector comprising an input end receiving the received data signal and an output end; a pulse generator comprising a plurality of logic circuits and receiving the received data signal and the delay control signal to generate a plurality of delayed pulse signals; a plurality of switches, each of the switch electrically connected to one corresponding logic circuit, wherein one of the switches is selectively turned on by the data switch detector. The data switch detector selects an output pulse signal from a specific switch when the data switch detector senses a logic state change in the received data signal. The input-signal recovery circuit can prevent data error from error accumulation due to physical difference of crystal oscillators. | 03-04-2010 |
20100109728 | ELECTRONIC DEVICE AND METHOD OF CORRECTING CLOCK SIGNAL DEVIATIONS IN AN ELECTRONIC DEVICE - A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal. The clock correcting means is used to correct the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal. The clock correcting means comprises at least a first and second compensation path (P | 05-06-2010 |
20100164578 | REPEATER CIRCUIT WITH STAGED OUTPUT - A repeater circuit. The repeater circuit includes a first output stage having two output circuits, a second output stage having two additional output circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, and responsive thereto another corresponding output circuit is configured to be activated. The output circuits drive an output signal on the output node. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the other corresponding output circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuits. | 07-01-2010 |
20100231277 | SEMICONDUCTOR INPUT/OUTPUT CONTROL CIRCUIT - In a synchronous semiconductor device ( | 09-16-2010 |
20100271095 | OUTPUT SIGNAL ERROR DETECTION, CIRCUMVENTION, SIGNAL RECONSTRUCTION AND RECOVERY - A method of dealing with anomalies in an output signal is provided. The method includes monitoring transitions in the output signal. When transitions do not occur at expected times, detecting an anomalous signal. Determining the type of anomalous signal based at least in part on the time period of the anomalous signal and conditioning the output signal based on the type of anomalous signal detected. | 10-28-2010 |
20110227622 | BUFFER CIRCUIT AND DUTY CYCLE CORRECTION METHOD USING SAME - A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle. | 09-22-2011 |
20110267122 | ALL-DIGITAL CLOCK DATA RECOVERY DEVICE AND TRANSCEIVER IMPLEMENTED THEREOF - The present invention relates to an all-digital clock data recovery (CDR) which is implemented by a digital filter and a digitally controlled oscillator. The CDR of the present invention comprises a phase detector producing a digital sequence of data and a digital sequence of edge by sampling the serial data stream with a clock, a de-serializer transforming the digital sequences of data and edge into n-bit bus, a digitally controlled oscillator (DCO) implemented by a multi-stage chain of inverters having a variable resistance switching matrix wherein the resistance of each element of the variable resistance switching matrix is varied in such a way that the supply current being fed to each inverter is controlled in pursuant to a digital control code, and thereby producing a clock whose oscillation frequency is updated and fed to the phase detector, a digital synthesis control logic circuit generating a thermometer-code-type digital control code out of the n-bit data and n-bit edge from the de-serializer wherein the thermometer-code-type digital control code is fed to the DCO, and a 2-bit direct forward path directly controlling the frequency of the clock being produced by the DCO with an operating speed which is faster than the digital synthesis control logic circuit by n times. | 11-03-2011 |
20120293224 | DIGITAL CLOCK REGENERATOR - A sampling unit ( | 11-22-2012 |
20120306554 | APPARATUS AND METHODS FOR ALTERING THE TIMING OF A CLOCK SIGNAL - Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal. | 12-06-2012 |
20140152361 | APPARATUS AND METHODS FOR ALTERING THE TIMING OF A CLOCK SIGNAL - Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal. | 06-05-2014 |
20140266358 | LOW-DISTORTION PROGRAMMABLE CAPACITOR ARRAY - In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system. | 09-18-2014 |
327166000 | Having digital device (e.g., logic gate, flip-flop, etc.) | 5 |
20080258786 | Clock regeneration circuit - A clock regeneration circuit includes a half-bit delay device that outputs a half-bit delayed signal B of a multi-level input signal A, a one-bit delay device that outputs a one-bit delayed signal C of the signal A, an adder, an attenuator that forms an threshold signal, an XOR circuit, and a BPF that outputs a clock signal with a frequency corresponding to a bit rate of the XOR signal. The XOR signal is calculated as an XOR of a two-level input signal F, which is a logical zero when a level of the signal A is no more than a level of the threshold signal and otherwise is a logical one, and a two-level input signal G, which is a logical zero when a level of the signal B is no more than the level of the threshold signal and otherwise is a logical one. | 10-23-2008 |
20100176855 | PULSE WIDTH MODULATED CIRCUITRY FOR INTEGRATED DEVICES - An apparatus for producing a separate pulse width modulation signal for each of a plurality of integrated devices, comprising circuitry for each integrated device having structures that :receive and convert a digital signal for each integrated device to an analog voltage level; sample the analog voltage level and storing such analog voltage level; and compare the stored analog voltage level to a common dynamic reference signal and producing a variable width pulse having a first level when the reference signal is above the analog voltage level and a second level when the reference signal is below the analog voltage level, wherein the common dynamic reference signal is the same signal for each integrated device | 07-15-2010 |
20110140749 | INPUT DATA RECOVERY CIRCUIT FOR ASYNCHRONOUS SERIAL DATA TRANSMISSION - An input data recovery circuit is applied for asynchronous serial data transmission such as USB, SATA, or PCI-E. The input data recovery circuit includes two-tier switches controlled by the switching state of input data signal and pulse signals. The input data recovery circuit further includes pulse generator for producing pulse signals to trigger the input data signal and correctly recover the input data signal. The input data recovery circuit can be applied to equipment with high speed protocol because accumulated error between data sending end and data receiving end can be prevented. | 06-16-2011 |
20140021993 | APPARATUSES AND METHODS TO SUPPRESS POWER SUPPLY NOISE HARMONICS IN INTEGRATED CIRCUITS - Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit. | 01-23-2014 |
20140197871 | TRANSMISSION SYSTEM - A signal transmission system ( | 07-17-2014 |
327167000 | Having network providing particular mathematical function (e.g., integrator, etc.) | 3 |
20080309389 | SYSTEM FOR PREVENTING SHOPPING CART PUSH-OUT THEFT - A system and method for preventing push-out theft includes a network of electronic devices that are collectively operable in either a “safe restart” mode” or in an “operational” mode. The network is installed in a shopping area and prevents shopping cart removal from the area when in the “operational” mode. It does this by initially issuing egress permits to every shopping cart. The network then selectively removes egress permits when a shopping cart enters a selected section of the shopping area. Another egress permit is issued when the shopping cart successfully passes a cashier location. Otherwise, a sentry beacon will disable a shopping cart with no egress permit, before it can leave the shopping area. The network defaults to a permit issuing mode whenever a component of the system becomes inoperable. | 12-18-2008 |
20120133406 | Configurable System for Cancellation of the Mean Value of a Modulated Signal - Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance. | 05-31-2012 |
20130135021 | PASSIVE CAPTURE ADAPTER CIRCUIT FOR SENSING SIGNALS OF A HIGH-SPEED CIRCUIT - A multi-stage passive capture adapter (PCA) circuit is configured to sense and recover digital signals present on a high-speed serial bus for capture and analysis in external test equipment. A first stage of the PCA circuit includes a differentiator that functions as a high impedance probe that contacts the serial bus to capture an original input signal waveform of the high-speed digital signals. The signal waveform is fed to a dual-slope comparator/driver that includes a plurality of high-speed comparators and drivers. The second stage includes a differential receiver/shaper that converts logic levels of differential receiver outputs to input signals that set and reset a signal restorer whose output signals are fed to a driver of a driver/shaper. The output of the driver is then fed to a shaper network configured to substantially match an output signal of driver/shaper to the input signal waveform sensed from the high-speed serial bus. | 05-30-2013 |