Class / Patent application number | Description | Number of patent applications / Date published |
327162000 | Having reference source | 41 |
20090015304 | Clock data recovery and synchronization in interconnected devices - For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance. | 01-15-2009 |
20090121762 | TIMEBASE VARIATION COMPENSATION IN A MEASUREMENT INSTRUMENT - Timebase variation compensation in a measurement instrument is achieved by simultaneously acquiring both a signal under test and a reference signal. The reference signal is derived from a source that has very stable timing with respect to the timebase. Timing variations are measured from the acquired signals. Timing variations detected in the reference signal are deemed to reflect variations in the timebase of the test and measurement instrument. The timing variations in the reference signal are used to detect, and compensate for, timebase variation in the signal under test to produce a corrected signal under test that reflects the actual timing variations present in the signal under test. | 05-14-2009 |
20090195280 | INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS - In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability. | 08-06-2009 |
20090219070 | CONTROL DEVICE FOR USE IN A RESONANT DIRECT CURRENT/DIRECT CURRENT CONVERTER - A control device for controlling a switch unit of a resonant direct current/direct current converter includes a frequency modulation controller and a pulse selector. The frequency modulation controller is adapted to be coupled electrically to the converter for receiving a correcting threshold value and output information of the converter, and for generating a synchronization signal according to the correcting threshold value and the output information received thereby. The pulse selector is adapted to be coupled electrically to the converter and the frequency modulation controller for receiving the correcting threshold value, the output information and the synchronization signal, and for generating a driving signal according to the correcting threshold value, the output information and the synchronization signal received thereby. The driving signal is adapted to drive the switch unit and has a working period. The driving signal switches between high and low signal levels at a frequency that is substantially equal to that of the synchronization signal during the working period. | 09-03-2009 |
20100019814 | SEMICONDUCTOR IC DEVICE AND DATA OUTPUT METHOD OF THE SAME - A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal. | 01-28-2010 |
20100026355 | Load drive device and control system of the same - A load drive device for driving an inductive load by PWM controlling a switching element includes synchronization control unit, a synchronization signal input terminal, and a synchronization signal output terminal. The synchronization control unit outputs the PWM signal to the switching element. The synchronization control unit receives a synchronization signal through the input terminal from an exterior. The synchronization control unit outputs the synchronization signal through the output terminal to an exterior. When the synchronization control unit does not receive the synchronization signal, the synchronization control unit outputs the synchronization signal such that a first switching period of the PWM signal is prevented from overlapping with a second switching period of a PWM signal of an external device. When the synchronization control unit receives the synchronization signal, the synchronization control unit generates the PWM signal based on the synchronization signal. | 02-04-2010 |
20100182062 | AUDIO PROCESSOR WITH INTERNAL OSCILLATOR-GENERATED AUDIO INTERMEDIATE FREQUENCY REFERENCE - An integrated circuit audio processor having an internal-oscillator generated intermediate frequency reference provides for operation of an audio processor without requiring an external master clock. Input audio streams are sample-rate converted to an intermediate sample rate derived from the internal oscillator, which may be an LC oscillator. One or more output audio streams are generated from the one or more input audio streams at the intermediate sample rate and are converted from the intermediate sample rate to corresponding output sample rates. A divider generates the intermediate sample rate from the oscillator output, and is programmed to control the intermediate sample rate to ensure that the intermediate sample rate is in the proper range for operation of the integrated circuit. The divider can be programmed to accommodate changes in process, voltage and/or temperature of the IC, so that the intermediate sample rate is maintained near an expected frequency. | 07-22-2010 |
20100194459 | CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS - Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path. | 08-05-2010 |
20110001530 | METHOD AND APPARATUS FOR RECEIVING BURST DATA WITHOUT USING EXTERNAL DETECTION SIGNAL - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 01-06-2011 |
20110001531 | Method and apparatus for receiving burst data without using external detection signal - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 01-06-2011 |
20110032015 | SYSTEMS AND METHODS FOR CLOCK CORRECTION - A method, apparatus and system for correcting different clock domains are disclosed. The disclosed implementations correct a second clock domain by making reference to a resampling filter, or similar device, used to correct a first clock domain. The implementations thereby facilitate clock correction using fewer or a different variety of elements. | 02-10-2011 |
20110128058 | SIGNAL PROCESSING DEVICE - A signal processing device includes: a wiring unit including a plurality of signal input terminals, wirings extending from the signal input terminals, and a wiring concentration section on which the wirings are concentrated; a plurality of electronic circuit units, each including a device that outputs a signal, an output control section that controls a timing at which the device outputs the signal, and a signal output terminal coupled to the signal input terminal; and a control unit that supplies a reference timing signal to the plurality of electronic circuit units, wherein each of the output control section controls a timing at which the signal is output based on the reference timing signal and phase difference information indicative of a phase difference between the signal and the reference timing signal. | 06-02-2011 |
20110187429 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same. | 08-04-2011 |
20110221498 | SYSTEM FOR SYNCHRONIZING OPERATION OF A CIRCUIT WITH A CONTROL SIGNAL, AND CORRESPONDING INTEGRATED CIRCUIT - A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops. | 09-15-2011 |
20120038403 | SEMICONDUCTOR CIRCUIT AND METHOD OF RETRIEVING SIGNAL TO SEMICONDUCTOR CIRCUIT - In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance. | 02-16-2012 |
20120139597 | HIGH PRECISION SYNCHRONISATION METHOD AND SYSTEM - Method of synchronising clocks between a first reference clock and a second clock to be slaved on the frequency of the reference clock, the two sharing a common clock, this method comprising the following steps: | 06-07-2012 |
20120256668 | METHOD FOR ADJUSTING A TIME BASE FOR A TIRE PRESSURE MEASUREMENT UNIT - Method of controlling the drifting of a low-frequency LFO circuit in a wheel unit of a tire pressure monitoring system, each wheel unit including temperature and pressure sensors in conjunction with a signal control circuit, the sensors being activated according to an LFO circuit time base integrated into the control circuit. An RF emission circuit of each wheel unit transmits data stored in a memory and an identifier of the unit to a central unit. The emission circuit is regulated by a high-precision clock. In each wheel unit, a variation between a measured temperature and a reference temperature is compared with a variation threshold and a drift between the periods of the time base of the LFO circuit and of the clock is determined. The drift is used to adjust the time base to the period of the clock if the temperature variation ΔTi is greater than this threshold ΔT. | 10-11-2012 |
20120313681 | SIGNAL SYNCHRONIZING SYSTEMS - A signal synchronizing system includes comparison circuitry and control circuitry. The comparison circuitry compares a synchronizing signal with an input signal to generate a comparison result. The control circuitry adjusts the synchronizing signal into a range that is determined by the input signal, and controls the range according to the comparison result. | 12-13-2012 |
20130021074 | DECISION FEEDBACK EQUALIZER OPERABLE WITH MULTIPLE DATA RATES - Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates. | 01-24-2013 |
20130162314 | SIGNAL OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods. | 06-27-2013 |
20130222027 | INTEGRATED CIRCUIT, MICRO-CONTROLLER UNIT, AND METHOD INCLUDING A SYNCHRONOUS SAMPLING CONTROLLER - A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module. | 08-29-2013 |
20130234767 | 3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT - There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata. | 09-12-2013 |
20140035642 | Techniques for Aligning and Reducing Skew in Serial Data Signals - A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. | 02-06-2014 |
327163000 | By phase | 18 |
20080258785 | Periodic signal synchronization apparatus, systems, and methods - Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed. | 10-23-2008 |
20090039933 | SYSTEM AND METHOD - System and method, including path sections, each path section including a supply line into which a medium-frequency current is able to be injected by an infeed assigned to the particular path section, | 02-12-2009 |
20090079486 | SIGNAL GENERATOR WITH SIGNAL TRACKING - Frequency and phase of an output signal is adjusted to track an input signal. A control signal is adjusted to control a frequency of an oscillating signal from which the output signal is derived. In some aspects the frequency of the oscillating signal is adjusted by reconfiguration of reactive circuits coupled to an oscillator circuit. Phase of the output signal may be adjusted based on comparison of the oscillating signal with an adjustable threshold. For example, the adjustable threshold may comprise an adjustable bias signal for a transistor circuit whereby the oscillating signal is provided as an input to the transistor circuit and the output of the transistor circuit provides the output signal. | 03-26-2009 |
20090102528 | SEMICONDUCTOR INTEGRATED CIRCUIT - During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. | 04-23-2009 |
20090195281 | Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System - A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period. | 08-06-2009 |
20090243681 | Embedded Source-Synchronous Clock Signals - A synchronous communication system includes two transmitters that transmit respective first and second data signals that are phase offset from one another by about 90 degrees. On the receive side, a pair of extraction circuits extract a first clock signal from the first data signal and a second clock signal from the second data signal. The clock signals are offset from one another by about 90 degrees due to the phase offset of the corresponding data signals. Edges of the first clock signal are thus centered within the symbols of the second data signal, and edges of the second clock signal are centered within the symbols of the first data signal. A pair of receivers employs the first clock signal to sample the second data symbol and the second clock signal to sample the first data signal. | 10-01-2009 |
20100066422 | CLOCK TIMING CALIBRATION CIRCUIT AND CLOCK TIMING CALIBRATION METHOD FOR CALIBRATING PHASE DIFFERENCE BETWEEN DIFFERENT CLOCK SIGNALS AND RELATED ANALOG-TO-DIGITAL CONVERSION SYSTEM USING THE SAME - A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal. | 03-18-2010 |
20100066423 | PHYSICAL QUANTITY DETECTION CIRCUIT AND PHYSICAL QUANTITY SENSOR DEVICE - A physical quantity detection circuit ( | 03-18-2010 |
20100207674 | METHOD FOR SYNCHRONIZING A PLURALITY OF MEASURING CHANNEL ASSEMBLIES AND/OR MEASURING DEVICES, AND APPROPRIATE MEASURING DEVICE - A method and a measuring device for synchronizing measuring channel assemblies are provided. A reference signal is produced by a reference signal source. The reference signal is supplied to the individual measuring channel assemblies of the measuring device. A clock signal generator is used to produce a clock signal at a low frequency, the clock signal generator being connected to each measuring channel assembly by a respective connecting line of the same length. The clock signal is supplied through a phase corrector element for the purpose of correcting the phase of the reference signal in each measuring channel assembly to the phase of the clock signal. | 08-19-2010 |
20100308880 | LOW POWER CLOCK AND DATA RECOVERY PHASE INTERPOLATOR - A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of current source circuits, and the current source circuits comprise a plurality of transistors, and the transistors of the current source circuits are coupled to one another by the drains of the transistors. | 12-09-2010 |
20110012656 | SEMICONDUCTOR INTEGRATED CIRCUIT - During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. | 01-20-2011 |
20110148492 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal. | 06-23-2011 |
20110169540 | CLOCK AND DATA RECOVERY FOR BURST-MODE SERIAL SIGNALS - A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device. | 07-14-2011 |
20110309868 | Data transfer unit, data transmission device, data receiving device, and control method - A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer. | 12-22-2011 |
20130076419 | Piecewise Linear Phase Interpolator - In one embodiment, a phase interpolator with a phase range of n degrees, where 0m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal. | 03-28-2013 |
20140312948 | METHOD AND SYSTEM FOR SYNCHRONIZING THE PHASE OF A PLURALITY OF DIVIDER CIRCUITS IN A LOCAL-OSCILLATOR SIGNAL PATH - A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits. | 10-23-2014 |
20150137865 | PHASE ESTIMATING DEVICE, SIGNAL GENERATING DEVICE, SYNCHRONIZING SYSTEM, AND SIGNAL PROCESSING DEVICE - According to one embodiment, a phase estimating device includes a periodic signal obtaining unit that obtains a first periodic signal, and a wireless time synchronizing unit that synchronizes a reference time with that of a signal generating device by wirelessly communicating with the signal generating device that outputs a second periodic signal according to phase information. The phase estimating device includes a reference time storing unit that stores the reference time synchronized with that of the signal generating device by the wireless time synchronizing unit. The phase estimating device includes a phase determining unit that obtains sampled times from the reference time storing unit at timing at which the first periodic signal rises above or falls below a predetermined level, and determines phase information on a phase of the first periodic signal based on the obtained sampled time and period information on a period of the first periodic signal. | 05-21-2015 |
20160065192 | COMPENSATION TIME COMPUTING METHOD and DEVICE FOR CLOCK DIFFERENCE - The present invention provides a method for computing compensation time for clock difference between a first chip and a second chip. The method comprises emitting, by the second chip, a pulse with a fixed pulse length to the first chip; measuring, by the first chip, a pulse length of the pulse; computing the compensation time according to the measure pulse length and the fixed pulse length; and setting the compensation time to the second chip. | 03-03-2016 |