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With delay means

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327141000 - Synchronizing

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DocumentTitleDate
20120200330SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR CHIP AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.08-09-2012
20090195279DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.08-06-2009
20090121761INTRA-PAIR DIFFERENTIAL SKEW COMPENSATION METHOD AND APPARATUS FOR HIGH-SPEED CABLE DATA TRANSMISSION SYSTEMS - A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew.05-14-2009
20130076418System and Method for Calibration of Timing Mismatch for Envelope Tracking Transmit Systems - One embodiment of the present invention relates to a system for calibrating of timing between an amplifier input signal and a modulated supply power. The system includes a supply modulation component, an error metric component, and a delay determiner. The supply modulation component provides the modulated supply power and the amplifier input signal according to an input signal and a set delay signal. The error metric component provides information from a transmitted amplitude signal and a received amplitude signal. The delay determiner generates timing adjustments in the form of the set delay signal from the error metric information.03-28-2013
20100045351INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY - Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.02-25-2010
20130038367DEVICE WITH AUTOMATIC DE-SKEW CAPABILITY - A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.02-14-2013
20130135020MULTI-PHASE CLOCK SIGNAL GENERATION CIRCUITS - Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. The circuit block MD05-30-2013
20090115477Circuit Device and Related Method for Mitigating EMI - In order to mitigate electromagnetic interference (EMI), the present invention provides a circuit device for an electronic device including a signal generating unit, a phase adjusting unit and an output interface. The signal generating unit generates a plurality of in-phase signals. The phase adjusting unit is coupled to the signal generating unit and is used for adjusting the plurality of in-phase signals to generate a plurality of output signals, where all or some of the output signals have different phases. The output interface is coupled to the phase adjusting unit and is used for outputting the plurality of output signals to a plurality of signal processing units for image processing.05-07-2009
20090302910DELAY TIME MEASURING METHOD, DELAY TIME ADJUSTING METHOD, AND VARIABLE DELAY CIRCUIT - A variable delay circuit 12-10-2009
20120218016SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING PLURAL DELAY PATHS AND CONTROLLER CAPABLE OF BLOCKING SIGNAL TRANSMISSION IN DELAY PATH - A semiconductor integrated circuit device, includes a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal, a delay detection unit that detects respective delay times in the plurality of delay paths, and a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path. The control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths.08-30-2012
20090079484Pre-distorting a transmitted signal for offset cancellation - In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.03-26-2009
20090079483DELAY CIRCUITS MATCHING DELAYS OF SYNCHRONOUS CIRCUITS - Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.03-26-2009
20090267668METHOD AND APPARATUS FOR CALIBRATING A DELAY CHAIN - Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed.10-29-2009
20090267667Low Power Programmable Clock Delay Generator with Integrated Decode Function - A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.10-29-2009
20110012655LOCKED LOOPS, BIAS GENERATORS, CHARGE PUMPS AND METHODS FOR GENERATING CONTROL VOLTAGES - Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages. The charge pump and the bias generator can also include circuitry for limiting the charging of the capacitor when the control voltage is relatively low.01-20-2011
20130162313SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first structural body including a first temperature voltage generation unit configured to generate first and second temperature voltages which have different voltage level variations according to a temperature variation, in response to a temperature measurement command, and a first temperature information determination unit configured to generate first temperature information depending on a difference between levels of the first and second temperature voltages; and a second structural body including a second temperature voltage generation unit configured to generate a third temperature voltage and a fourth temperature voltage which have different voltage level variations according to a temperature variation, when a predetermined time elapses after the first and second temperature voltages are generated from the first structural body, and a second temperature information determination unit configured to generate second temperature information depending on a difference between levels of the third and fourth temperature voltages.06-27-2013
20100253406APPARATUS AND METHOD FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION OF THE TIME DELAY OF A DIGITAL DELAY LINE - A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.10-07-2010
20110298512CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY - A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.12-08-2011
20090115476PROGRAMMABLE HIGH-RESOLUTION PHASE DELAY - A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase difference between the input signal and the delayed output signal. An accumulator provides a delay command signal as a function of a difference between a commanded delay and the actual phase difference. A programmable phase delay circuit is configured to generate a ramp signal based upon the input signal, to adjust the ramp signal with respect to a threshold level in response to the delay command signal, to generate a trigger signal based upon a comparison of the ramp signal with the threshold level, and to clock the delayed output signal in response to the trigger signal.05-07-2009
20100176854DELAY CIRCUIT - Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (07-15-2010
20110291723STREAM SIGNAL TRANSMISSION DEVICE AND TRANSMISSION METHOD - Provided is a stream signal transmission device that can eliminate transmission delay fluctuation with a fast change such as network jitter with high accuracy and synchronize a plurality of streams. The stream signal transmission device includes at least one reception unit that receives a stream signal to which a time code is attached from a network, at least one extraction unit that extracts the time code from the stream signal received by the reception unit, and at least one delay control unit that determines an output time by adding a predetermined fixed delay to a time indicated by the time code extracted by the extraction unit, and outputs the stream signal received by the reception unit after holding the stream signal up to the output time.12-01-2011
20100090737CLOCK DATA RECOVERY CIRCUIT AND METHOD - A change-point detection circuit 04-15-2010
20110291722PHASE CORRECTION CIRCUIT - A phase correction circuit includes a skew detection unit configured to generate first skew detection signals and second skew detection signals by comparing multi-phase signals with one another, a phase control signal generation unit configured to generate a plurality of phase control signals by combining the first skew detection signals with the second skew detection signals, and a phase adjustment unit configured to delay the multi-phase signals by delay time corresponding to the plurality of the phase control signals.12-01-2011
20100033221CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS - A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.02-11-2010
20090237133SWITCHING CONTROL CIRCUIT FOR MULTI-CHANNELS AND MULTI-PHASES POWER CONVERTER OPERATED AT CONTINUOUS CURRENT MODE - A switching control circuit for multi-channels and multi-phases power converter according to the present invention comprises a master control circuit and a slave control circuit. The master control circuit generates a multiplier signal in response to an input voltage and an output voltage of the power converter, and generates a first switching signal to switch a first inductor of the power converter in accordance with the multiplier signal and the first-current signal generated by a first current-sense device. The slave control circuit generates a second switching signal to switch a second inductor of the power converter in accordance with the multiplier signal, the first switching signal and a second-current signal generated by a second current-sense device. Once the power converter is at light-load, the multiplier signal is disabled to turn off the second switching signal to turn off the slave control circuit for power saving of the power converter.09-24-2009
20110215852HIGH SPEED LATCH CIRCUIT WITH METASTABILITY TRAP AND FILTER - A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.09-08-2011
20090189660SEMICONDUCTOR DEVICE - A semiconductor device includes an input circuit, an output circuit, and a test circuit that is adapted to evaluate delaying of a signal which is input to the input circuit to be output from the output circuit. The test circuit includes a first delay circuit for delaying a signal output from the input circuit, a second delay circuit which is configured of a plurality of serially connected gate circuits and is adapted to further delay a signal output from the first delay circuit, a through-path which is configured of a wiring pattern and is adapted to transmit the signal output from the first delay circuit, a selector that selects one of a signal output from the second delay circuit and a signal transmitted through the through-path according to a control signal to supply the selected signal to the output circuit, and a control signal generating circuit that generates the control signal according to the signal output from the input circuit so as to allow the selector to alternately select the signal output from the second delay circuit and the signal transmitted through the through-path.07-30-2009
20090146713CLOCK SIGNAL GENERATING CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.06-11-2009
20080272813Analog To Digital Converter Clock Synchronizer - The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must receive a radio frequency signal and simultaneously use circuitry where the timing of the operations are based on the received RF signal and circuitry where the timing is based on a fixed rate signal with sensitivity to clock jitter. According to an exemplary embodiment, the apparatus comprises, a first input (RefClk), a second input (PllClk), an output (CLK 11-06-2008
20100085096ENERGY-EFFICIENT CLOCK SYSTEM - A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time.04-08-2010
20110148491SEMICONDUCTOR APPARATUS AND LOCAL SKEW DETECTING CIRCUIT THEREFOR - A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to receive a predetermined signal and generate a reference delay signal by delaying the predetermined signal by a delay time and a first timing detecting block located on one edge of the semiconductor apparatus, the first timing detecting block being configured to receive the predetermined signal, generate a first delay signal by delaying the predetermined signal by the delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.06-23-2011
20080211557SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS - The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.09-04-2008
20090115479METHODS AND APPARATUS FOR SYNCHRONIZING WITH A CLOCK SIGNAL - Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.05-07-2009
20090167390Data transfer device and electronic camera - A data transfer device can adjust a phase of a clock signal with a simple configuration in a short period of time when transferring a digital data signal in synchronization with the clock signal. Accordingly, the data transfer device includes a data transfer line serially transferring the data signal, a clock transfer line transferring the clock signal, a decision unit deciding an adjustment amount by which the phase of the clock signal accompanying the data signal is shifted, the adjustment amount being used when transferring the data signal in synchronization with the clock signal, and a phase adjusting unit shifting the phase of the clock signal in accordance with the adjustment amount decided by the decision unit while keeping a frequency of the clock signal fixed.07-02-2009
20080290919CLOCK GENERATOR FOR SEMICONDUCTOR MEMORY APPARATUS - The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.11-27-2008
20100201418Variable-Length Digitally-Controlled Delay Chain With Interpolation-Based Tuning - A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.08-12-2010
20080303570METHOD AND APPARATUS FOR SYNCHRONOUS CLOCK DISTRIBUTION TO A PLURALITY OF DESTINATIONS - Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.12-11-2008
20100201417Clock extraction circuit - Error occurrence is predicted before the error occurs. Included are: a clock regeneration circuit (08-12-2010
20080309388METHOD FOR ADJUSTING PHASE RELATIONSHIP BETWEEN SIGNALS IN A MEASURING APPARATUS, AND A MEASURING APPARATUS - A measuring apparatus having a frequency-swept heterodyne-type frequency converter equipped with a frequency-swept signal source and a multiplier includes means for detecting the timing of reference burst signals that have been subjected to frequency conversion by the frequency converter, with the frequency of the output signals of the frequency-swept signal source locked; means for generating periodic pulse signals; and means for adjusting the phase relationship between the pulse signals and the reference burst signals using the detected timing; and means for sweeping the frequency of the output signals of the frequency-swept signal source using pulse signals that have been subjected to a phase relationship adjustment.12-18-2008
20080303571Delay Circuit - A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals.12-11-2008
20080309387DLL CIRCUIT - A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units being equal to the delay time of each of the first delay units; and a blocking control circuit configured to control the blocking circuit whether to pass or block the delayed signal that is input in the blocking circuit.12-18-2008
20080211556SEMICONDUCTOR INTEGRATED CIRCUIT - A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof.09-04-2008
20090184743Deskew system for eliminating skew between data signals and clock and circuits for the deskew system - A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.07-23-2009
20120068748Phase Detection Method and Phase Detector - This invention relates to a phase detection method. An input signal (03-22-2012
20090140784HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS - A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.06-04-2009
20120229186MEMORY INTERFACE CIRCUIT AND DRIVE CAPABILITY ADJUSTMENT METHOD FOR MEMORY DEVICE - Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width.09-13-2012
20110221497METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS - Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.09-15-2011
20090096499Apparatus and method for power amplification with delay control in wireless communication system - A transmitting apparatus and method for power amplification with delay control in a wireless communication system are provided. The apparatus includes signal converters, a delay difference measurer, and a delay controller. The signal converters separate a baseband signal into an envelope signal and a phase modulated signal. The delay difference measurer measures a delay difference between an envelope signal path and a phase modulated signal path using a correlation coefficient extraction and interpolation technique. The delay controller sets a delay in a clock period unit to a signal path having a small delay and sets a delay by a remainder delay difference to a signal path having a large delay, depending on the measured delay difference.04-16-2009
20100164576TRANSIT STATE ELEMENT - A transit state element circuit. The transit state element circuit includes a clock input stage coupled to receive a clock signal, an output stage configured to drive an output signal on an output node and an activation stage coupled to an input node. The activation stage is configured to, responsive to the clock input stage detecting a transition from a first logic level to a second logic level and detecting a logical transition of an input signal on the input node, activate the output stage to drive an output signal on the output node. A storage element is configured to capture a logic value of the input signal when the clock is at the second logic level and to store the logic value, and to provide the output signal on the output node when the clock signal is at the first logic level.07-01-2010
20090201060CLOCK SYNCHRONIZING CIRCUIT - A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.08-13-2009
20090243680DATA SIGNAL GENERATING APPARATUS - It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means 10-01-2009
20120194243SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF - A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.08-02-2012
20100271093ADJUSTMENT APPARATUS, ADJUSTMENT METHOD AND TEST APPARATUS - Provided is an adjustment apparatus that adjusts signal output timings, comprising a control section that causes a first signal output section to output a signal having a rising edge and causes a second signal output section to output a signal having a falling edge; a signal acquiring section that acquires a composite signal obtained by combining the signal output by the first signal output section and the signal output by the second signal output section; and an adjusting section that adjusts a timing difference between a signal output timing of the first signal output section and a signal output timing of the second signal output section, such that the signal acquiring section acquires the composite signal having a composite waveform in which the rising edge and the falling edge overlap.10-28-2010
20120194242SIGNAL DELAY APPARATUS FOR PROVIDING EXACT DELAY AMOUNT, MEMORY APPARATUS UTILIZING THE SIGNAL DELAY APPARATUS, AND SIGNAL DELAY METHOD - A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.08-02-2012
20100148833DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.06-17-2010
20100156490DELAY CIRCUIT - Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.06-24-2010
20090079482METHOD AND SYSTEM FOR CONTROLLING A DELAY CIRCUIT FOR GENERATION OF SIGNALS UP TO EXTREMELY HIGH FREQUENCIES - Aspects of a method and system for generation of signals up to extremely high frequencies using a delay circuit are provided. In this regard, a variable delay circuit may be adjusted such that an output signal generated by the delay circuit may be twice the frequency of a signal input to the delay circuit. The adjustment may be via an variable capacitance and/or a variable number of delay elements utilized to generate the output signal. Moreover, the adjustment may be based on a signal strength of the output signal. In this regard, the delay may be adjusted to maximize the signal strength of the output signal. The input signal may be delayed to generate a second signal that is 90° phase shifted relative to the input signal. The second signal and the input signal may be mixed to generate the output signal. The output signal may be filtered by a a bandpass filter centered at twice the frequency of the input signal. Accordingly, the center frequency of the bandpass filter may be tunable.03-26-2009
20090079485PHASE DETECTOR FOR REDUCING NOISE - The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.03-26-2009
20100231276DIGITAL ELECTRONIC DEVICE AND METHOD OF ALTERING CLOCK DELAYS IN A DIGITAL ELECTRONIC DEVICE - A digital electronic device is provided with a first and second sequential logic unit (SS09-16-2010
20110057699INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY - Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.03-10-2011
20110057698METHOD AND APPARATUS FOR SYNCHRONIZING WITH A CLOCK SIGNAL - Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.03-10-2011
20100219869SEMICONDUCTOR INTERGRATED CIRCUIT AND SIGNAL ADJUSTING METHOD - A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings, a second signal generator that generates a third signal having a delay relative to the first signal, and a detector that detects, when a state of the third signal changes, a delay state of a signal based on the states of the second signals, wherein the first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state.09-02-2010
20090108893Electric circuit and method for designing electric circuit - A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.04-30-2009
20110001529SIGNAL PROCESSING CIRCUIT, AGC CIRCUIT, AND RECORDING AND PLAYBACK DEVICE - Disclosed herein is a signal processing circuit including: a main path configured to transmit an input signal and output an actual signal; and a negative feedback path configured to feed back the actual signal to an input stage of the main path, wherein the main path includes a main path block that receives an input signal and outputs an actual signal, the negative feedback path includes a negative feedback block that generates a control signal and supplies the control signal to an input part of an input signal of the main path; a replica block that is supplied with a control signal of the negative feedback block to output a pseudo actual signal, and imitates the main path block; and a signal delay block that delays a pseudo actual signal of the replica block by a dead time of a loop.01-06-2011
20110109360SYSTEM AND METHOD FOR IMPROVED TIMING SYNCHRONIZATION - Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal is used to define a “frame” consisting of a predetermined number of clock periods, and a reset signal is used to define a larger period consisting of a predetermined number of frames. Due to a variety of system parameters, the innate delay time associated with each respective timing distribution path may differ. The system is operable to adjust the timing signals propagated to the plurality of host devices along each respective timing distribution path to compensate for these differences so that each host device remains synchronized with all other host devices.05-12-2011
20090033392Delay locked loop with improved jitter and clock delay compenstating method thereof - A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.02-05-2009
20090033391CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE - A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.02-05-2009
20090033389MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES - Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.02-05-2009
20100164577SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.07-01-2010
20110241743APPARATUS AND METHOD FOR SYNCHRONIZING TIMING CLOCK BETWEEN TRANSMISSION SIGNAL AND RECEPTION SIGNAL - Provided are an apparatus and method for synchronizing a timing clock between a transmission signal and a reception signal. The apparatus for synchronizing a timing clock includes a timing restorer configured to restore a timing clock based on a digital input data; and a timing clock synchronizer configured to synchronize the timing clock based on timing information and a timing restoration signal restored in the timing restorer.10-06-2011
20100026353Semiconductor device for constantly maintaining data access time - The semiconductor device may include a calibration circuit, a control unit, and a delay unit. The calibration circuit may be configured to output an output signal. The control unit may be configured to generate and output the control signal in response to the output signal of the calibration circuit. The control unit may generate the control signal by using a correlation between a signal transmission speed of the semiconductor device and the output signal of the calibration circuit. The delay unit may be configured to delay a clock signal in response to the control signal and output the delayed clock signal to the output driver.02-04-2010
20110084744Semiconductor device, adjustment method thereof and data processing system - Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured.04-14-2011
20090315601DEVICE AND METHOD FOR TIMING ERROR MANAGEMENT - A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal.12-24-2009
20090039932DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as an output signal, wherein the delay time can be one selected from a plurality of delay times according to the sensing signal. The delay time can be selectively determined according to a clock frequency used in a semiconductor memory apparatus.02-12-2009
20090033390SIGNAL PROCESSING APPARATUS AND CONTROL METHOD THEREOF - A signal processing apparatus and a control method thereof are provided. The signal processing apparatus includes: a signal processor which respectively processes an input video signal and an input audio signal; a communication unit which is communicably linked with an external audio output unit that outputs the audio signal; and a controller which controls the signal processor to delay and process one of the video signal and the audio signal by a delay value corresponding to the external audio output unit if the external audio output unit is predetermined.02-05-2009
20110102037CIRCUIT FOR RESETTING SYSTEM AND DELAY CIRCUIT - A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage.05-05-2011
20110248757DIGITAL CALIBRATION DEVICE AND METHOD FOR HIGH SPEED DIGITAL SYSTEMS - A digital calibration device and method for a high speed digital system. A digital calibration device coupled to a timing device in a high speed digital system for digitally calibrating the timing device includes a delay estimator, a control logic, and a digitally controlled load unit. In operation, the delay estimator calculates a delay value indicative of a timing delay between a first output and a second output of a timing device of the high speed digital system. Further, the control logic generates a control signal based on the delay value. Furthermore, the digitally controlled load unit applies at least one of a first load to a non-delayed line and a second load to a delayed line of the timing device based on the control signal to calibrate a timing delay between the non-delayed line and the delayed line of the timing device.10-13-2011
20090085623BIAS SIGNAL DELIVERY - Provided herein are approaches for controlling remote slave DLL circuits with a master DLL circuit by conveying a relevant bias signal as a current signal instead of as a voltage signal.04-02-2009
20080252346CIRCUIT HAVING A CLOCK SIGNAL SYNCHRONIZING DEVICE WITH CAPABILITY TO FILTER CLOCK-JITTER - A circuit having a clock signal synchronizing device with capability to filter clock-jitters is disclosed. One embodiment provides a delayed locked loop with capability to filter clock-jitter. Further, the invention relates to a clock signal synchronizing method with capability to filter clock-jitter.10-16-2008
20110095797SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.04-28-2011
20110175656CIRCUIT INCLUDING CURRENT-MODE LOGIC DRIVER WITH MULTI-RATE PROGRAMMABLE PRE-EMPHASIS DELAY ELEMENT - A circuit (07-21-2011
20080218231MULTIPLE OUTPUT TIME-TO-DIGITAL CONVERTER - A differential line compensation apparatus, semiconductor chip and system are disclosed.09-11-2008
20100026354Delay Amount Estimating Apparatus and Signal Transmitting Apparatus - A delay amount estimating apparatus includes a delay value search section that searches for a first delay value smaller than a delay setting value at which a given correlation value between an input signal and a feedback signal is provided, and also for a second delay value greater than the delay setting value, the feedback signal coming from a signal processing apparatus that applies signal processing on the input signal, wherein respective correlation values of the first delay value and the second delay value satisfy a given condition; and a delay estimating section that estimates a delay amount of the feedback signal relative to the input signal based on the first delay value and the second delay value.02-04-2010
20090174448DIFFERENTIAL COMMUNICATION LINK WITH SKEW COMPENSATION CIRCUIT - A system and method is presented for reducing skew between the positive and negative components of a differential signal in a high speed communications link. The communications link includes a signal generator producing and transmitting complementary positive and negative signals over separate transmission lines and a receiver receiving the complementary signals. The communication link further includes a skew compensation circuit having a skew detector, a controller, and separate delay and buffer elements for both the positive and negative component of the differential signal. The controller separately controls each of the delay or buffer elements in response to the detected skew between differential signal components.07-09-2009
20110304369METHOD FOR SOURCE SYNCHRONOUS HIGH-SPEED SIGNAL SYNCHRONIZATION - A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.12-15-2011
20110316600Serial Link Receiver and Method Thereof - A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision.12-29-2011
20110316602SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING - Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.12-29-2011
20110316601Method and Device for Delaying Activation Timing of Output Device - A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a first mirror current, delaying an enable signal of the circuit system according to the first mirror current to generate a charging activation signal, providing a charging current according to the charging activation signal, and determining the activation moment of the output device according to the activation current.12-29-2011
20110156785TRIMMING OF A PSEUDO-CLOSED LOOP PROGRAMMABLE DELAY LINE - An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal.06-30-2011
20110156784CLOCK DELAY CORRECTING DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.06-30-2011
20120044004TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.02-23-2012
20100315141MULTIPLE-STAGE, SIGNAL EDGE ALIGNMENT APPARATUS AND METHODS - Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.12-16-2010
20110089985Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator - A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.04-21-2011
20110089984Clock signal balancing circuit and method for balancing clock signal in IC layout - A method for balancing clock signals in an IC layout includes obtaining a data-flow information of the IC, selecting a first data-flow according to the dataflow information, and synchronizing a first clock signal from a first register and a second clock signal from a second register involved in the first data-flow. The data processed by the first register is directly transmitted to the second register or transmitted through a combinational logic circuit to the second register. The first data-flow is not related to other data-flows included in the data-flow information.04-21-2011
20120119806DATA OUTPUT CIRCUIT - A data output circuit includes an output control signal generation unit configured to generate output control signals in response to an output enable bar signal and a delay locked clock signal and a register configured to output stored data in response to the output control signals.05-17-2012
20120119805CLOCK GATER WITH PROGRAMMABLE DELAY - An integrated circuit device includes first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry including second logic devices and a clock gater operable to receive the clock signal and distribute the clock signal to the second logic devices. The clock gater comprises a programmable delay circuit.05-17-2012
20120126869TIMING SKEW ERROR CORRECTION APPARATUS AND METHODS - Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.05-24-2012
20120212269SINGLE-INVERSION PULSE FLOP - A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer.08-23-2012
20120249201CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation circuit includes a clock delay control signal generation unit and a doubler clock generation unit. The clock delay control signal generation unit divides a clock signal to generate a divided clock signal, generates a plurality of periodic signals for a half period of the divided clock signal, and generates clock delay control signals from the plurality of periodic signals. The doubler clock generation unit delays the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generates an output clock signal in response to the clock signal and the delayed clock signal.10-04-2012
20100052753CLOCK SIGNAL DIVIDING CIRCUIT - A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.03-04-2010
20090115478Data output controller - Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.05-07-2009
20100271094Signal Alignment System - Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal.10-28-2010
20100271092LOW-POWER SOURCE-SYNCHRONOUS SIGNALING - Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.10-28-2010
20120262210CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.10-18-2012
20110121875POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF - A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.05-26-2011
20080297218VARIABLE CAPACITANCE WITH DELAY LOCK LOOP - An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.12-04-2008
20120319752LOOK-UP TABLES FOR DELAY CIRCUITRY IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) CHIPSETS - A method, new use for Look-Up Tables (LUTs), and a Field Programmable Gate Array (FPGA) chipset are provided for delaying data signals. The FPGA comprises an input and a set of LUTs operationally connected to and receiving from the interface a data signal and a clock signal. The set of LUTs delay the data signal by a delay so that a corresponding first delayed data signal output from the set of LUTs is so synchronized with the clock signal for appropriate sampling of the delayed data signal to be performed by the FPGA chipset. A process of manufacturing of the FPGA chipset comprises calculating a delay for delaying and synchronising the data signal with a clock signal to meet requirements of the chipset, calculating a number of LUTs for delaying the data signal, and implementing in a data path of the data signal the number of LUTs.12-20-2012
20120319753INTEGRATED CIRCUIT PULSE GENERATORS - An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.12-20-2012
20130009685DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER - A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.01-10-2013
20080252347DEVICE FOR DETECTING A TIMING OF AN EDGE - A device and method for detecting timing of an edge of a signal with respect to a timing of a predefined edge of a periodic signal is provided, wherein the edge defines a state change between a first state and a second state of the signal, and wherein the device can include: a phase-shift element to shift the phase of the signal relative to the phase of the periodic signal by a phase shift value at which the state change can be sensed at a point in time determined by the timing of the predefined edge; and a detection element to detect the timing of the edge relative to the timing of the predefined edge on the basis of the phase shift value. The phase-shift element can be an adjustable delay element for delaying the signal by an adjustable delay value as a phase shift value.10-16-2008
20080252345SYSTEM AND METHOD FOR GENERATING A RESET SIGNAL - Systems and methods are provided to generate a reset signal, such as to facilitate synchronization. In one embodiment, a system to generate a reset signal includes an offset generator that provides an offset clock signal having a frequency offset relative to a frequency of an input clock signal. A reset generator generates the reset signal in response to detecting a periodic phase shift between the offset clock signal and the input clock signal.10-16-2008
20080231334CLOCK SIGNAL TRANSMISSION CIRCUIT - A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied.09-25-2008
20130176062TIME DELAY CIRCUIT AND METHOD OF GENERATING TIME DELAYED SIGNAL - A delay circuit includes an input port, an output port, a first delay circuit block, a second delay circuit block, and an inverter module. The first delay circuit block is coupled to the input port and configured to generate an intermediate signal by applying a first delay to an input signal. The inverter module has an input terminal and an output terminal. The input terminal of the inverter module is coupled to the first delay circuit block, and the inverter module is configured to generate an inverted intermediate signal at the output terminal. The second delay circuit block is coupled to the output terminal of the inverter module and configured to generate a delayed signal by applying a second delay to the inverted intermediate signal.07-11-2013
20130176063SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first chip including a first port configured to receive an operation clock signal, a first circuit configured to operate in synchronization with the operation clock signal, and a second chip mounted on the first chip. The second chip includes a delay control part configured to generate a delay control signal indicating a delay amount based on a cycle of a reference clock signal, plural delay circuits connected in multiple stages and configured to delay clock signals input to the plural delay control circuits based on the delay control signal and sequentially output the delayed clock signals to a subsequent stage, and a second port connected to the first port and configured to receive the operation clock signal based on the delayed clock signals output from the plural delay circuits.07-11-2013
20080218230CLOCK TEST APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A clock test apparatus for a semiconductor integrated circuit includes a delay unit configured to delay an internal clock signal. A comparison unit compares the phase of an output signal of the delay unit with the phase of a reference clock signal. A phase discrimination unit receives a test mode signal, the reference clock signal, and an output signal of the comparison unit, thereby outputting a discrimination signal.09-11-2008
20130093484DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.04-18-2013
20080197900DELAY LOCKED LOOP FOR CONTROLLING DELAY TIME USING SHIFTER AND ADDER AND CLOCK DELAYING METHOD - A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.08-21-2008
20100308879PHASE SYNCHRONIZATION DEVICE AND PHASE SYNCHRONIZATION METHOD - A sampling section (12-09-2010
20100315142HIGH-SPEED SOURCE-SYNCHRONOUS SIGNALING - A system for communicating data between a first integrated circuit device and a second integrated circuit device. The first iterated circuit device transmits a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition. The first integrated circuit device then delays the data, so that the data is delayed relative to the timing signal by a first predetermined delay time. Next, the first integrated circuit device transmits the delayed data to the second integrated circuit device, which receives the tinting signal and the delayed data. Next, the second integrated circuit device delays the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition. The second integrated circuit device then senses the data during a time interval between the delayed version of the first transition and the second transition.12-16-2010

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