Class / Patent application number | Description | Number of patent applications / Date published |
327160000 | With counter | 35 |
20080284477 | ON-CHIP JITTER MEASUREMENT CIRCUIT - An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay. | 11-20-2008 |
20090184742 | Externally Synchronizing Multiphase Pulse Width Modulation Signals - Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to “capture” the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases. | 07-23-2009 |
20090231004 | DIGITAL CYCLE CONTROLLED OSCILLATOR AND METHOD FOR CONTROLLING THE SAME - An oscillator is disclosed. The oscillator comprises a cycle controller and a re-cycle delay line module. The cycle controller generates a cycle control signal. The re-cycle delay line module produces a periodic signal. The re-cycling delay line module performs a re-cycling operation. The number of re-cycling in the re-cycling operation is determined based on the cycle control signal. | 09-17-2009 |
20090267666 | Phase Difference Detector And Phase Difference Detection Method - A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting. | 10-29-2009 |
20100007392 | CRYSTAL AUTO-CALIBRATION METHOD AND APPARATUS - A system for automatically calibrating a crystal of a communication device and a method thereof are described. The system comprises a timing generator for generating a timing signal, a timing adjustment device coupled with the timing generator and for adjusting the timing of the timing signal responsive to receipt of an adjustment signal, and a calibration device coupled with the timing adjustment device and arranged to transmit the adjustment signal responsive to a comparison between the timing signal and a reference signal. | 01-14-2010 |
20100141317 | SPREAD-PERIOD CLOCK GENERATOR - A spread-period clock generator (SPC) counts basic clock pulses (XK) to generate output pulses (EQ) with varying periods, and has means (controlled by signal QS) for switching between a first mode, in which counting is carried out in response to the leading edges of the basic clock pulses (CK), and a second mode, in which counting is carried out in response to the trailing edges of the basic clock pulses (CK). Accordingly, if mode switching (signal QS) is carried out during a counting operation, the counting period is altered by a portion of a basic clock period (CK). Thus, the number of different periods of the output pulses can be increased without increasing the basic clock frequency (input WC, signal LK, CK). | 06-10-2010 |
20100141318 | TRIGGER SIGNAL DETECTION APPARATUS - A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal. | 06-10-2010 |
20100225371 | Methods of Operating Timers to Inhibit Timing Error Accumulation - Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M−N equals±1). | 09-09-2010 |
20100289545 | OSCILLATION CIRCUIT, TIMING DEVICE, AND ELECTRONIC SYSTEM UTILIZING THE SAME - An oscillation circuit including a first transistor, a second transistor, a current source, a first inverter, and an impedance unit is disclosed. The first transistor has a first source receiving a first operation voltage, a first drain, and a first gate coupled to the first drain. The second transistor has a second source receiving the first operation voltage, a second drain, and a second gate coupled to the first gate. The current source is coupled between the first drain and a grounding voltage. The first inverter generates an oscillation signal and has a first input terminal, a first output terminal, and a first power terminal coupled to the second drain. The impedance unit is coupled between the first input terminal and the first output terminal. | 11-18-2010 |
20110050306 | TIME CORRECTION CIRCUIT AND ELECTRONIC APPARATUS - A time correction circuit includes: a time-measurement device that measures a time period; a receiver device that receives electromagnetic wave based on a first baseband signal, the first baseband signal including time information concerning time and being encoded by a pulse width modulation method, and outputs a second baseband signal based on the electromagnetic wave received; and an asynchronous circuit that corrects the time based on the second baseband signal, wherein the asynchronous circuit executes a specified process to retrieve the time information from the second baseband signal based on the time period measured, at least one of when the second baseband signal changes from high level to low level and when the second baseband signal changes from low level to high level, and assumes a standby state after executing the specified process. | 03-03-2011 |
20110204945 | CALIBRATION - A method of calibrating a module whose operation is dependent upon a module clock signal, the method comprising: over each calibration period of a plurality of such periods, obtaining a measure of the frequency of an observed signal, the observed signal being the module clock signal or a clock signal generated based upon the module clock signal; influencing operation of the module in dependence upon the obtained measures so as to calibrate the module; and for each said calibration period, taking account of a position in time of the end of that calibration period relative to a particular feature of the observed signal and delaying the start of the following calibration period relative to a subsequent said particular feature of the observed signal in dependence upon that position. | 08-25-2011 |
20110204946 | SYSTEM AND METHOD FOR SYNCHRONIZING ASYNCHRONOUS SIGNALS WITHOUT EXTERNAL CLOCK - One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device. | 08-25-2011 |
20110298511 | STROBE SIGNAL MANAGEMENT TO CLOCK DATA INTO A SYSTEM - A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal. | 12-08-2011 |
20120025884 | Method and Apparatus for Conveying and Reproducing Multiple Independent Timebases Using a Shared Reference Clock, Clock Snapshots and a Packet Network - Disclosed are methods and systems of conveying and reproducing independent timebases in a network. The methods include distributing a common measurement clock and a common measurement clock counter to a plurality of cards in a master chassis in the network. Distributed master clock counters are locked to an external input signal in each of the plurality of cards. Periodic snapshots of a count value generated by the master clock counter are taken. A counter speed of the master clock counter is analyzed to create a future snapshot of the count value. The future snapshot of the count value is transmitted from the master chassis to at least one receiving chassis in the network. The association between master counters and slave counters is programmable by various means including modifying the routing of the snapshot packets. | 02-02-2012 |
20120044003 | SKEW ADJUSTMENT CIRCUIT AND SKEW ADJUSTMENT METHOD - A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which a plurality of signals transmitted through the signal lines are respectively input, has: a plurality of delay circuits, respectively provided in stages preceding the buffer circuits; a monitoring circuit monitoring changes in the signals of the plurality of signal lines; and a delay adjustment circuit, which decides delay amounts for the plurality of delay circuits based on a monitoring result output of the monitoring circuit, and sets the delay amounts in the plurality of delay circuits. The monitoring circuit detects, as the monitoring result, a number of signal changes in the signal lines in which a signal change occurs in a monitoring period, and the delay adjustment circuit decides the delay amounts based on the number of signal changes. | 02-23-2012 |
20120319751 | HIGH RESOLUTION CAPTURE - The high resolution capture (HRCAP) of this invention enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock. | 12-20-2012 |
20130027103 | Frequency Locking Oscillator - A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle. | 01-31-2013 |
20130076416 | SUB-MICRON CMOS VCO THAT USES DELAY-BASED CALIBRATION AND METHOD OF OPERATION - A system for calibrating a circuit comprising a delay to voltage converter for receiving an input signal and generating an output signal that represents a delay metric. A counter for receiving the output signal and generating a binary output as a function of the delay metric. | 03-28-2013 |
20130076417 | MAINTAINING PULSE WIDTH MODULATION DATA-SET COHERENCY - Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle. | 03-28-2013 |
20130278312 | SYNCHRONIZATION OF MULTIPLE SIGNAL CONVERTERS - The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal. | 10-24-2013 |
20130278313 | TRIGGER SIGNAL DETECTION APPARATUS - A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal. | 10-24-2013 |
20140015579 | SYSTEM HAVING HALF-CYCLE PRECISION - A system that may include a slow clock event generator arranged to generate the slow clock event; a fast clock edge type detector that is arranged to perform a determination process of determining whether an earliest fast clock edge that occurs within a slow clock event is a rising clock edge or a falling clock edge, and whether a last fast clock edge that occurs within the slow clock event is a rising clock edge or a falling clock edge; and a counter module that is arranged to count fast clock cycles during the slow clock event to provide a duration estimate indicative of duration of the slow clock event and generate a slow clock event duration value indicative of the duration of the slow clock event, in response to the duration estimate and to a determination result that is indicative of an outcome of the determination process. | 01-16-2014 |
20140062555 | PROPAGATION SIMULATION BUFFER - Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay. | 03-06-2014 |
20140103978 | LOW POWER DATA RECOVERY - In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal. | 04-17-2014 |
20140176209 | CLOCK GENERATION CIRCUIT AND CLOCK GENERATION SYSTEM USING THE SAME - A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes. | 06-26-2014 |
20140240014 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple BER test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation. | 08-28-2014 |
20140292390 | DATA TRANSMISSION CIRCUITS AND SYSTEM HAVING THE SAME - Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal. | 10-02-2014 |
20140333360 | Modulated Clock Synchronizer - The present invention relates to a signal synchronization circuit comprising at least one synchronizer ( | 11-13-2014 |
20150015314 | MESOCHRONOUS SYNCHRONIZER WITH DELAY-LINE PHASE DETECTOR - A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal. | 01-15-2015 |
20150042389 | LOW POWER TIMING, CONFIGURING, AND SCHEDULING - A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device. | 02-12-2015 |
20150084679 | PANEL DRIVING CIRCUIT AND RING OSCILLATOR CLOCK AUTOMATIC SYNCHRONIZATION METHOD THEREOF - A ring oscillator clock automatic synchronization method of a panel driving circuit includes steps of: when a vertical blanking interval happens, a master driver generates a pulse signal to slave drivers respectively. A pulse width of the pulse signal equals to N times of a master ring oscillator clock, wherein N is larger than 0. When a slave driver receives the pulse signal, the slave driver uses its slave ring oscillator clock to count the pulse width of the pulse signal to obtain that the pulse width of the pulse signal equals to M times of the slave ring oscillator clock, wherein M is larger than 0. The slave driver compares M with N and automatically adjusts the slave ring oscillator clock according to the comparison result to make it achieve synchronization with the master ring oscillator clock. | 03-26-2015 |
20150109039 | TUNABLE CLOCK SYSTEM - A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented. | 04-23-2015 |
20150137864 | CIRCUIT DELAY MONITORING APPARATUS AND METHOD - A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period. | 05-21-2015 |
20160006445 | ASYNCHRONOUS SAMPLE RATE CONVERTER - An asynchronous sample rate converter and method for converting an input signal to a resampled output signal is disclosed. An efficient and cost-effective sample rate converter for converting an input signal of arbitrary sample rate to a resampled output signal of a second sample rate is disclosed. A hardware-efficient sample-rate converter for resampling an audio input signal with an arbitrary sample rate to an output audio signal with a known sample rate for use in an audio processor is disclosed. | 01-07-2016 |
20160204774 | PULSE WIDTH MODULATION SIGNAL GENERATION CIRCUIT AND METHOD | 07-14-2016 |