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With variable delay means

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327141000 - Synchronizing

327155000 - With feedback

327156000 - Phase lock loop

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DocumentTitleDate
20130043918MULTI PHASE CLOCK SIGNAL GENERATOR, SIGNAL PHASE ADJUSTING LOOP UTILIZING THE MULTI PHASE CLOCK SIGNAL GENERATOR, AND MULTI PHASE CLOCK SIGNAL GENERATING METHOD - A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units.02-21-2013
20130043919SEMICONDUCTOR DEVICE HAVING DELAY LINE - Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.02-21-2013
20130027102FRACTIONAL AND INTEGER PLL ARCHITECTURES - A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.01-31-2013
20100156489DLL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a DLL circuit including: a first phase determination circuit that compares phases of rising edges of an external clock and a first internal clock; a second phase determination circuit that compares phases of falling edges of the external clock and the first internal clock; an adjusting unit that adjusts positions of active edges of internal clocks based on determination results; and a control circuit that sets one of adjustment amounts of the second and third internal clocks to a larger value than the other, in response to a fact that adjustment directions of the active edges of the second and third internal clocks are mutually the same. With this arrangement, a duty can be set nearer to 50% while performing phase adjustment. Accordingly, the time required to lock the DLL circuit can be shortened.06-24-2010
20100117697SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION - There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.05-13-2010
20090195277SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLK08-06-2009
20120169388METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.07-05-2012
20110193602JITTER SUPPRESSION CIRCUIT AND JITTER SUPPRESSION METHOD - There is provided a jitter suppression circuit and a jitter suppression method in which both shortening of a pull-in time and high jitter suppression characteristics is satisfied.08-11-2011
20100073053DELAY LOCKED LOOP FOR HIGH SPEED SEMICONDUCTOR MEMORY DEVICE - A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.03-25-2010
20080290918DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DELAYING AND LOCKING CLOCK IN SEMICONDUCTOR MEMORY APPARATUS - A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.11-27-2008
20130082755FILTERING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.04-04-2013
20090179675DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.07-16-2009
20130038366BIST CIRCUIT FOR PHASE MEASUREMENT - A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.02-14-2013
20100102863DELAY CLOCK GENERATOR - A delay clock generator includes a plurality of delay element arrays arranged in parallel; a feed side transfer line and a return side transfer line provided in each of the delay elements which make up the delay element arrays, and that transfer a clock signal in a feed direction and a return direction; a selector selecting a first transfer route that couples the feed side transfer lines to each other along the preceding and succeeding delay elements and a third transfer route that couples the return side transfer lines to each other along the preceding and succeeding delay elements, and a second transfer route that couples the feed side transfer lines and the return side transfer lines of each of the delay elements; and a decoder causing the selector to select the second transfer route for one of the delay elements in the delay element array.04-29-2010
20100109727SEMICONDUCTOR DEVICE - A semiconductor device for providing a reliable data valid window includes a drive control unit configured to output a driving power control signal in response to an internal clock and a command signal; a sub-drive voltage supply unit configured to supply sub-drive voltages; a main drive unit configured to generate a delay-locked loop (DLL) clock by driving the internal clock with a main drive voltage; a sub-drive unit configured to drive the internal clock with the sub-drive voltage in response to the driving power control signal; and a data output driver configured to drive and output a data signal in sync with the DLL clock, wherein the main drive unit and the sub-drive unit share their output terminal.05-06-2010
20100109725DLL CIRCUIT HAVING DUTY CYCLE CORRECTION AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.05-06-2010
20100109726SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING OUTPUT ENABLE SIGNAL - A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency.05-06-2010
20100321077PHASE SYNCHRONIZATION APPARATUS - A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.12-23-2010
20120262209Multi-Phase Clock Generator and Data Transmission Lines - An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.10-18-2012
20090146707DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals.06-11-2009
20130135019PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME - A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.05-30-2013
20090322389JITTER ATTENUATING DELAY LOCKED LOOP (DLL) USING A REGENERATIVE DELAY LINE - In general, in one aspect, the disclosure describes a delay locked loop (DLL) with a regenerative delay line that includes a cascade of delay stages. A first delay stage includes a two-input delay device which receives a 180 degree phase shifted signal as feedback. This feedback signal configures the delay line into a regenerative amplifier, the frequency response of which has peaking or resonance at the input frequency which results in jitter filtering. The amount of regeneration is determined by relative strength of an input signal and the feedback signal. Relative strength is determined by relative size of devices receiving the signals. The resonant frequency (with or without oscillations) of the delay line may automatically be tuned to the incoming clock frequency by the DLL control loop. Each of the other delay stages may include two-input delay devices with the inputs shorted for uniformity.12-31-2009
20090243678Delay locked-loop circuit and display apparatus - A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.10-01-2009
20100079180AC-COUPLING PHASE INTERPOLATOR AND DELAY-LOCKED LOOP USING THE SAME - An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.04-01-2010
20090045858DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.02-19-2009
20090045857DELAY LOCKED LOOP CIRCUIT - A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.02-19-2009
20090045856CLOCK SIGNAL SYNCHRONIZING DEVICE WITH INHERENT DUTY-CYCLE CORRECTION CAPABILITY - One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.02-19-2009
20130049831POLYPHASE CLOCK GENERATOR - A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.02-28-2013
20100134165TIME-TO-DIGITAL CONVERTER AND ALL-DIGITAL PHASE-LOCKED LOOP - A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.06-03-2010
20120218015DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.08-30-2012
20090091363DLL CIRCUIT - A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.04-09-2009
20090091362DEVICE, SYSTEM AND METHOD OF DELAY CALIBRATION - System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.04-09-2009
20090273381DELAYED LOCKED LOOP CIRCUIT - A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.11-05-2009
20090267665SEMICONDUCTOR MEMORY DEVICE FOR GENERATING A DELAY LOCKED CLOCK IN EARLY STAGE - A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.10-29-2009
20090267664PLL CIRCUIT - In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.10-29-2009
20090267663ELECTRONIC SYSTEM THAT ADJUSTS DLL LOCK STATE ACQUISITION TIME - One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.10-29-2009
20120223755DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.09-06-2012
20120223754DELAY CIRCUITRY - Integrated circuits with delay circuitry are provided. Delay circuitry may receive a clock signal and generate a corresponding delayed clock signal. The delayed clock signal generated using the delay circuitry may exhibit reduced duty cycle distortion in comparison to conventional systems. The delay circuitry may include a pulse generation circuit, a delay circuit, and a latching circuit. The pulse generation circuit may generate pulses in response to detecting rising edges or falling edges at its input. The pulses may propagate through the delay circuit. The latching circuit may generate (reconstruct) a delayed version of the clock signal in response to receiving the pulses at its control input. The delay circuitry may be used in duty cycle distortion correction circuitry, delay-locked loops, and other control circuitry.09-06-2012
20130063194Circuit for the Clocking of an FPGA - The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.03-14-2013
20090009225CLOCK SIGNAL GENERATOR - A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.01-08-2009
20100085095APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.04-08-2010
20130162310CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY - A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.06-27-2013
20130162311FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP - A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.06-27-2013
20130162312DELAY LOCKED LOOP - A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.06-27-2013
20130207701SEMICONDUCTOR DEVICE HAVING DUTY-CYCLE CORRECTION CIRCUIT - Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.08-15-2013
20120268180DELAY LOCKED LOOP - A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.10-25-2012
20110025389CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHODS FOR GENERATING JITTER COMPENSATED CLOCK SIGNALS - Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal.02-03-2011
20120112810CLOCK DE-SKEWING DELAY LOCKED LOOP CIRCUIT - A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.05-10-2012
20090009224Multiphase DLL using 3-edge phase detector for wide-range operation - The invention discloses a new architecture of multiphase delay-locked loop (DLL) with innovative 3-edge phase detector (3-edge PD), which compares the VCDL's first delay interval and the last delay interval to send an Up pulse or a Dn pulse to adjust the interval among those delay clock phases. The DLL may achieve both wide-range operation and multiple clock phase generation, and is also immune to multi-selection problem.01-08-2009
20110193603FAST MEASUREMENT INITIALIZATION FOR MEMORY - Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact.08-11-2011
20090115474CLOCK SYNCHRONIZATION CIRCUIT AND CLOCK SYNCHRONIZATION METHOD - A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage.05-07-2009
20110279157DEVICE - A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.11-17-2011
20090189656Delay-locked loop and a stabilizing method thereof - A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage.07-30-2009
20110279156PROGRAMMABLE FINE LOCK/UNLOCK DETECTION CIRCUIT - An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.11-17-2011
20130021073DLL PHASE DETECTION USING ADVANCED PHASE EQUALIZATION - A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an Onlx mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal is used to terminate the ForceSL and Onlx modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during Onlx exit, and resulting in faster DLL locking time.01-24-2013
20090284291COMPLEMENTARY SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE COMPRISING SAME - A complementary signal generation circuit includes a first transmission path including a first number N of inverters and a second transmission path including a second number (N−1) of inverters. A delay circuit composed of a first resistance element and a capacity element is arranged in series between two inverters in the second transmission path so as to correspond to any one of the inverters in the first transmission path. The capacity element is formed by a capacitive inverter having the same input capacity ratio as the any one of the inverters. The complementary signal generation circuit generates output signals having the logic levels which are complementary to each other through the first and second transmission paths.11-19-2009
20100007390Clock generating circuit, power converting system, and related method with spread spectrum for EMI reduction - A clock signal generating circuit includes a main delay circuit and a variable delay circuit. The main delay circuit receives a feedback clock signal, and outputs an output clock signal after a first delay when receiving the feedback clock signal. The variable delay circuit receives the output clock signal, and updates the feedback clock signal after a second delay when receiving the output clock signal. The second delay is periodically varied and is shorter than the first delay.01-14-2010
20090284290DLL CIRCUIT ADAPTED TO SEMICONDUCTOR DEVICE - A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.11-19-2009
20110109358CONTROL VOLTAGE TRACKING CIRCUITS, METHODS FOR RECORDING A CONTROL VOLTAGE FOR A CLOCK SYNCHRONIZATION CIRCUIT AND METHODS FOR SETTING A VOLTAGE CONTROLLED DELAY - Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.05-12-2011
20120187993Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization - There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.07-26-2012
20120105119INTEGRATED CIRCUIT - An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.05-03-2012
20110291718CLOCK GENERATION CIRCUIT AND DELAY LOCKED LOOP USING THE SAME - A clock generation circuit includes a plurality of variable delay units configured to control a delay of an input clock signal under the control of delay control signals assigned thereto among a plurality of delay control signals, and output a plurality of delayed clock signals; a phase comparison unit configured to compare a phase of a reference clock signal which has a predetermined phase difference from the input clock signal and a phase of a delayed clock signal which is outputted from any one variable delay unit among the plurality of variable delay units; and a delay control unit configured to generate the plurality of delay control signals based on a comparison result from the phase comparison unit.12-01-2011
20110298509TIME-SHARED LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.12-08-2011
20110291721Wide Frequency Range Delay Locked Loop - A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.12-01-2011
20110291720DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.12-01-2011
20110291719PHASE CORRECTION CIRCUIT, DATA ALIGNMENT CIRCUIT AND METHOD OF ALIGNING DATA USING THE SAME - Various exemplary embodiments of a phase correction circuit are disclosed. In one exemplary embodiment, the phase correction circuit may include a delay unit configured to delay a clock signal by a predetermined delay time and generate a delay clock signal, a delay line configured to delay a data strobe signal by a variable delay time in response to a delay control signal and generate a corrected data strobe signal, a phase detector configured to detect a phase difference between the delay clock signal and the corrected data strobe signal and generate a phase detection signal, and a shift register configured to generate the delay control signal in response to the phase detection signal.12-01-2011
20110291717SEMICONDUCTOR DEVICE - A semiconductor device includes a delay locked loop including a replica delay unit which is configured to delay a signal reflecting a delay amount of an output path of a signal, and a delay time compensator configured to compensate for a difference of a delay time between the replica delay unit and the output path by comparing an output signal of the replica delay unit and an output signal of the output path.12-01-2011
20100090736DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.04-15-2010
20110298510VOLTAGE-CONTROLLED DELAY LINES, DELAY-LOCKED LOOP CIRCUITS INCLUDING THE VOLTAGE-CONTROLLED DELAY LINES, AND MULTI-PHASE CLOCK GENERATORS USING THE VOLTAGE-CONTROLLED DELAY LINES - A delay-locked loop circuit includes a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed from one another to produce an earliest delayed clock signal to a latest delayed clock signal, the voltage-controlled delay line including an anti-jitter delay circuit and a plurality of delay circuits, the anti-jitter delay circuit configured to output the earliest delayed clock signal, and the plurality of delay circuits coupled in series and configured to output a remainder of the plurality of delayed clock signals, a phase frequency detection circuit configured to generate an up signal and a down signal based on the earliest delayed clock signal and the latest delayed clock signal, a filter configured to generate the voltage control signal in response to the up signal and the down signal, and a lock detection circuit configured to generate the lock signal in response to the up signal and the down signal.12-08-2011
20080303567DELAY LOCKED LOOP CIRCUIT - A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.12-11-2008
20100264969PHASE INTERPOLATOR WITH ADAPTIVE DELAY ADJUSTMENT - The phase interpolator includes two adjustable delays 10-21-2010
20100033219SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes a delay locked loop (DLL) control block configured to generate a buffer enable signal, the buffer enable signal being a pulse signal that is periodically enabled when a smart power down signal is enabled, and a DLL circuit configured to control a phase of an external clock signal in response to the buffer enable signal to generate an output clock signal.02-11-2010
20100033218SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.02-11-2010
20100033217Delayed-Locked Loop with power-saving function - A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power.02-11-2010
20100264967CLOCK AND DATA RECOVERY CIRCUITS - A clock and data recovery (CDR) circuit is provided. The CDR circuit receives a data signal and generates a clock signal. The CDR circuit comprises an oscillator, a phase detector, and a first voltage-to-current (V-to-I) converter. The oscillator generates the clock signal according to an oscillation voltage. The phase detector receives the data signal. The phase detector comprises a mixer for detecting a phase difference between the data clock and the clock signal and generating a phase detection signal which represents the phase difference. The first V-to-I converter receives the phase detection signal and generates a first current signal according to a voltage level of the phase detection signal to vary the oscillation voltage.10-21-2010
20110215851DLL INCLUDING 2-PHASE DELAY LINE AND DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF - Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.09-08-2011
20090278580CLOCK CONTROL CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A clock control circuit includes a clock delay device, an edge detection device, a phase determination device and a delay control device. The clock delay device generates a delayed rising clock and a delayed falling clock by delaying a rising clock and a falling clock, which are transferred from a clock generation circuit, in response to a control signal, and to transfer the delayed rising clock and the delayed falling clock to a data output buffer. The edge detection device detects a difference between an edge timing of the delayed rising clock and an edge timing of the delayed falling clock to generate edge detection signals. The phase determination device detects a duty ratio of each of the edge detection signals to generate phase determination signals. The delay control device generates the control signal in response to the phase determination signals.11-12-2009
20090189658DLL circuit, semiconductor device using the same, and method for controlling DLL circuit - There is provided a DLL circuit that uses a small amount of area on a chip, and is compatible with a wide range of clock frequencies. The DLL circuit has a delay line 07-30-2009
20120187991CLOCK STRETCHER FOR VOLTAGE DROOP MITIGATION - A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to receive a group of phase shifted versions of the clock signal and to output one of the group of phase shifted versions of the clock signal as an output clock signal. A control component may receive the output clock signal from the multiplexer and a voltage droop event signal indicating whether a voltage droop event is occurring in a power supply. The control component may control, in response to the voltage droop event signal indicating the occurrence of the voltage droop event, the multiplexer to iteratively select the group of phase shifted versions of the clock signal to reduce the frequency of the output clock signal.07-26-2012
20110267119Wideband analog phase shifter - A phase shifter includes a low-pass filter, a high-pass filter, and an all-pass filter coupled in series between an RF input terminal and an RF output terminal of the phase shifter, at least one of the filters being tunable, controlling the phase of an input signal over a wide range of frequencies.11-03-2011
20090146709DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME - A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.06-11-2009
20090146706DLL CLOCK SIGNAL GENERATING CIRCUIT CAPABLE OF CORRECTING A DISTORTED DUTY RATIO - A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.06-11-2009
20090146711CLOCK SIGNAL GENERATING CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.06-11-2009
20090146705DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register outputs a digital signal in accordance with a phase difference between an input signal and a feedback signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input signal and an output signal in a delay locked loop circuit is also disclosed.06-11-2009
20090066380DOUBLE DATA RATE INTERFACE - The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.03-12-2009
20100123496MULTIPLE INPUT PLL WITH HITLESS SWITCHOVER BETWEEN NON-INTEGER RELATED INPUT FREQUENCIES - A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.05-20-2010
20090146712DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY - A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system.06-11-2009
20090146710Signal generating circuit - A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first time which is shorter than one cycle of the reference clock, a control section including a gate circuit holding the output of the input stage delay circuit for a second time which is shorter than one cycle of the reference clock from a point at which the output of the input stage delay circuit is changed to output a signal corresponding to the output of the gate circuit, and an output stage delay circuit outputting a signal delaying the output signal of the control section by the second time, in which the input stage delay circuit switches an output state in response to change of the output signal of the control section.06-11-2009
20090146708DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal.06-11-2009
20110012654LOCKING STATE DETECTOR AND DLL CIRCUIT HAVING THE SAME - A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.01-20-2011
20100123497Phase delay line - A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage equal division to time equal division converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the input of the voltage equal division to time equal division converter. The voltage can be precisely divided, and the number of the phases can be easily controlled and expanded. The band gap reference technology enables the working points not affected by the temperature. The negative feedback mechanism of the phase-locked loop determines the period, phase, duty-cycle of the sawtooth wave are same with the reference clock. The ascending and descending time of the sawtooth wave are precisely equal.05-20-2010
20100123499INFORMATION SYSTEM, SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR - An information system with an enhanced effect in reducing jitter with a short period. An input clock signal CLKi is output via a voltage-controlled delay circuit 05-20-2010
20090302909SEMICONDUCTOR DEVICE HAVING DELAY LOCKED LOOP AND METHOD FOR DRIVING THE SAME - A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.12-10-2009
20100141312DELAY LOCKED LOOP CIRCUIT AND OPERATION MEHTOD THEREOF - A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.06-10-2010
20110063006TIMING VERNIER USING A DELAY LOCKED LOOP - A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal.03-17-2011
20110063005DELAY-LOCKED LOOP HAVING A DELAY INDEPENDENT OF INPUT SIGNAL DUTY CYCLE VARIATION - A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.03-17-2011
20090243679Semi-Digital Delay Locked Loop Circuit and Method - A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.10-01-2009
20090206897SKEW ADJUSTMENT CIRCUIT AND A METHOD THEREOF - Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.08-20-2009
20090206898Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage - Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.08-20-2009
20090256604REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT - A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL operation and sequentially toggled. The registered controlled DLL circuit for generating a DLL clock by delaying internal clocks includes a timing pre-pulse generating unit configured to generate a plurality of timing pre-pulses activated sequentially in response to a source clock, the plurality of pre-pulses being repeated two or more times in each delay shifting update period, a mask signal generating unit configured to generating a mask signal having a logic level varied according to toggling of a predetermined one of the timing pre-pulses, and a timing pulse outputting unit configured to output the plurality of timing pre-pulses as a plurality of timing pulses in response to the mask signal.10-15-2009
20080315927FREQUENCY ADJUSTING APPARATUS AND DLL CIRCUIT INCLUDING THE SAME - A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.12-25-2008
20110199138Semiconductor device and test method thereof - A semiconductor device includes a PLL (Phase Locked Loop) circuit configured to generate a reception clock signal and a transmission clock signal based on a reference clock signal which has been subjected to frequency-modulation; a serializer configured to convert parallel data into serial data in response to the transmission clock signal to output the serial data; and a CDR (Clock Data Recovery) circuit configured to perform clock data recovery on reception data in response to the reception clock signal to output recovery data. A deserializer is configured to convert the recovery data into parallel data; and a loop-back line configured to supply the serial data outputted from the serializer to the CDR circuit as the reception data.08-18-2011
20110169538WIDEBAND DELAY-LOCKED LOOP (DLL) CIRCUIT - A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal.07-14-2011
20080211555Delay locked loop in semiconductor memory device - A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively comparing a phase of a delayed feedback signal and a phase of the feedback signal with a phase of the external clock signal; a clock selecting block for selecting one of the first and second internal clock signals based on one comparison result to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on the other comparison result; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal.09-04-2008
20080211553Delay locked loop in semiconductor memory device and method for generating divided clock therein - Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.09-04-2008
20090115475Semiconductor device and operating method thereof - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.05-07-2009
20090273380DELAY LOCKED LOOP CIRCUIT AND METHOD THEREOF - A delayed locked loop (DLL) circuit for reducing power consumption in updating a delay value of an external clock after locking. The DLL circuit includes a phase comparator for comparing a phase of a feedback clock and a phase of an external clock, and a delay unit for delaying an external clock in response to a comparison signal from the phase comparison. A replica unit receives the delayed external clock and outputs the feedback clock. A toggling controller disables toggling of the delayed external clock that is inputted to the replica unit for a predetermined time at a regular interval after locking.11-05-2009
20090278581DELAY LOCK LOOP AND PHASE ANGLE GENERATOR - The provided delay lock loop delaying an input signal includes a quadrature generator, a voltage controller and a delay cell. The input signal is inputted into the quadrature generator and the delay cell. A phase-changing signal from the quadrature generator and a delay signal respectively from the delay cell are inputted into the voltage controller at the same time so that a control voltage inputted into the delay cell to control a delay time of the delay signal is generated. Also, the provided phase angle generator generates an output signal in an arbitrary phase.11-12-2009
20120194240LATENCY CONTROL CIRCUIT AND METHOD OF CONTROLLING LATENCY - A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal.08-02-2012
20090289675DIFFERENTIAL TRANSMITTER AND AUTO-ADJUSTMENT METHOD OF DATA STROBE THEREOF - A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result.11-26-2009
20110169537MULTI-PHASE SIGNAL GENERATOR AND METHOD - Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals.07-14-2011
20090295441APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.12-03-2009
20090295442APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second intermediate signals having edges delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay element delaying the first intermediate signal by a first delay amount; a second delay element delaying the first intermediate signal by a second delay amount; a third delay element delaying the second intermediate signal by a third delay amount; and a fourth delay element delaying the second intermediate signal by a fourth delay amount. The third delay amount is equal to the first delay amount. The fourth delay amount is equal to the second delay amount. The apparatus also includes a delay detection loop to adjust the second and fourth delays.12-03-2009
20110204943DELAY CELL AND PHASE LOCKED LOOP USING THE SAME - A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.08-25-2011
20090002040DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.01-01-2009
20100102861DLL CIRCUIT AND CONTROL METHOD THEREOF - A DLL circuit includes a first phase comparing circuit that compares phases between an input clock signal and an output clock signal, a first delay circuit that delays the output clock signal, and a second phase comparing circuit that compares phases between the input clock signal and an output signal of the first delay circuit. A delay amount in the variable delay circuit is controlled based on a comparison result of the first phase comparing circuit and a comparison result of the second phase comparing circuit.04-29-2010
20100102862DLL CIRCUIT AND CONTROL METHOD THEREFOR - Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (04-29-2010
20100102860WIDEBAND DELAY-LOCKED LOOP (DLL) CIRCUIT - A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal.04-29-2010
20110204942CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A clock control circuit includes: a phase determination circuit that generates a phase determination signal based on a phase of an external clock signal; a counter circuit having a count value updated based on a logic level of the phase determination signal; a delay line that generates an internal clock signal by delaying the external clock signal based on the count value; and a pitch adjustment circuit that sets an update pitch of the counter circuit to be twice as high as a minimum pitch in a period in which the phase determination signal has no change, and sets the update pitch of the counter circuit to the minimum pitch in response to a change in the phase determination signal. With this configuration, it is possible to realize quick and highly accurate locking of a DLL circuit.08-25-2011
20110267118DELAY LOCKED LOOP OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines.11-03-2011
20090167388DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME - A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection.07-02-2009
20100271090Adaptive Temporal Filtering of Single Event Effects - Technologies are described herein for mitigating the effects of single event effects or upsets on digital semiconductor device data paths and clocks utilizing an adaptive temporal filter. The adaptive temporal filter includes a master delay line and a slave delay line to generate two output clock signals that remain unaffected by variations in process, voltage and temperature (PVT) conditions. The adaptive temporal filter supplies the three independent clock signals having a programmable phase relationship, to a triple voting register structure for storing and outputting an uncorrupted data value using a majority voter.10-28-2010
20080278205Programmable clock control architecture for at-speed testing - According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The N-stage programmable clock control architecture further includes means for programming the N flip-flops such that the N-stage programmable clock control architecture outputs N programmed at-speed clock pulses. For example, when N is equal to 3, three programmed clock pulses can be outputted by the N-stage programmable clock control architecture, with a total of eight different patterns of programmed clock pulses. The N-stage programmable clock control architecture can thus adequately test, for example, combinational logic requiring greater than two consecutive clock pulses for complete at-speed testing. In one embodiment, scan-shift registers can be utilized to program the N flip-flops. In another embodiment, a look-up table can be used to program the N flip-flops.11-13-2008
20080303568Clock distribution network supporting low-power mode - A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.12-11-2008
20100201416PHASE-GENERATION CIRCUITRY WITH DUTY-CYCLE CORRECTION AND METHOD FOR GENERATING A MULTIPHASE SIGNAL - Embodiments of phase-generation circuitry and methods for generating a multiphase signal with duty-cycle correction are generally described herein. The phase-generation circuitry may include a plurality of controllable delay stages arranged in series and phase detector circuitry. Each delay stage may be configured to phase shift a differential signal based on a control signal. The phase detector circuitry may be configured to generate the control signal based on a first time difference and a second time difference. The first time difference may be a time difference between rising edges of a first component of the differential signal and a second component of a phase-shifted signal. The second time difference may be a time difference between falling edges of the first component of the differential signal and the second component of the phase-shifted signal. Other circuits, systems, and methods are described.08-12-2010
20100201415METHOD AND APPARATUS FOR OUTPUT DATA SYNCHRONIZATION WITH SYSTEM CLOCK - A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to delay an external clock signal to produce a substantially in-phase output clock signal, a main loop configured to control delay through the delay line, and a secondary loop configured to adjust delay through the main loop. The clock synchronization method generally includes adjusting a delay along a delay line in response to a first phase difference between an input clock to the delay line and a shared clock signal delayed by a shared dynamic I/O model of an output driver. The method further includes adjusting the shared dynamic I/O model in response to a second phase difference between an output clock signal and the shared clock signal.08-12-2010
20100201414SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.08-12-2010
20100201413Clock control circuit and semiconductor device including the same - A clock control circuit includes a phase determination circuit that generates a first phase determination signal based on a phase of an external clock signal, a counter circuit that updates a count value based on a second phase determination signal for each sampling period, a delay line that generates an internal clock signal by delaying the external clock signal based on the count value, and an invalidation circuit that generates the second phase determination signal which is obtained by invalidating a change of the first phase determination signal within a same sampling period in response to a fact that the first phase determination circuit indicates a predetermined logical level.08-12-2010
20090039931Frequency-doubling delay locked loop - A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.02-12-2009
20110204941DELAY LOCKED LOOP SEMICONDUCTOR APPARATUS THAT MODELS A DELAY OF AN INTERNAL CLOCK PATH - A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.08-25-2011
20080238507Semiconductor memory device - A semiconductor memory device includes a phase comparator, a delay chain, a delay controller, a fine delay chain, a delay model, a locking state detector, and a fine delay controller. The phase comparator compares a phase of a reference clock with that of a feedback clock. The delay chain delays and outputs the reference clock. The delay controller controls a delay value of the delay chain in response to the comparison result of the phase comparator. The fine delay chain outputs a delay value of a clock outputted from the delay chain. The delay model delays a clock to a modeled delay value to provide a delayed clock as the feedback clock. The locking state detector generates a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock. The fine delay controller controls a fine adjustment value of the fine delay chain.10-02-2008
20080278206DLL CIRCUIT - A DLL circuit can enable a semiconductor integrated circuit to perform a stable data processing operation. The DLL circuit includes a phase splitter that controls the phase of a delay clock, thereby generating a rising clock and a falling clock, an amplifying unit that performs differential amplification on the rising clock and the falling clock in response to first and second duty control signals, thereby generating an amplified rising clock and an amplified falling clock, and a duty cycle control unit that detects the duty rates of the amplified rising clock and the amplified falling clock, thereby generating the first and second duty control signals.11-13-2008
20080211554Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays - A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.09-04-2008
20080303569Delay locked loop circuit - The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.12-11-2008
20100264968DELAY LOCKED LOOP AND METHOD OF DRIVING DELAY LOCKED LOOP - Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.10-21-2010
20100264966SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal.10-21-2010
20110006821System and Method for Signal Adjustment - Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal.01-13-2011
20120105118DELAY LOCKED LOOP AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.05-03-2012
20130214837COHERENT PHASE LOCKED LOOP - In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+08-22-2013
20130120042DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.05-16-2013
20130120043DELAY-LOCKED-LOOP CIRCUIT - A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.05-16-2013
20090160512Delay control circuit and delay control method - A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit.06-25-2009
20120139595DELAY LOCKED LOOP WITH OFFSET CORRECTION - A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.06-07-2012
20090179676LOCAL COARSE DELAY UNITS - One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a clock reference signal, a phase detector, a shift register, and a control unit. The delay line system includes a coarse delay line to adjust the delay line system time delay by remote coarse-shifting, a phase selector configured to adjust the delay line system time delay by local coarse-shifting output signals from a series of local coarse delay units, and a phase mixer to adjust a particular time delay of the clock output signal by fine-shifting. The phase mixer does not receive the clock reference signal. The phase detector detects a phase difference between the clock reference signal and the clock output signal. The shift register controls the remote coarse-shifting, and the control unit controls the local coarse-shifting, based on the phase difference.07-16-2009
20090206896DELAY LOCKED LOOP - An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output clock signal phase shifted with respect to the input clock signal by a selected value. The first phase detector is configured to provide a common control signal to each delay element based on a phase difference between the input clock signal and a signal output from one of the delay elements to adjust a delay of each delay element. The controller is configured to provide an independent control signal to each delay element to individually adjust the delay of each delay element such that the delay of each delay element is equal.08-20-2009
20110221495DIGITAL DLL INCLUDING SKEWED GATE TYPE DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF - Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.09-15-2011
20110227618INTERNAL-CLOCK ADJUSTING CIRCUIT - A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes.09-22-2011
20090096498Receiver system and method for automatic skew-tuning - A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data.04-16-2009
20090015302DELAY LOCKED LOOP AND METHOD OF CONTROLLING THE SAME - A delay locked loop includes a DLL hold control unit that receives a first control signal and outputs a DLL hold control signal, and a DLL block that receives the DLL hold control signal and generates a DLL clock.01-15-2009
20120194239DELAY LOCKED LOOP - A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.08-02-2012
20110227620SEMICONDUCTOR DEVICE HAVING DELAY LOCKED LOOP AND METHOD FOR DRIVING THE SAME - A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.09-22-2011
20090201059System and Method for Signal Adjustment - Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal.08-13-2009
20090002039POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.01-01-2009
20090102526Spread Spectrum clock generator - A delay-type phase adjusting circuit including a first variable delay circuit for receiving a reference clock signal and adding a delay to the reference clock signal, for output a phase comparator for receiving an output of the first variable delay circuit and the reference clock signal and detecting a phase difference therebetween a control circuit for generating a control signal for variably controlling a delay value of the first variable delay circuit based on a result of phase comparison by said phase comparator a second variable delay circuit for receiving an input signal and adding a delay to the input signal, for output a computation circuit for receiving a predetermined value and the control signal and variably controlling a delay value of the second variable delay circuit.04-23-2009
20090243677Clock generator and methods using closed loop duty cycle correction - Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments.10-01-2009
20090251183DELAY LOCK LOOP CIRCUIT AND SEMICONDUCTOR DEVICE - A simple circuit for preventing occurrence of a hazard and output delay for an asynchronous input signal in a clock signal. A flip-flop circuit (FF) outputs an output signal at a low level to a clocked inverter circuit (INVO) when a clock signal (PCLKB) transitions from a high level to a low level after an enabling signal (ENAT) goes to a high level. The clocked inverter circuit (INVO) is active when the clock signal (PCLKB) is at a low level, and inverts an output signal of the flip-flop circuit (FF) and outputs the output signal to a holding circuit (LATCH). The holding circuit (LATCH) holds the output signal of the clocked inverter circuit (INVO) and outputs the output signal as a signal (ENAOUT).10-08-2009
20090140783SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a delay adjusting circuit including a delay line having N stages of differential delay circuits and N stages of differential interpolators. A differential interpolator of an Mth (where M06-04-2009
20080297215METHOD AND APPARATUS FOR OUTPUT DATA SYNCHRONIZATION WITH SYSTEM CLOCK - A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to delay an external clock signal to produce a substantially in-phase output clock signal, a main loop configured to control delay through the delay line, and a secondary loop configured to adjust delay through the main loop. The clock synchronization method generally includes adjusting a delay along a delay line in response to a first phase difference between an input clock to the delay line and a shared clock signal delayed by a shared dynamic I/O model of an output driver. The method further includes adjusting the shared dynamic I/O model in response to a second phase difference between an output clock signal and the shared clock signal.12-04-2008
20090315600LOCKED-LOOP QUIESCENCE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.12-24-2009
20100171536VOLTAGE SELECTING CIRCUIT, VOLTAGE PROVIDING CIRCUIT UTILIZING THE VOLTAGE SELECTING CIRCUIT, AND SIGNAL DELAYING SYSTEM UTILIZING THE VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes: a first voltage providing circuit, for generating a first voltage; a switch device, for receiving a first voltage; a second voltage providing circuit, for providing a second voltage; a control circuit, for controlling the switch device and the second voltage providing circuit, wherein in a first mode, the control circuit turns off the switch device for allowing a target device to receive the second voltage, and in a second mode, the control circuit turns on the switch device and stops the second voltage providing circuit from providing the second voltage such that the target device can receive the first voltage; and an adjusting circuit, for providing a reference voltage to the first voltage providing circuit according to the first voltage and the second voltage for changing the first voltage, thereby making the first voltage substantially equal to the second voltage.07-08-2010
20100156486DLL CIRCUIT HAVING ACTIVATION POINTS - A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.06-24-2010
20100194456Delay locked loop, electronic device including the same, and method of operating the same - A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.08-05-2010
20100156488DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY - The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.06-24-2010
20100156485DELAY ELEMENT ARRAY FOR TIME-TO-DIGITAL CONVERTERS - Embodiments of the present disclosure provide methods, systems, and apparatuses related to a delay element array for time-to-digital converters. Some embodiments include a voltage controlled oscillator; a time-to-digital converter including a delay element array to output delayed versions of a signal and logic to generate a digital word that represents phase information of the signal based at least in part on the delayed versions; and a phase detector to generate a digital phase error based at least in part on the digital word. Other embodiments may be described and claimed.06-24-2010
20100182059SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS - A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the V07-22-2010
20090079481PERIODIC SIGNAL DELAY APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to generate a periodic output signal and to vary a power supply to the delay elements. Additional apparatus, systems, and methods are disclosed.03-26-2009
20100001772METHODS AND SYSTEMS FOR DELAY COMPENSATION IN GLOBAL PLL-BASED TIMING RECOVERY LOOPS - A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.01-07-2010
20100194457DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.08-05-2010
20100188125DIGITAL LOCKED LOOPS AND METHODS WITH CONFIGURABLE OPERATING PARAMETERS - A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.07-29-2010
20100182058DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.07-22-2010
20100164573SEMICONDUCTOR DEVICE - A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.07-01-2010
20100123495DLL circuit and semiconductor device having the same - A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.05-20-2010
20100225370Frequency-Doubling Delay Locked Loop - A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.09-09-2010
20100237917Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device - To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.09-23-2010
20100225369Devices Comprising Delay Line for Applying Variable Delay to Clock Signal - The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements. Devices according to this disclosure are, amongst other uses, suited for use in Ultra Wide Band (UWB) receiving or transmitting devices, in particular those devices, designed for low power consumption, by enabling power on and off switching of parts of such devices as analog to digital converters and integrators, during timing windows.09-09-2010
20100237918Frequency measuring circuit and semiconductor device having the same - A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal09-23-2010
20100231275SEMICONDUCTOR DEVICE HAVING CLOCK GENERATING CIRCUIT - A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.09-16-2010
20100253404CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHODS FOR GENERATING JITTER COMPENSATED CLOCK SIGNALS - Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal.10-07-2010
20100123498Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit - A phase locked loop circuit includes a delay compensation circuit and a phase change circuit. The delay compensation circuit is adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase. The phase change circuit is adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase, wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, and wherein the quotient is an integer.05-20-2010
20110057697Clock generating circuit, semiconductor device including the same, and data processing system - To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, and a clock generating unit that generates an internal clock signal based on the second phase determination signal. The sampling circuit includes a continuity determining circuit that fixes the second phase determination signal when a logic level of the first phase determination signal changes within a sampling cycle, an initial operation circuit that fixes the second phase determination signal at a high level until when a third phase determination signal indicates a high level, and a disabling circuit that disables an operation of the continuity determining circuit after the third phase determination signal indicates a high level.03-10-2011
20100253405TECHNIQUES FOR NON-OVERLAPPING CLOCK GENERATION - Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (t10-07-2010
20100085094MULTI-PHASE SIGNAL GENERATOR AND METHOD - A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.04-08-2010
20120194241SYNCHRONIZATION CIRCUIT - A synchronization circuit includes a first delay unit configured to delay an input signal by a delay time corresponding to first initial delay information and generate a pre-delayed signal; a second delay unit configured to delay the pre-delayed signal by a delay time corresponding to second initial delay information and generate a delayed signal; and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to internal delayed signals of the first delay unit and the input signal.08-02-2012
20090189657Delay locked loop circuit and method for eliminating jitter and offset therein - A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.07-30-2009
20090184741Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit - A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock target upon deviation from the lock target. There are provided with a plurality of phase comparators 07-23-2009
20090322392DIGITAL DELAY LOCKED LOOP CIRCUIT - A phase determination section determines the quantity of first fixed delay elements for delaying a clock signal by one cycle and generates a selection signal indicating the determination result. A phase adjustment section determines, based on the selection signal, the quantity of second fixed delay elements for delaying an input signal and generates the output signal by delaying the input signal by a certain phase amount. The phase adjustment section includes a variable delay unit which generates, based on the selection signal, a variable delay time allowing the delay time of the output signal to be adjusted in steps of ½12-31-2009
20090153206OPTICAL DRIVER INCLUDING A MULTIPHASE CLOCK GENERATOR HAVING A DELAY LOCKED LOOP (DLL), OPTIMIZED FOR GIGAHERTZ FREQUENCIES - An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks.06-18-2009
20110032014Delay locked loop circuit and signal delay method - A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.02-10-2011
20090289676DLL circuit - A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.11-26-2009
20090033387Master Slave Delay Locked Loops and Uses Thereof - Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states. One of the two states causes the first signal to drive the first delay stage and the second signal to drive the second delay stage, and the other state causes the reference signal to drive the first delay stage and the first stage output to drive the second delay stage. In some cases, the first state is referred to as a slave state and the second state is referred to as a master state. In addition, the circuit includes a feedback loop.02-05-2009
20080246520DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY - A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system.10-09-2008
20100295589MULTI-STAGE DIFFERENTIAL AMPLIFICATION CIRCUIT AND INPUT BUFFER FOR SEMICONDUCTOR DEVICE - A multi-stage amplification circuit includes a common differential amplification unit configured to receive and detect differential input signals to generate a positive signal and a negative signal, a positive signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a positive amplification signal, and a negative signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a negative amplification signal.11-25-2010
20100295588DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal.11-25-2010
20100301912DELAY LOCKED LOOP AND DELAY LOCKING METHOD HAVING BURST TRACKING SCHEME - A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.12-02-2010
20100134166SYSTEM AND METHOD FOR AN ACCURACY-ENHANCED DLL DURING A MEASURE INITIALIZATION MODE - A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.06-03-2010
20100134164DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock, a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock, and a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled.06-03-2010
20110001527DUTY-CYCLE ERROR CORRECTION CIRCUIT - A duty cycle error correction circuit is disclosed. The circuit includes an inversion and delay circuit and a phase interpolator. The inversion and delay circuit is configured to receive an input signal having a waveform that includes a duty cycle error, delay and invert the input signal to form an inverted delayed signal, a determine whether the input signal and the inverted delayed signal are in phase. The phase interpolator is configured to receive the input signal, receive the inverted delayed signal, interpolate the received input signal and the received inverted delayed signal, and based on the interpolation, output a duty cycle error corrected signal.01-06-2011
20110001526DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.01-06-2011
20110109359Variable Capacitance with Delay Lock Loop - An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A variable capacitance circuit is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.05-12-2011
20110109356APERTURE GENERATING CIRCUIT FOR A MULTIPLYING DELAY-LOCKED LOOP - A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.05-12-2011
20130147531DIGITAL PHASE LOCKED LOOP DEVICE AND METHOD IN WIRELESS COMMUNICATION SYSTEM - A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.06-13-2013
20090256605PHASE CONTROLLING APPARATUS, PHASE-CONTROL PRINTED BOARD, AND CONTROLLING METHOD - In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.10-15-2009
20110001528PERIODIC SIGNAL SYNCHRONIZATION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed.01-06-2011
20110018600DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.01-27-2011
20110043262Input interface circuit - An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.02-24-2011
20110043263SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.02-24-2011
20110115536ADC HAVING INPROVED SAMPLE CLOCK JITTER PERFORMACE - In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).05-19-2011
20110241742DATA OUTPUT CONTROL CIRCUIT - A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.10-06-2011
20110018599Partial Response Receiver And Related Method - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.01-27-2011
20090033384METHOD AND SYSTEM FOR MANAGING DIGITAL TO TIME CONVERSION - A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.02-05-2009
20100164574SIMPLIFIED, EXTENDABLE, EDGE-BASED WATCHDOG FOR DLL - A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.07-01-2010
20100164572SEMICONDUCTOR DEVICE - A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.07-01-2010
20100164571PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME - A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.07-01-2010
20090322390DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit and a delay locked loop circuit including the same are capable of reducing area and power consumption of a circuit. The delay locked loop circuit includes a delay locked loop unit, a delay controller, a duty cycle ratio correction circuit, and a duty cycle ratio detector. The delay locked loop unit outputs an internal clock by delaying an external clock in order to compensate a clock skew. The delay controller outputs a delay internal clock by delaying the internal clock in response to correction signals. The duty cycle ratio correction circuit outputs an internal correction clock by increasing or decreasing a high level section of the internal clock according to the correction signals. The duty cycle ratio detector outputs the correction signals in accordance with a duty cycle ratio of the internal correction clock.12-31-2009
20110074479DELAY LOCKED LOOP APPARATUS - A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.03-31-2011
20110128056DELAY-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.06-02-2011
20100219867Delay-locked loop and electronic device including the same - A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.09-02-2010
20100219868SIGNAL DELAYING SYSTEM UTILIZING VOLTAGE PROVIDING CIRCUIT - A signal delaying system is provided, including a delay locked loop circuit and a voltage providing circuit. The delay locked loop circuit delays an input signal to generate a delayed signal. The voltage providing circuit provides a control voltage to the delay locked loop circuit for determining a delay time of the delay locked loop circuit when the delay locked loop circuit operates in a first mode; and providing a stand-by voltage to the delay locked loop circuit when the delay locked loop circuit operates in a second mode, wherein the voltage providing circuit further adjusts the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.09-02-2010
20110140748SYNTHESIZABLE DLL ON SYSTEM-ON-CHIP - The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.06-16-2011
20090219069Semiconductor integrated circuit device - Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.09-03-2009
20090219068Phase detector, phase comparator, and clock synchronizing device - A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.09-03-2009
20090322391PHASE SYNCHRONIZATION APPARATUS - A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.12-31-2009
20090039930DLL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE USING THE SAME, AND DATA PROCESSING SYSTEM - A DLL circuit includes a delay line (CDL) (02-12-2009
20090033388Systems and Methods for Reduced Area Delay Locked Loop - Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.02-05-2009
20090033386Delay Lock Loop Circuits Including Glitch Reduction and Methods for Using Such - Various systems and methods for delaying one signal in relation to another are disclosed. As one example, a delay lock loop circuit is discussed that includes at least a first delay stage and a second delay stage, each including a plurality of selectable delay elements. The delay stages are configured such that a gated reference signal drives an input of the first delay stage, and a first output from the first delay stage drives an input of the second delay stage. The circuits further include a unified selector register that is associated with both the first delay stage and the second delay stage. A value maintained in the unified selector register determines a number of the selectable delay elements utilized in the first delay stage and a number of the selectable delay elements utilized in the second delay stage. In operation, modification of the value maintained in the unified selector register is synchronized to the reference signal. A reference signal gate is included that receives the reference signal and provides the gated reference signal. The gated reference signal is substantially the reference signal modified such that the gated reference signal is not asserted when modification of the unified selector register is enabled.02-05-2009
20090033385Glitch Reduced Delay Lock Loop Circuits and Methods for Using Such - Various embodiments of the present invention provide delay lock loop circuits. Such delay lock loop circuits include two or more delay stages that each include a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, and the first delay stage provides a first output. The first output drives an input of the second delay stage, and the second delay stage provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. Modification of the value maintained in the first selector register is synchronized to the first output. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the value maintained in the second selector register is synchronized to the second output.02-05-2009
20120242385SIGNAL RECEIVING CIRCUIT, MEMORY CONTROLLER, PROCESSOR, COMPUTER, AND PHASE CONTROL METHOD - A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.09-27-2012
20110248756SEMICONDUCTOR CIRCUIT - Power consumption in a DLL circuit having a DCC circuit is reduced. Specifically, a semiconductor circuit includes a change-in-duty detection circuit, activation and deactivation of which is controlled based upon a control signal (DCCEN), for comparing duty of a clock signal that has been generated based upon an input clock signal and a preset duty and outputting result of the comparison; and a duty determination circuit for outputting the control signal (DCCEN) for deactivating the change-in-duty detection circuit when the output of the change-in-duty detection circuit indicates that duty of the generated clock signal is in the vicinity of a target value, which is a preset duty, and outputting the control signal (DCCEN) for activating the change-in-duty detection circuit when the duty of the generated clock signal is not in the vicinity of the target value.10-13-2011
20110095794Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode - An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.04-28-2011
20110175654DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD - A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.07-21-2011
20100123494CONFIGURABLE ARCHITECTURE HYBRID ANALOG/DIGITAL DELAY LOCKED LOOP (DLL) AND TECHNIQUE WITH FAST OPEN LOOP DIGITAL LOCKING FOR INTEGRATED CIRCUIT DEVICES - A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.05-20-2010
20110102036PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS - A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.05-05-2011
20110102035SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DELAY LOCKED LOOP CIRCUIT - A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.05-05-2011
20120146694DEVICE AND METHOD FOR COMPENSATING A SIGNAL PROPAGATION DELAY - A device for compensating a delay τ suffered by a first periodic signal ref(t) during propagation between a first and second end of a first transmission connection, comprising at least: 06-14-2012
20110074480Method and Apparatus for the Controlled Delay of an Input Signal - An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.03-31-2011
20110074478SEMICONDUCTOR APPARATUS - A semiconductor apparatus for reducing unnecessary current consumption disclosed. The semiconductor apparatus includes: a clock signal transmission unit that selectively transmits a clock signal in accordance with the frequency of the clock signal at an operation standby mode. A delay locked loop generates a DLL clock signal on the basis of the clock signal inputted through the clock signal transmission unit. The delay locked loop generates the DLL clock signal during a period where the clock signal is transmitted.03-31-2011
20120200329SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.08-09-2012
20110043264DOUBLE DATA RATE INTERFACE - The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.02-24-2011
20110018601PHASE CONTROL DEVICE, PHASE-CONTROL PRINTED BOARD, AND CONTROL METHOD - A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.01-27-2011
20100090735DELAY CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME - A delay circuit includes a delay line unit including a plurality of delay units configured to generate a plurality of delay input clocks by delaying an input clock by a unit delay amount in response to at least one delay control signal; and a signal selection unit configured to selectively output at least one of the plurality of delay input clocks in response to the delay control signal.04-15-2010
20090256603REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT - A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator. The clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, the second delay unit providing a longer delay than the first delay unit. A delay replica model is configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock.10-15-2009
20090289677DEVICE - A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.11-26-2009
20090153205METHODS, DEVICES, AND SYSTEMS FOR A DELAY LOCKED LOOP HAVING A FREQUENCY DIVIDED FEEDBACK CLOCK - Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider operably coupled to the delayed clock signal and configured to generate a frequency divided clock signal. Furthermore, the delay locked loop may include a phase detector configured to receive the reference clock signal and the frequency divided clock signal having a frequency less than that of the reference clock signal. Additionally, the phase detector may be configured to measure a phase difference of the reference clock signal and the frequency divided clock signal upon receipt of an active edge of the frequency divided clock signal.06-18-2009
20080272812SEMICONDUCTOR MEMORY DEVICE INCLUDING DELAY-LOCKED-LOOP CONTROL CIRCUIT AND CONTROL METHOD FOR EFFECTIVE CURRENT CONSUMPTION MANAGEMENT - A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.11-06-2008
20090002041METHOD FOR IMPROVING STABILITY AND LOCK TIME FOR SYNCHRONOUS CIRCUITS - Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.01-01-2009
20080252344TIMING VERNIER USING A DELAY LOCKED LOOP - A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.10-16-2008
20080252343DLL CIRCUIT - A DLL circuit has an input circuit configured to generate a synchronization reference signal on the basis of an input signal, a first delay unit configured to delay the synchronization reference signal, a timing offset circuit configured to adjust a synchronization position of the synchronization reference signal delayed by the first delay unit to generate a signal to be synchronized, a phase comparison circuit configured to compare phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit configured to select an output signal of the first delay unit on the basis of a comparison result of the phase comparison circuit, a second delay unit configured to delay the synchronization reference signal or the signal to be synchronized and a second control circuit configured to select an output signal of the second delay unit in the case where the comparison result of the phase comparison circuit is within a predetermined range. The phase comparison circuit compares the phase of the signal, which is either the synchronization reference signal or the signal to be synchronized, delayed by the second delay unit with the phase of the other signal.10-16-2008
20080204094Semiconductor memory device and method for driving the same - The present invention intends to provide a semiconductor memory device including a delay locked loop (DLL) circuit capable of generating a duty-corrected delay locked clock. A semiconductor memory device includes: a DLL circuit for generating a delay locked clock through a delay locked operation; and a duty-correction circuit for correcting a duty ratio of the delay locked clock by using the delay locked clock and a divided clock generated by dividing the delay locked clock by an even value.08-28-2008
20080204095METHOD AND APPARATUS FOR CONTROLLING POWER-DOWN MODE OF DELAY LOCKED LOOP - A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells. Of the DLL to the output terminal of the DLL.08-28-2008
20080204093Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal - Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.08-28-2008
20100321076DELAY-LOCKED LOOP FOR CORRECTING DUTY RATIO OF INPUT CLOCK SIGNAL AND OUTPUT CLOCK SIGNAL AND ELECTRONIC DEVICE INCLUDING THE SAME - A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.12-23-2010
20110163787DIGITAL PHASE LOCKING LOOP AND METHOD FOR ELIMINATING GLITCHES - The present disclosure discloses a digital phase locking loop and a method. The digital phase locking loop includes a trigger and a delay line. The trigger receives a delayed clock signal output by the delay line, and receives a signal of a selection end of a first delay element in the delay line; the selection end is in a gating state before triggering of the trigger. The trigger samples the signal of the selection end of the first delay element, and outputs the sampled signal to a selection end of a second delay element in the delay line; the selection end of the second delay element is in the gating state after triggering of the trigger. The signal of the selection end of the first delay element is sampled by the trigger, and the sampled result is used as the signal of the selection end of the second delay element, thus reducing glitches caused by transition.07-07-2011
20110001525DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes: a voltage level detector for detecting of an external power source voltage level; a phase comparator for comparing phases of reference clock and feedback clock; a clock delayer for designating one of a first delay cell unit and a second delay cell unit as initial delay cell unit and the other as connected delay cell unit, delaying the reference clock by the initial delay cell unit until delay amount of the reference clock reaches a predetermined delay amount, delaying the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparator, and outputting a delay locked clock; and a delay duplication modeler for changing the delay locked clock to reflect an actual delay condition of the reference clock and outputting the feedback clock.01-06-2011
20110187427LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.08-04-2011
20110128057Delay Locked Loop and Associated Method - A delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator generates a pulse signal and a determination signal according to an input clock signal. The delay unit delays the pulse signal according to a digital control signal to generate a delayed pulse signal. The phase detector detects a time delay of the delayed pulse signal according to the determination signal to generate a detection result. The control unit generates a digital control signal according to the detection result to control the delayed pulse signal by a delay amount.06-02-2011
20110254604Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage - Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.10-20-2011
20110169539DELAY LOCKED LOOP CIRCUIT AND OPERATION METHOD THEREOF - A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.07-14-2011
20100117695SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.05-13-2010
20100117696DLL CIRCUIT, UPDATE CONTROL APPARATUS IN DLL CIRCUIT AND UPDATE METHOD OF DLL CIRCUIT - A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.05-13-2010
20100117698TIMING VERNIER USING A DELAY LOCKED LOOP - A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.05-13-2010
20110095796PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME - A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.04-28-2011
20110095795SEMICONDUCTOR MEMORY DEVICE HAVING DELAY LOCK LOOP WITH WIDE FREQUENCY RANGE AND DELAY CELL CURRENT REDUCTION SCHEME - A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on.04-28-2011
20110109357DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a delay circuit and a phase adjusting circuit. The phase adjusting circuit is configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number. The delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection. A semiconductor device, semiconductor system, and method are also disclosed.05-12-2011
20110175655DIGITAL LOCKED LOOPS AND METHODS WITH CONFIGURABLE OPERATING PARAMETERS - A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.07-21-2011
20100213995DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME - A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection.08-26-2010
20100213994Charge Pump for PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.08-26-2010
20100060334DLL CIRCUIT AND CONTROL METHOD THEREFOR - A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.03-11-2010
20110148487DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.06-23-2011
20110148486CONTROLLED CLOCK GENERATION - Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.06-23-2011
20100026352ALL DIGITAL FREQUENCY-LOCKED LOOP CIRCUIT METHOD FOR CLOCK GENERATION IN MULTICORE MICROPROCESSOR SYSTEMS - A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.02-04-2010
20100019813INTERNAL CLOCK DRIVER CIRCUIT - An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.01-28-2010
20090174447SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.07-09-2009
20100277212DELAY LOCKED LOOP - A delay locked loop comprises a delay line having a plurality of sequentially connected delay elements (E11-04-2010
20110074477Techniques for Providing Reduced Duty Cycle Distortion - A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.03-31-2011
20120146693APPARATUS FOR CLOCK SKEW COMPENSATION - An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.06-14-2012
20120146695Temperature Compensation Via Power Supply Modification to Produce a Temperature-Independent Delay in an Integrated Circuit - A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. Such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature.06-14-2012
20120306553TIME DIFFERENCE ADDERS, TIME DIFFERENCE ACCUMULATORS, SIGMA-DELTA TIME-TO-DIGITAL CONVERTERS, DIGITAL PHASE LOCKED LOOPS AND TEMPERATURE SENSORS - A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.12-06-2012
20120306552APPARATUS AND SYSTEM OF IMPLEMENTATION OF DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY - An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.12-06-2012
20100194458SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.08-05-2010
20100060335Seamless Coarse and Fine Delay Structure for High Performance DLL - A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.03-11-2010
20110050305CENTRALIZING THE LOCK POINT OF A SYNCHRONOUS CIRCUIT - A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.03-03-2011
20110050304SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 03-03-2011
20110050303DIE LOCATION COMPENSATION - Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.03-03-2011
20100097111Semiconductor device including delay locked loop having periodically activated replica path - A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.04-22-2010
20120105120Digital Phase-Locked Loop Architecture - A phase-locked loop circuit comprising: an oscillator (05-03-2012
20110316598APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME - A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.12-29-2011
20110316599MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.12-29-2011
20090146704DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.06-11-2009
20120044002SEMICONDUCTOR APPARATUS AND DLL CIRCUIT USING THE SAME - A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.02-23-2012
20110156780APPARATUS FOR DETECTING JITTER OF PHASE LOCKED LOOP - A method and apparatus for detecting jitter of a Phase Locked Loop (PLL), which is capable of detecting a jitter level of the PLL without using a separate jitter measurement device, is disclosed. The apparatus for detecting the jitter of the PLL includes the PLL configured to detect a phase difference signal between a reference clock and a feedback clock and to generate an oscillation signal having a predetermined frequency according to the phase difference signal, a variable phase delay unit configured to switch a plurality of capacitors according to an input delay control signal and to delay the phase difference signal from the PLL according to the delay control signal, a comparator configured to compare the phase difference signal from the PLL with the phase difference signal delayed by the variable phase delay unit and to detect a delay period of the phase difference signal, and a lock detection unit configured to detect whether the oscillation signal is within a lock range after the delay period detected by the comparator.06-30-2011
20110156779PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.06-30-2011
20110156778INTERNAL CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF - An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.06-30-2011
20120007646DLL CIRCUIT HAVING ACTIVATION POINTS - A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.01-12-2012
20100156487DLL CIRCUIT - A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.06-24-2010
20120206178STATE MACHINE FOR DESKEW DELAY LOCKED LOOP - A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.08-16-2012
20120154001SHIFT REGISTER AND SYNCHRONIZATION CIRCUIT USING THE SAME - A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.06-21-2012
20090134924DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.05-28-2009
20120025883LOCK DETECTION CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT INCLUDING THE SAME - A phase-locked loop circuit including a lock detector is provided comprising a delay circuit including a load capacitor, and a bias circuit configured to generate a constant reference current, wherein the load capacitor is charged or discharged with a current whose level is dependent upon the reference current.02-02-2012
20120062295CONTROL VOLTAGE TRACKING CIRCUITS, METHODS FOR RECORDING A CONTROL VOLTAGE FOR A CLOCK SYNCHRONIZATION CIRCUIT AND METHODS FOR SETTING A VOLTAGE CONTROLLED DELAY - Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.03-15-2012
20120062294CLOCK DELAY CIRCUIT AND DELAY LOCKED LOOP INCLUDING THE SAME - A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.03-15-2012
20120154002DELAY LOCKED LOOP - A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.06-21-2012
20090309638 Variable-Length Digitally-Controlled Delay Chain with Interpolation-Based Tuning - A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Optionally, the programmable delay element utilizes current-mode logic (CML) and the control signal is a thermometer coded digital signal. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.12-17-2009
20120119804MULTI-PHASE DUTY-CYCLE CORRECTED CLOCK SIGNAL GENERATOR AND MEMORY HAVING SAME - Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.05-17-2012
20120119803DLL HAVING A DIFFERENT TRAINING INTERVAL DURING A VOLTAGE CHANGE - A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.05-17-2012
20120119802DELAY LOCKED LOOP WITH DELAY PROGRAMMABILITY - A delay locked loop (DLL) with delay programmability includes a pair of delay blocks, each containing multiple delay elements, but configurable to connect a desired subset of the delay elements between input and output nodes of the respective delay blocks. The subsets of the delay elements in the two delay blocks are connected in series. The ratio of the number of delay elements programmed to form each of the two subsets determines a delay provided as an output by the DLL. In operation, a phase discriminator and a loop filter in combination with the programmed subsets in the delay blocks, operate to generate an analog error signal to compensate for process, temperature and voltage (PTV) variations in the delay provided as an output by the DLL.05-17-2012
20100289543Method and Apparatus for Improving Accuracy of Signals Delay - A delay module, a delay method, a clock detection apparatus, and a digital locked loop (DLL) are disclosed. The delay module includes a first delay unit, a second delay unit and an inverter. Each of the first delay unit and the second delay unit include two logic gates adapted to invert a phase: a logic gate for gating and a logic gate for delaying. These two logic gates are electrically connected. The input port of the logic gate for gating of the first delay unit is electrically connected to the output port of the inverter; the output port of the logic gate for delaying of the first delay unit is electrically connected to the input port of the logic gate for delaying of the second delay unit; the input port of the inverter is electrically connected to the input port of the logic gate for gating of the second delay unit; the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal. With the present invention, a more accurate delay step value may be achieved.11-18-2010
20100289542SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.11-18-2010
20100289541DIGITAL PHASE-LOCKED LOOP CIRCUIT INCLUDING A PHASE DELAY QUANTIZER AND METHOD OF USE - A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.11-18-2010
20100244916SELF-TIMED FINE TUNING CONTROL - A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.09-30-2010
20100244915Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same - In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.09-30-2010
20120126868Mechanism for an Efficient DLL Training Protocol During a Frequency Change - An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.05-24-2012
20120212268PHASE CONTROL CIRCUIT - A phase control circuit includes a first duty cycle correction circuit configured to correct a duty cycle of a clock signal; a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit; and a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop, wherein the first duty cycle correction circuit and the second duty cycle correction circuit are selectively activated depending upon an operating condition.08-23-2012
20110181328FREQUENCY ADJUSTING APPARATUS AND DLL CIRCUIT INCLUDING THE SAME - A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.07-28-2011
20120161837NON-OVERLAPPING CLOCK GENERATION - Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (t06-28-2012
20120235720APPARATUS, SYSTEM, AND METHOD FOR TIMING RECOVERY - Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.09-20-2012
20100052751DLL CIRCUIT AND CONTROL METHOD THEREFOR - A DLL (delay locked loop) circuit includes a first variable delay circuit, a pair of second variable delay circuits and a first synthesis circuit. The first variable delay circuit outputs signals of different delayed time values from each of first and second clock transitions. The pair of second variable delay circuits receive the signals from the first variable delay circuit, and the first synthesis circuit synthesizes output signals of the pair of second variable delay circuits to output the resulting synthesized signal. Each of the pair of second variable delay circuits includes a pair one-shot pulse generating circuits that generate one-shot pulses from the signals from the first variable delay circuit, a pair latch circuits, and a second synthesis circuit. The second synthesis circuit receives the set outputs of the latch circuits to output a signal which is a synthesis at a preset synthesis ratio.03-04-2010
20100052750DLL CIRCUIT - A DLL circuit includes an input circuit generating a synchronization reference signal, a first delay unit delaying the synchronization reference signal to generate a plurality of delayed synchronization reference signals and selecting one of the delayed synchronization reference signals, a timing offset circuit adjusting a synchronization position of the delayed synchronization reference signal to generate a signal to be synchronized, a phase comparison circuit comparing phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit selecting an output signal of the first delay unit, a second delay unit delaying the synchronization reference signal or the signal to be synchronized to generate a plurality of delayed signals, a configuration information memory storing configuration information, and a second control circuit selecting an output signal of the second delay unit if the comparison result of the phase comparison circuit is within a predetermined range.03-04-2010
20100052749CLOCK GENERATION CIRCUIT - A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation,03-04-2010
20100052748DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.03-04-2010
20100277213VARIABLE DELAY CIRCUIT, VARIABLE DELAY DEVICE, AND VCO CIRCUIT - Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.11-04-2010
20100007391METHOD FOR USING DIGITAL PLL IN A VOLTAGE REGULATOR - A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.01-14-2010
20120256667DELAY LOCKED LOOP SEMICONDUCTOR APPARATUS THAT MODELS A DELAY OF AN INTERNAL CLOCK PATH - A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.10-11-2012
20120187992CLOCK DELAY CIRCUIT - Various embodiments of a clock delay circuit may include a variable delay unit and a delay control unit. The variable delay unit may include a plurality of first unitary delay units and a plurality of second unitary delay units. The variable delay unit is configured to generate an output clock by delaying an input clock through the first unitary delay units or the first and second unitary delay units, according to the activation/deactivation of a pre-locking signal. The delay control unit is configured to detect a phase difference between the input clock and a feedback clock generated by delaying the output clock by a delay value of an internal clock path, adjust the delay values of the first and second unitary delay units according to the detected phase difference, and activate the pre-locking signal if the phase difference between the input clock and the feedback clock is within a predetermined range.07-26-2012
20090027094TRIMMABLE DELAY LOCKED LOOP CIRCUITRY WITH IMPROVED INITIALIZATION CHARACTERISTICS - Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.01-29-2009
20090027093SAMPLING CIRCUIT AND METHOD - A sampling circuit for sampling an input data to obtain an output data includes a delay control unit, a first sampling unit, a second sampling unit, and a processing unit. The delay control unit delays a sampling signal for a first delay time to generate a first delayed signal, and delays the sampling signal for a second delay time to generate a second delayed signal; the first sampling unit samples the input data to obtain a first sampled value according to the first delayed signal, wherein the first sampling unit is utilized to generate the output data; the second sampling unit samples the input data to obtain a second sampled value according to the second delayed signal; and the processing unit controls the delay control unit to adjust at least the first delay time according to the first and second sampled values to calibrate the first delayed signal.01-29-2009
20100171537DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a first feedback loop configured to delay a reference clock signal with a delay line, wherein the first feedback loop is further configured to generate a correction clock signal by correcting a duty cycle of the reference clock signal by adjusting a delay of the delay line; and a second feedback loop configured to generate an output clock signal by detecting a phase of the reference clock signal and delaying the correction clock signal with a delay according to the detection result.07-08-2010
20100327926DLL circuit and semiconductor device having the DLL circuit - To include a phase-difference-amount detecting circuit that detects an amount of phase difference between an external clock signal and a replica clock signal, a variable delay circuit that delays the external clock signal based on the amount of phase difference to generate an internal clock signal, and a replica buffer that delays the internal clock signal to generate the replica clock signal. According to the present invention, the variable delay circuit is controlled based on the amount of phase difference, instead of being controlled based on whether the phase of the replica clock signal is advanced or delayed with respect to the external clock signal. Accordingly, even when the amount of phase difference is large, a DLL circuit can be locked at a high speed.12-30-2010
20100327925CALIBRATING MULTIPLYING-DELAY-LOCKED-LOOPS (MDLLS) - Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.12-30-2010
20080297216TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE - An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.12-04-2008
20120319749DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT - One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.12-20-2012
20120319748DIGITAL PHASE LOCKED LOOP SYSTEM AND METHOD - A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter.12-20-2012
20110037504DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.02-17-2011
20120268181SEMICONDUCTOR DEVICE - A semiconductor device includes a DLL circuit, which comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing the first clock signal and a signal generated by further delaying the second clock signal; a counter circuit outputting a count value that determines a delay amount of the delay unit to the delay unit, and up/down operating in response to the result of the phase comparison by the phase comparator circuit; and an initial delay amount control circuit detecting a cycle of the first clock signal at the time of initial setting operation, and outputting an initial value of the count value depending upon the detected cycle to the counter circuit.10-25-2012
20110215850METHOD FOR TRACKING DELAY LOCKED LOOP CLOCK - A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.09-08-2011
20120274375FREQUENCY CONTROL CLOCK TUNING CIRCUITRY - Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.11-01-2012
20120274376DUTY CYCLE CORRECTOR CIRCUITS - Duty cycle corrector circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.11-01-2012
20120081161SYNCHRONIZATION CIRCUIT - A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.04-05-2012
20120081160DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.04-05-2012
20110254602LOCKSTEP SYNCHRONIZATION AND MAINTENANCE - A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.10-20-2011
20120092052TIME-TO-DIGITAL CONVERTER - A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.04-19-2012
201200920511 TO 2N-1 FRACTIONAL DIVIDER CIRCUIT WITH FINE FRACTIONAL RESOLUTION - A fractional divider has been provided that allows for division ratios of 1:1 to 1:204-19-2012
20120139596CIRCUITRY FOR CLOCK AND METHOD FOR PROVIDING CLOCK SIGNAL - The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.06-07-2012
20130009684SEMICONDUCTOR APPARATUS AND SYSTEM - A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.01-10-2013
20130009683SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT AND CONTROL METHOD THEREOF - Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.01-10-2013
20130015898FREQUENCY-DOUBLING DELAY LOCKED LOOP - A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.01-17-2013
20130015897DUTY RATIO CORRECTION CIRCUITAANM KIM; Young-wookAACI Gunpo-siAACO KRAAGP KIM; Young-wook Gunpo-si KRAANM JANG; Soon-bokAACI SeoulAACO KRAAGP JANG; Soon-bok Seoul KRAANM SONG; Jong-ukAACI SeoulAACO KRAAGP SONG; Jong-uk Seoul KRAANM OH; Hwa-seokAACI Yongin-siAACO KRAAGP OH; Hwa-seok Yongin-si KRAANM KIM; Sung-haAACI SeoulAACO KRAAGP KIM; Sung-ha Seoul KR - A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.01-17-2013
20080238506SEMICONDUCTOR MEMORY DEVICE USING MODULATION CLOCK SIGNAL AND METHOD FOR OPERATING THE SAME - A semiconductor memory device is capable of performing a modulation of output clock signals in order to prevent EMI characteristics of a system having the semiconductor memory device from being degraded. The semiconductor memory device includes a modulation clock signal generator, a clock input unit, a first modulation unit, a delay locked loop circuit, and a second modulation unit. The modulation clock signal generator generates a modulation clock signal. The clock input unit generates a reference clock signal from a system clock signal. The first modulation unit generates a modulated clock signal by modulating the reference clock signal with the modulation clock signal. The delay locked loop circuit performs a delay locking operation on the modulated clock signal to generate a delay locked clock signal. The second modulation unit modulates the delayed locked clock signal with the modulation clock signal.10-02-2008
20090072871VARIABLE DELAY CIRCUIT, DELAY TIME CONTROL METHOD AND UNIT CIRCUIT - Variable delay circuit constructed by connecting plural unit circuits in series which can change a delay time from input of signal until output of the signal by increasing or decreasing the number of unit circuits through which the signal concerned is passed. Each of the unit circuits is operable in a through operation mode in which a signal input from a unit circuit at the front stage is output to a unit circuit at the rear stage and also a signal input from a unit circuit at the rear stage is output to a unit circuit at the front stage and a feedback operation mode in which a signal input from a unit circuit at the front stage to a unit circuit at the front stage and a signal input from a unit circuit at the rear stage is output to a unit circuit at the rear stage.03-19-2009
20080224747VARIABLE DELAY CIRCUIT, VARIABLE DELAY DEVICE, AND VCO CIRCUIT - Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.09-18-2008
20110273209One-shot circuit capable of being integrated into a chip, transmitter capable of reducing start-up time, and related method - A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.11-10-2011
20120249199INTERNAL CLOCK GENERATOR AND OPERATING METHOD THEREOF - An internal clock signal generation circuit includes a variable delay line unit including an initial variable delayer having an initial delay amount controlled based on condition information and configured to delay an input clock signal by a time corresponding to a delay control signal to output a delay locked loop (DLL) clock signal, a delay replica modeling unit configured to delay the DLL clock signal by a time obtained by modeling a clock delay component and output a feedback clock signal, and a phase comparison unit configured to compare a phase of the input clock signal with a phase of the feedback clock signal and generate the delay control signal.10-04-2012
20130099838SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.04-25-2013
20130113536FRACTIONAL-N PHASE LOCKED LOOP BASED ON BANG-BANG DETECTOR - The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.05-09-2013
20130127506SYSTEM AND METHOD FOR AN ACCURACY-ENHANCED DLL DURING A MEASURE INITIALIZATION MODE - A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.05-23-2013
20100277211DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER - A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.11-04-2010
20110210773DATA OUTPUT CIRCUIT AND DATA OUTPUT METHOD THEREOF - A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.09-01-2011
20080197899Trimmable Delay Locked Loop Circuitry with Improved Initialization Characteristics - Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.08-21-2008
20110221496DLL CIRCUIT - A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.09-15-2011
20110227619Clock generation circuit, semiconductor device including the same, and method of generating clock signal - To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount of delay of the delay line; a counter control circuit that adjusts a count value of the counter circuit; and a subtraction circuit that determines a difference between first and second count values at which the rise edge of the first internal clock signal coincides with that of a replica clock signal. The fall edge of the second internal clock signal is adjusted based on a value equivalent to one-half of the difference obtained. This prevents the applicable frequency range from being limited as with a type of duty adjustment circuit that alternately discharges capacitors.09-22-2011
20100283520DELAY LOCKED LOOP - A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.11-11-2010
20100283519CLOCK SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.11-11-2010
20100283518DELAY APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal.11-11-2010
20090102527Semiconductor device including DLL circuit, and data processing system - A DLL circuit includes: a phase determining circuit that compares phases of respective rising edges of CK and LCLK to generate a determining signal R-U/D; a phase determining circuit that compares phases of respective falling edges of CK and LCLK to generate a determining signal F-U/D; a first adjusting circuit that adjusts a position of an active edge of LCLKR based on the determining signal R-U/D; a second adjusting circuit that adjusts a position of an active edge of LCLKF based on the determining signal F-U/D; a clock generating circuit that generates LCLK based on LCLKR and LCLKF; and a stop circuit that stops an adjusting operation by the second adjusting circuit in response to an adjusting direction of the active edge of LCLKR being opposite to each other to an adjusting direction of the active edge of LCLKF.04-23-2009
20120256666DELAY LOCK LOOP SYSTEM WITH A SELF-TRACKING FUNCTION AND METHOD THEREOF - A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.10-11-2012
20120274374FAST MEASUREMENT INITIALIZATION FOR MEMORY - Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact.11-01-2012
20120274373SEMICONDUCTOR DEVICE AND DELAY LOCKED LOOP CIRCUIT THEREOF - A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.11-01-2012
20110234281DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch and drive a phase comparison signal in response to the input of a delay enable signal, and output the driven signal as a phase conversion control signal. A phase converting unit configured to control the phase of a delay clock on the basis of the phase conversion control signal, and transmit the controlled delay clock to a delay compensating unit.09-29-2011
20110234280CLOCK SIGNAL DELAY CIRCUIT FOR A LOCKED LOOP CIRCUIT - A clock signal delay circuit includes a variable delay unit, a delay unit, a phase detection block, a control clock output block, and a delay control unit. The variable delay unit controls a delay amount of a reference clock signal based on a delay control signal and provides a delayed clock signal based thereon. The delay unit delays the delayed clock signal and provides a feedback clock signal based thereon. The phase detection block detects a phase difference between the feedback clock signal and the reference clock signal and provides a detected phase difference based thereon. The control clock output block provides a control clock signal based on the detected phase difference. The delay control unit generates the delay control signal based on the detected phase difference and in response to the control clock signal.09-29-2011
20110234279VARIABLE UNIT DELAY CIRCUIT AND CLOCK GENERATION CIRCUIT FOR SEMICONDUCTOR APPARATUS USING THE SAME - A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.09-29-2011
20110234278SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes an internal source clock generation unit configured to output first and second internal source clocks, a clock phase correction unit configured to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks, a clock delay unit configured to delay the first and second phase-corrected internal source clocks and to generate first and second delay locked loop (DLL) clocks, and a clock output unit configured to mix phases of the first and second DLL clocks to output a DLL clock, and to output a feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.09-29-2011
20110234277APPARATUS AND METHOD TO COMPENSATE FOR INJECTION LOCKING - A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.09-29-2011
20100315139SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.12-16-2010
20110254603PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR - Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.10-20-2011
20130154702DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.06-20-2013
20120007645DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.01-12-2012
20120019296Circuit With a Time to Digital Converter and Phase Measuring Method - Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit (01-26-2012
20130194013APPARATUSES AND METHODS FOR ALTERING A FORWARD PATH DELAY OF A SIGNAL PATH - Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.08-01-2013
20130200933FRACTIONAL SPUR REDUCTION USING CONTROLLED CLOCK JITTER - In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.08-08-2013
20130099839SEGMENTED FRACTIONAL-N PLL - A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.04-25-2013
20120068747METHOD AND APPARATUS FOR IMPROVING ACCURACY OF SIGNALS DELAY - A delay module, includes a first delay unit, a second delay unit and an inverter. Each of the first and second delay units includes: a logic gate for gating and a logic gate for delaying. The input port of the logic gate for gating of the first delay unit is electrically connected to the output port of the inverter; the output port of the logic gate for delaying of the first delay unit is electrically connected to the input port of the logic gate for delaying of the second delay unit; the input port of the inverter is electrically connected to the input port of the logic gate for gating of the second delay unit; the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal.03-22-2012
20120086487SEMICONDUCTOR DEVICE - A semiconductor device includes a monitoring circuit including a delay circuit including a plurality of elements and a plurality of interconnects arranged in a tree shape, a data supply circuit configured to supply a determination signal to the delay circuit, and a delay evaluation circuit connected to an end point of the delay circuit and configured to evaluate a delay state of the determination signal. The monitoring circuit controls at least one of a power supply voltage, a substrate voltage, and a clock frequency of a semiconductor circuit included in the semiconductor device based on an output of the delay evaluation circuit. The circuits included in the monitoring circuit are arranged in a space in the semiconductor device using a layout tool, whereby highly accurate delay monitoring can be performed while reducing an increase in area.04-12-2012
20120086486PHASE INTERPOLATOR AND DELAY LOCKED-LOOP CIRCUIT - A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.04-12-2012
20120086485Modular Programmable Delay Line Blocks for Use in a Delay Locked Loop - Modular delay line blocks include a plurality of delay elements, each including a delay unit, an input, an output, a next element output, and an element return path. The delay elements are coupled together in a chain between a block input and a block output. The block input is coupled to the input of a first element in the chain and the block output is coupled to the output of the first element. In addition, the next element output of the first element is coupled to the element input of a next element in the chain, and the element output of the next delay element is coupled to the element return path of a previous element in the chain. In response to a selection control signal, each element may selectively route a signal from the element input to one of the next element output or to the element output.04-12-2012
20120086484Delay Locked Loop Including a Mechanism for Reducing Lock Time - A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.04-12-2012

Patent applications in class With variable delay means