Entries |
Document | Title | Date |
20080197896 | Device and Method for Phase Synchronization with the Aid of a Microcontroller - The phase controller device according to the invention comprises a hardware core that is formed by a signal detector, a voltage-controlled oscillator, a phase comparator, and an integration unit, where the hardware core, by controlling the working clock pulse frequency of the microcontroller, brings an output clock pulse signal that is generated by a microcontroller into phase with the input clock pulse information that is received from the input data stream, and does so in such a manner that the jitter is low. The microcontroller executes a program with this working clock pulse, where with that program the microcontroller generates the output clock pulse signal with an output clock pulse frequency that is in a predetermined division ratio to the control clock pulse frequency that is generated by the voltage-controlled oscillator and is given to the microcontroller as a working clock pulse frequency. In this way the program enables the phase controller device according to the invention to process, with a microcontroller, external periodic signals, data, or events, where the software processes taking place in the microcontroller are always locked in phase with the periodic occurrence of these external signals, data, or events. | 08-21-2008 |
20080204092 | Cicuit Arrangement, in Particular Phase-Locked Loop, as Well as Corresponding Method - In order to further develop a circuit arrangement ( | 08-28-2008 |
20080218227 | SEMICONDUCTOR MEMORY APPARATUS - In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit. | 09-11-2008 |
20080224744 | CONTROL DEVICE, CONTROL CIRCUIT, CONTROL METHOD, AND RECORDING MEDIUM WITH A CONTROL PROGRAM RECORDED THEREIN - The present invention provides a control device capable of performing feedback control so that a signal-wavelength input to a control target object becomes a specific signal-wavelength, using an input signal whose duty value is other than 50%. Accordingly, the control device according to the present invention is a control device for performing feedback control so that a signal-wavelength input to a control target object ( | 09-18-2008 |
20080238503 | Injection locked LC VCO clock deskewing - In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock. | 10-02-2008 |
20080238504 | Phase locked loop - A phase locked loop includes a first clock divider configured to divide a first input clock to generate a second input clock; a clock selector configured to selectively output one of the first input clock and the second input clock in response to a test signal; a phase/frequency detector configured to detect phase and frequency differences between the selected output clock of the clock selector and a feedback clock to generate a detection signal corresponding to the detected phase and frequency differences; a control voltage generator configured to generate a control voltage having a voltage level corresponding to the detection signal; a voltage controlled oscillator configured to generate an internal clock having a frequency corresponding to the control voltage; and a second clock divider configured to divide the internal clock to generate the feedback clock. | 10-02-2008 |
20080252340 | DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME - Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal. | 10-16-2008 |
20080265957 | Self-Resetting Phase Frequency Detector with Multiple Ranges of Clock Difference - A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs. | 10-30-2008 |
20080265958 | Method for Noise Reduction in a Phase Locked Loop and a Device Having Noise Reduction Capabilities - A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period. | 10-30-2008 |
20080265959 | PLL circuit and frequency setting circuit employing the same - Disclosed is a PLL circuit in which an output signal of a frequency oscillator (VCO or ICO), an oscillation frequency of which is controlled by an electrical signal, is supplied via a high pass filter (HPF) to one of input terminals of a phase detector, the other input terminal of which receives a reference frequency. An output signal of the phase detector is supplied to a loop filter which then outputs a DC component of the signal that controls the frequency oscillator as the electrical signal. | 10-30-2008 |
20080272810 | FILTERLESS DIGITAL FREQUENCY LOCKED LOOP - A frequency and/or phase locked loop architecture that eliminates the loop filter generally required in conventional phase locked loops, and which may be implemented in digital logic, for example, as a field programmable gate array. In one example, a frequency/phase locked loop includes both a frequency comparison component and a phase comparison component to allow locking of an output clock signal to both the frequency and phase of a reference signal. | 11-06-2008 |
20080284476 | Techniques for integrated circuit clock management using pulse skipping - A processor ( | 11-20-2008 |
20080297213 | Signaling with Superimposed Clock and Data Signals - A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal. | 12-04-2008 |
20090009221 | METHOD AND APPARATUS FOR SYNCHRONIZING A CLOCK GENERATOR IN THE PRESENCE OF JITTERY CLOCK SOURCES - There are provided, in a clock generator for generating a plurality of output clock signals, an apparatus and method for synchronizing the clock generator to an input reference clock in the presence of a jittery input clock provided to the clock generator from a PLL. The clock generator and the PLL each have a divider with the same ratio. The apparatus includes a synchronizer ( | 01-08-2009 |
20090009222 | CLOCK GENERATION CIRCUIT, RECORDING DEVICE AND CLOCK GENERATION METHOD - A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generates the output clock signal, and a correction circuit that changes the multiplication factor of the PLL circuit. The correction circuit changes the PLL circuit multiplication factor by increasing or decreasing the specific multiplication factor, the change being performed only during a correction interval for each correction cycle, the correction cycle being longer than one cycle of the input signal, and being performed such that a time difference between an input synchronizing signal synchronized with the input signal and an output synchronizing signal synchronized with the output clock signal is reduced. The PLL circuit multiplies the input signal by the changed multiplication factor during the correction interval. | 01-08-2009 |
20090033380 | REDUNDANT CLOCK SWITCH CIRCUIT - A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal. | 02-05-2009 |
20090033381 | PHASE LOCKED LOOP, VOLTAGE CONTROLLED OSCILLATOR, AND PHASE-FREQUENCY DETECTOR - A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. | 02-05-2009 |
20090033382 | Frequency synthesizer - A circuit for receiving an input signal and generating an output signal, the input signal having a first frequency, the output signal having a second frequency. The circuit comprises a forward branch for generating the output signal and a return branch for feeding back the output signal. The return branch comprises a frequency divider for receiving the output signal, for dividing the frequency of the output signal by a factor, and for outputting a modified output signal. The forward branch comprises a detector for comparing the input signal and the modified output signal and outputting a comparison signal indicative of the comparison; a word-length reduction circuit for reducing the number of bits of the comparison signal, thereby generating a reduced-length comparison signal; a digital-to-analog converter for converting the reduced-length comparison signal to analog, thereby generating an analog signal; and an oscillator, controlled by said analog signal. By reducing the word length of the input to the digital-to-analog converter, the digital-to-analog converter may be greatly simplified. | 02-05-2009 |
20090039927 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 02-12-2009 |
20090039928 | LOW POWER AND LOW TIMING JITTER PHASE-LOCK LOOP AND METHOD - A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLK | 02-12-2009 |
20090045855 | APPARATUS FOR INTERFACING AND TESTING A PHASE LOCKED LOOP IN A FIELD PROGRAMMABLE GATE ARRAY - An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster. | 02-19-2009 |
20090058479 | TIMING CONTROLLERS AND DRIVING STRENGTH CONTROL METHODS - A timing controller receiving image data using an input clock signal and transferring the received image data and an output clock signal to a source driver. The received image data is transferred to the source driver through an output buffer. A frequency detection circuit detects a frequency of the input clock signal. A power supply circuit provides power to the output buffer, wherein power level is determined by the detected frequency. | 03-05-2009 |
20090079478 | LOCKED PHASE ACTIVE POWER CURRENT CONTROL CIRCUIT - The locked phase active power current control circuit is composed of a DC source, an electronic switch, a driving transformer, a phase detecting unit, a current intercepting unit and a square wave controller. A DC signal provided by the DC source is converted into a square wave signal by the electronic switch for the driving transformer to operate a load. The electronic switch outputs the square wave signal to the phase detecting unit whereat a phase signal of the square wave is detected and the detected signal is transmitted to the current intercepting unit whereat the detected signal is compared with the current intercepted at the electronic switch, the driving transformer, or the load, and the comparison result is fed back to the square wave controller so as to set the operation frequency of the electronic switch. The essential principle of the present invention is based on the fact that the square wave is in phase with the first harmonic wave. | 03-26-2009 |
20090079479 | ADJUSTABLE DIGITAL LOCK DETECTOR - An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal. | 03-26-2009 |
20090079480 | OSCILLATING APPARATUS - An oscillating apparatus is provided that includes: an integration circuit that outputs a control signal based on an integration value of two inputted voltage values; an oscillator that outputs an oscillation signal of a frequency that is based on the control signal; a phase comparator that outputs a phase difference signal of a pulse width that is in accordance with a phase difference between the oscillation signal and the reference signal, by comparing the oscillation signal with a reference signal of a predetermined frequency; a controlling circuits that controls the two inputted voltage values based on the phase difference signal, so as to approximate a phase difference between the oscillation signal and the reference signal to a predetermined reference phase difference; and a voltage stabilizing current that defines the two inputted voltages based on a predetermined reference voltage. | 03-26-2009 |
20090085620 | CLOCK SYSTEM AND APPLICATIONS THEREOF - A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal. | 04-02-2009 |
20090096497 | DESIGN STRUCTURES INCLUDING MULTIPLE REFERENCE FREQUENCY FRACTIONAL-N PLL (PHASE LOCKED LOOP) - A design structure including a system. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached. | 04-16-2009 |
20090102525 | Voltage controlled oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range - A wide tuning range and constant swing VCO is described that is based on a multipass Ring Oscillator enhanced with feed-backward connections. This VCO is designed to overcome tuning range limitations of prior-art “feed-forward” ring oscillators. The Feedback multipass Ring Oscillator of the invention provides decreasing frequency when tuned by increasing the feedback, thus covering a much wider tuning range irrespective of the speed limit of the technology while at the same time providing almost constant amplitude. | 04-23-2009 |
20090108889 | Precision Integrated Phase Lock Loop Circuit Loop Filter - A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor. | 04-30-2009 |
20090108890 | Internal Supply Voltage Controlled PLL and Methods for Using Such - Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage. | 04-30-2009 |
20090108891 | BANDWIDTH CONTROL IN A MOSTLY-DIGITAL PLL/FLL - Methods and apparatus for controlling a controlled oscillator using a phase-locked loop (PLL) or frequency-locked loop (FLL) having a digital loop filter with programmable filter parameters. An exemplary PLL (or FLL) includes a digital loop filter having one or more of the programmable filter parameters, which are changed by increments during operation in order to minimize disturbances (e.g., settling transients) as the loop bandwidth of the PLL is varied from a narrow loop bandwidth to a wide loop bandwidth, or vice versa. By changing the loop filter parameters in increments the loop bandwidth can be varied with substantially no perturbation. The end result is a much faster frequency switching time, improved settling dynamics, and predictable and stable loop operating performance. According to another aspect of the invention, one or more of the programmable filter parameters are changed in order to oppose a change in tuning sensitivity of the controlled oscillator (e.g., in order to maintain a constant loop bandwidth). By holding the loop bandwidth constant, switching time is maintained substantially constant under all conditions. This allows design and production margins to be reduced in a frequency agile system, and also relaxes the tuning sensitivity linearity requirements of the controlled oscillator. | 04-30-2009 |
20090115472 | MULTIPLE REFERENCE PHASE LOCKED LOOP - A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBDIMM system, another may be a forwarded clock in an AMB | 05-07-2009 |
20090121758 | CHIPSETS AND CLOCK GENERATION METHODS THEREOF - Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock. | 05-14-2009 |
20090128203 | PLL-BASED TIMING-SIGNAL GENERATOR AND METHOD OF GENERATING TIMING SIGNAL BY SAME - A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency F | 05-21-2009 |
20090140782 | SPREAD SPECTRUM CLOCK GENERATING APPARATUS - A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spread spectrum module includes a counter, a plurality of delta-sigma counters and a data shifter. These delta-sigma counters accumulate input signals, and enable a first overflow signal while accumulation of a last stage delta-sigma counter is overflowed. The frequency of the output clock can be tuned dynamically according to the first overflow signal, and the spectrum of the output clock can be spread. | 06-04-2009 |
20090146703 | OSCILLATION CIRCUIT, TEST APPARATUS AND ELECTRONIC DEVICE - Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section. | 06-11-2009 |
20090153203 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 06-18-2009 |
20090160508 | PLL CIRCUIT - Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced. | 06-25-2009 |
20090160509 | OVERCLOCKING WITH PHASE SELECTION - A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency. | 06-25-2009 |
20090167382 | PLL Apparatus - It is an object of the present invention to provide a PLL apparatus realizing extremely high frequency stability. | 07-02-2009 |
20090167383 | Method for Generating a Clock Frequency - A method and apparatus generates a clock frequency dependent on a reference clock signal and has a phase locked loop configuration. A multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and in delayed fashion, on the other hand. The common clock signal used is a system clock signal, independent of the reference clock signal and the local clock signal and whose frequency is higher by a factor of at least “5” than the frequency of the reference clock signal and of the local clock signal, respectively. The temporal spacing between the edges of the undelayed clock signal, and of the delayed clock signal, is set such that it is greater than the temporal spacing of the sampling pulses of the phase detector that are predetermined by the system clock signal. | 07-02-2009 |
20090167384 | Dividing circuit and phase locked loop using the same - The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage. | 07-02-2009 |
20090189653 | Phase Lock Loop Clock Distribution Method and System - A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes. | 07-30-2009 |
20090195275 | TECHNIQUE FOR EFFICIENTLY MANAGING BOTH SHORT-TERM AND LONG-TERM FREQUENCY ADJUSTMENTS OF AN ELECTRONIC CIRCUIT CLOCK SIGNAL - A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control. | 08-06-2009 |
20090201057 | METHOD AND APPARATUS TO GENERATE SYSTEM CLOCK SYNCHRONIZATION PULSES USING A PLL LOCK DETECT SIGNAL - Method and apparatus for generating system clock synchronization pulses using a Phase Locked Loop (PLL) lock detect signal are provided. The method includes utilizing a clock lock detect signal indicative that a system clock is synchronized with an internal clock, and determining an initial count value. Then, start counting beginning at a first rising edge of the system clock after the clock lock detect signal is generated, the counting starting with the initial count value. The method further includes generating a synchronization pulse (syncnp) when the counting ends, where the syncnp indicates the beginning of the next system clock cycle, and continue generating syncnps separated by one system clock cycle so as to continue indicating the beginning of the next system clock cycle. The method further guarantees stopping the syncnp generation when the lock detect is inactive indicating that the internal clock and the system clock are not synchronized. | 08-13-2009 |
20090206892 | Phase-Locked Loop System and Method - A phase-locked loop including a phase detector configured to receive inputs from a reference signal path and a feedback signal path and generate a phase detector output based upon such inputs. The phase-locked loop also includes an oscillator operatively coupled with the phase detector and configured to produce an oscillatory output in response to and based upon the phase detector output, and where the oscillatory output is applied to the feedback signal path. The reference signal path includes a mixer configured to mix a reference signal with output from a direct digital synthesizer; and a switching mechanism configured to selectively place one of a plurality of different filters in series between the mixer and the phase detector. | 08-20-2009 |
20090206893 | CHARGE PUMP CIRCUIT AND PLL CIRCUIT - PLL circuit | 08-20-2009 |
20090212835 | DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP - The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled. | 08-27-2009 |
20090219067 | Locked Loop Circuit With Clock Hold Function - A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal. | 09-03-2009 |
20090251180 | ANALOG PHASE-LOCKED LOOP - Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop anangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth). | 10-08-2009 |
20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
20090251182 | Constant Phase Angle Control for Frequency Agile Power Switching Systems - Power switching systems often benefit from controlling the instant at which the power devices change state so as to minimize dissipation in these devices. Such systems often require fairly tight tolerances on reactive components and a relatively narrow frequency operating range to be certain these switching times occur as intended. This invention defines a system that can adapt the required switching instant over very wide changes in the reactive components. | 10-08-2009 |
20090256601 | PHASE TO DIGITAL CONVERTER IN ALL DIGITAL PHASE LOCKED LOOP - A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock. | 10-15-2009 |
20090261874 | Phase locked loop with small size and improved performance - A phase locked loop (PLL) includes a frequency detector and a type 1 PLL including a phase detector. The phase detector produces a phase error signal indicative of a difference in phase between a reference signal and a feedback signal, while the frequency detector produces a frequency error signal indicative of a difference in frequency between the reference signal and the feedback signal. Logic switches between the phase detector and the frequency detector based on the frequency error signal. | 10-22-2009 |
20090267661 | PLL CONTROL CIRCUIT - A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency. | 10-29-2009 |
20090273377 | THRESHOLD DITHERING FOR TIME-TO-DIGITAL CONVERTERS - Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold. | 11-05-2009 |
20090273378 | CLOCK CONFIGURATION - A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal. | 11-05-2009 |
20090295439 | Phase Lock Loop (PLL) with Gain Control - A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. | 12-03-2009 |
20090302904 | Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error - A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output. | 12-10-2009 |
20090302905 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 12-10-2009 |
20090302906 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 12-10-2009 |
20100019812 | PLL CIRCUIT, RADIO TERMINAL DEVICE AND CONTROL METHOD OF PLL CIRCUIT - There is provided a PLL circuit including a phase comparison unit that compares an accumulated addition value of a division ratio converted into a digital value and that of an oscillating signal from an oscillator controlled by using the digital value in each cycle of a reference frequency, a data conversion unit that has a variable gain amplification unit to change a gain and causes output of the phase comparison unit to converge to an arbitrary setting value, an offset detection unit that detects an offset arising due to a change in gain of the variable gain amplification unit using output of the phase comparison unit, and an offset compensation unit that compensates for the offset detected by the offset detection unit in timing when the gain of the variable gain amplification unit changes. | 01-28-2010 |
20100039151 | Phase Locked Loop, Lock Detector and Lock Detection Method - The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval. The PLL, lock detector thereof and lock detection method can detect the lock state quickly and correctly. | 02-18-2010 |
20100052746 | VOLTAGE-CONTROLLED OSCILLATOR, PHASE-LOCKED LOOP (PLL) CIRCUIT, AND CLOCK GENERATOR - A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal. | 03-04-2010 |
20100060332 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage. | 03-11-2010 |
20100073045 | FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT - A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal. | 03-25-2010 |
20100073046 | METHOD AND SYSTEM FOR A FAST-SWITCHING PHASE-LOCKED LOOP USING A DIRECT DIGITAL FREQUENCY SYNTHESIZER - Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: translating an inphase component of said first signal in frequency via a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and translating a corresponding quadrature component of said first signal in frequency via a phase-shifted version of said generated filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively. The filtered fast-switching oscillating signal may be obtained by removing at least one frequency-sum term of the fast-switching oscillating signal, where the fast-switching signal oscillating signal may be generated from a signal generated by the DDFS that may be multiplied with an oscillating reference signal. | 03-25-2010 |
20100073047 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 03-25-2010 |
20100085089 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals. | 04-08-2010 |
20100090732 | CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY - A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal | 04-15-2010 |
20100090733 | Generating Multiple Clock Phases - In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases. | 04-15-2010 |
20100097110 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT COMPRISING A VOLTAGE CONTROLLED OSCILLATOR AND METHOD OF OPERATION THEREFOR - A wireless communication unit comprises a frequency generation circuit employing a phase locked loop (PLL) circuit comprising a voltage controlled oscillator having a modulation port for directly modulating a signal output from the voltage controlled oscillator. The voltage controlled oscillator is operably coupled to at least one switch and a capacitor bank comprising one or more varactors. A controller is arranged to switch in one or more varactors associated with the modulation port of the phase locked loop circuit to provide an inverse cubic relationship to the direct modulated signal. | 04-22-2010 |
20100102858 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 04-29-2010 |
20100109724 | SUBMILLIMETER-WAVE SIGNAL GENERATION BY LINEAR SUPERIMPOSITION OF PHASE-SHIFTED FUNDAMENTAL TONE SIGNALS - Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized. | 05-06-2010 |
20100117693 | DUAL CONVERSION TRANSMITTER WITH SINGLE LOCAL OSCILLATOR - The present disclosure relates to systems, devices and methods related to transmitters, and/or transceivers having a single, tunable oscillator in a dual conversion architecture. In various exemplary embodiments, this transmitter may include: a first mixer configured to receive a first oscillator signal from the single oscillator; a filter configured to band pass filter the converted signal and output a filtered signal; and a second mixer in communication with the filter, configured to receive the filtered signal. This dual conversion transmitter may be configured to receive a communication signal from an input to the transmitter and to output a converted signal based on the first oscillator signal and the communication signal. The second mixer may be configured to receive a scaled version of the first oscillator signal and to output a desired frequency output signal based on the scaled version of the first oscillator signal and the filtered signal. | 05-13-2010 |
20100123490 | CONTROL CIRCUITRY - Control circuitry, comprising: first control means operable to generate a first control signal, the first control signal being indicative of a relationship between an output signal and a first reference signal, and to generate said output signal in dependence upon said first control signal, the first control means being configured to tend to maintain a first desired relationship between the output signal and the first reference signal in response to said first control signal; and second control means configured to influence operation of said first control means in response to said first control signal by way of a second control signal so as to tend to maintain a second desired relationship between said first control signal and a second reference signal. | 05-20-2010 |
20100123491 | EXACT FREQUENCY TRANSLATION USING DUAL CASCADED SIGMA-DELTA MODULATOR CONTROLLED PHASE LOCK LOOPS - A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit. | 05-20-2010 |
20100123492 | CONTROL APPARATUS AND CLOCK SYNCHRONIZING METHOD - A control apparatus that performs control to synchronize an output clock signal with an input clock signal includes a counting part that counts a phase difference between the input clock signal and the output clock signal, an extracting part that extracts a count value indicating, of phase differences counted by the counting part, a phase difference within a certain range, and a clock generating part that generates the output clock signal, the clock generating part being capable of controlling a frequency of the output clock signal on the basis of the extracted count value indicating the phase difference within the certain range. | 05-20-2010 |
20100127742 | Frequency locked detecting apparatus and the method therefor - The invention relates to a frequency locked detecting apparatus for detecting the frequency of an output frequency signal generated by a phase locked loop according to a input frequency signal, determining whether the phase locked loop is locked or not and generating a detecting signal correspondingly. The frequency detecting apparatus comprises an input module, a processing module, a decoding module and a control module. The inputting module generates an input signal and an enable signal according to a control signal, the input frequency signal and the output frequency signal. The processing module generates at least one processing signal corresponding to the input signal and the enable signal. The decoding module decodes at least one processing signal and generates a decoded signal. The control module generates the detecting signal according to the control signal, the enable signal and the decoded signal. | 05-27-2010 |
20100134156 | TRI-STATE DELAY-TYPED PHASE LOCK LOOP - The present invention relates to a tri-state delay-typed phase lock loop, which comprises: a phase and frequency detector, a mode detector, a mode selector, a first sampling delay unit, a plurality of counters, a second sampling delay unit, and a phase and frequency calculator. The phase and frequency of the input reference signal can be determined automatically by the phase lock loop, and the output synchronization signal can be generated such that the frequency and the phase of the output synchronization signal are identical to those of the input reference signal. | 06-03-2010 |
20100134157 | PLL circuit and method of cotrolling the same - A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability. | 06-03-2010 |
20100134158 | CLOCK EXTRACTION DEVICE WITH DIGITAL PHASE LOCK, REQUIRING NO EXTERNAL CONTROL - A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator ( | 06-03-2010 |
20100134159 | SOFT REFERENCE SWITCH FOR PHASE LOCKED LOOP - A phase locked loop includes a digital controlled oscillator and a number of phase detectors, each having a first input connected to a reference source and a second input coupled to the output of the digital controlled oscillator, and an output for producing a phase error signal. A loop filter coupled to the output of each phase detector has an output and a feedback input. An adjustment unit for derives an adjustment signal for the digital controlled oscillator from one or more of the loop filters by selecting or combining output signals from the loop filters taking into account the stability of said reference sources. The adjustment signal for the digital controlled oscillator produced by the adjustment unit is coupled to each of the feedback inputs of the loop filters. This arrangement results in hitless reference switching. | 06-03-2010 |
20100134160 | FREQUENCY SYNTHESIZER - There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency. | 06-03-2010 |
20100141310 | OPERATING CLOCK GENERATION SYSTEM AND METHOD FOR AUDIO APPLICATIONS - A clock signal generator ( | 06-10-2010 |
20100156481 | SYNCHRONIZATION SCHEME WITH ADAPTIVE REFERENCE FREQUENCY CORRECTION - The present invention relates to an apparatus and method for providing synchronization of an output signal to a synchronization information. The synchronization is accomplished by providing coupling of a correction control information that controls a signal generating means, e.g. a phase locked loop arrangement ( | 06-24-2010 |
20100156482 | MEANS TO DETECT A MISSING PULSE AND REDUCE THE ASSOCIATED PLL PHASE BUMP - A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop. | 06-24-2010 |
20100164569 | CIRCUIT ARRANGEMENT FOR FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL, PROCESSING SYSTEM AND METHOD OF FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL - A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement. | 07-01-2010 |
20100171533 | PLL CIRCUIT - A PLL comprises a current-controlled oscillator ( | 07-08-2010 |
20100171534 | CLOCK GENERATING APPARATUS AND CLOCK GENERATING METHOD - A clock generating apparatus includes a phase-difference measuring device for measuring a difference in phase between a reference clock and a feedback clock generated by a divider with a high-speed clock generated by a multiplier, an averager for averaging the measured phase difference, and an output clock generator for returning a self-generated output clock to the multiplier and the divider and generating an output clock synchronized with the reference clock by using the averaged phase difference and a generated operation clock. The multiplier generates the high-speed clock by multiplying the returned output clock, and the divider generates the feedback clock by dividing the returned output clock A frequency of generation of the output clock in the output clock generator is increased. | 07-08-2010 |
20100176853 | Monitoring apparatus and computer-readable storage medium - A monitoring apparatus monitors a system including an oscillator with a variable oscillation frequency. The monitoring apparatus has a transmitting unit to transmit an information collecting instruction for collecting state information of the system to the system at an arbitrary monitoring timing, and a control unit to perform a control operation that includes transmitting to the system control information for controlling the oscillation frequency to become a reference value or less if the oscillation frequency exceeds the reference value, and computing a changing amount of the oscillation frequency at least due to aging and a next monitoring timing. | 07-15-2010 |
20100194455 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - A semiconductor integrated circuit apparatus includes a main clock generation circuit that generates a main clock signal, a plurality of function blocks, a clock generation circuit in the plurality of function blocks, and a phase locked loop circuit in the clock generation circuit. The phase locked loop circuit generates a clock signal in the plurality of function blocks, using the main clock signal from the main clock generation circuit. | 08-05-2010 |
20100213993 | Phase Locked Oscillator And Radar Unit Having The Same - An error detecting unit of a phase-locked oscillator evaluates difference between a reference phase error signal output from a phase detector and a phase error signal actually output from the phase detector when a reference frequency modulation signal is output from a voltage-controlled oscillator and further detects a frequency error of the frequency modulation signal from the voltage-controlled oscillator based on a rate of change of the difference. A correction unit of the phase-locked oscillator calculates an average value of the frequency error in a predetermined section of the frequency modulation signal and corrects center frequency of the frequency modulation signal by correcting the average value to be zero, and changes the rate of change of control voltage per control step based on comparison between at least two frequency errors in one cycle of the frequency modulation signal. Thus frequency shift of the frequency modulation signal is corrected. | 08-26-2010 |
20100225367 | FREQUENCY SYNTHESIZER WITH IMMUNITY FROM OSCILLATOR PULLING - Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency. | 09-09-2010 |
20100244913 | Method and appartus for exchanging data between devices operating at different clock rates - Source-synchronous communications between networked devices can be hindered by differing clock rates and data interface formats among the devices. By implementing a plurality of clock converters, a data interface format of a transmitting device is converted to a data interface format compatible with a receiving device. The clock converters provide a clock signal based on the source-synchronous data clock, and having a phase controlled with respect to an associated data signal. As a result, data exchange between devices operating at different clock rates is made possible. | 09-30-2010 |
20100253400 | Phase-Locked Loop (PLL) Having Extended Tracking Range - A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width. | 10-07-2010 |
20100253401 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component. | 10-07-2010 |
20100253402 | COMMUNICATION SYSTEM, PHASE-LOCKED LOOP, MOVABLE BODY AND COMMUNICATION METHOD - A communication system includes a phase-locked loop that maintains synchronization of a reception signal. The phase-locked loop includes a loop filter that has a circuit configuration m for an m-th order phase-locked loop including a circuit configuration n for an n-th order phase-locked loop (m>n), and a switching section that switches circuit configurations, which are activated in the loop filter, between the circuit configuration n and the circuit configuration m. | 10-07-2010 |
20100264961 | Oscillation frequency control circuit - Provided is an oscillation frequency control circuit for correcting its frequency, keeping the oscillation frequency stable when self-oscillating, and oscillating with a control voltage generated by making a fixed voltage given from outside variable. In the oscillation frequency control circuit, a CPU selects/outputs the control voltage preferentially according to a command of a control voltage selection. If the command is not given and the level of an outside reference signal detected by a detecting circuit is within an adequate range, it turns a select switch on. If the command is not given and the level of the outside reference signal is out of the adequate range, it turns the select switch off and outputs information about pulse generation stored in a memory to a PWM circuit. | 10-21-2010 |
20100264962 | VCO DRIVING CIRCUIT AND FREQUENCY SYNTHESIZER - A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF | 10-21-2010 |
20100301910 | Frequency synthesizer - A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit. | 12-02-2010 |
20100308878 | AUTOMATIC CONTROL OF CLOCK DUTY CYCLE - In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops. | 12-09-2010 |
20100315136 | PLL CIRCUIT AND VOLTAGE-CONTROLLED OSCILLATOR - In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values. The oscillator outputs a signal with the oscillation frequency corresponding to the control voltage and associated with the correspondence relation specified by the controlling value. | 12-16-2010 |
20100315137 | PLL circuit - A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit | 12-16-2010 |
20110001523 | FREQUENCY SYNTHESIZER - Provided is a frequency synthesizer capable of fine setting over a wide band and having a wide frequency pull-in range. A sine wave signal of an output frequency of a voltage controlled oscillating part is quadrature-detected, and in a PLL utilizing a vector rotating at a frequency (velocity) equal to a difference from a frequency of a frequency signal used for the detection, a frequency pull-in means integrates a first constant for increasing the output frequency as a pull-in voltage when a control voltage from the PLL to the voltage controlled oscillating part is larger than a prescribed set range, and integrates a second constant for decreasing the output frequency as the pull-in voltage when the control voltage is smaller than the set range. Then, an adding means adds the control voltage from the PLL and the pull-in voltage from the frequency pull-in means to output an addition result to the voltage controlled oscillating part. | 01-06-2011 |
20110001524 | Phase locked loop circuit - A Phase Locked Loop circuit, includes: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of the main path; and a local feedback path through which feedback is carried out from a path middle of the main path to a path middle of an input stage side; the main path including a phase detector, a loop filter, and a controlled oscillator, and the local feedback path including a replica portion, a delay portion, a first subtracter, and a second subtracter. | 01-06-2011 |
20110006819 | LEVEL-RESTORED SUPPLY-REGULATED PLL - The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage. | 01-13-2011 |
20110012652 | Phase-Locked Loop - A loop filter for receiving an input signal indicative of a phase-difference between a reference signal and a signal output by a signal generator and forming a control signal for controlling the signal generator in dependence thereon, the loop filter comprising a plurality of filter components that determine the frequency response of the filter, said filter components being arranged so that a first set of said components determines one or more zeros of the filter's frequency response and a second set of said components determines one or more poles of the filter's frequency response, each of said first and second sets of filter components being independent of the other such that the zero(s) and pole(s) of the filter's frequency response may be selected independently. | 01-20-2011 |
20110018596 | Phase Locked Loop and 3-Stage Frequency Divider - The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies. | 01-27-2011 |
20110018597 | Phase Locked Loop and Phase-Frequency Detector - The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current. | 01-27-2011 |
20110025385 | Power Supply Noise Rejection in PLL or DLL Circuits - A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock. | 02-03-2011 |
20110025386 | Phase-Locked Loop - A loop filter for a phase-locked loop that generates an output signal having a predetermined phase relationship with a reference signal, the loop filter being arranged to control a signal generator that forms the output signal in dependence on a phase error between the output signal and the reference signal by outputting a control signal for controlling the signal generator in dependence thereon, the loop filter being arranged to form the control signal to comprise a proportional component representative of an instantaneous magnitude of the phase difference and an integral component representative of an integral of the phase difference, the loop filter comprising a proportional path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the proportional component of the control signal in dependence thereon and an integral path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the integral component of the control signal in dependence thereon, the proportional and integral paths being decoupled in the loop filter such that each has a transfer function relating its received signal to its respective component of the control signal that is independent of the other path. | 02-03-2011 |
20110032011 | AUTO FREQUENCY CALIBRATOR, METHOD THEREOF AND FREQUENCY SYNTHESIZER USING IT - The present invention relates to and auto frequency calibrator, a method thereof, and a frequency synthesizer using it. The auto frequency calibrator includes a capacitor bank selector that is operated as an open loop and compares a frequency signal having integer-divided reference frequency with the reference frequency signal to select a capacitor bank corresponding to an output frequency; and a capacitor bank controller that is operated as a closed loop when the capacitor bank is selected and compares the output voltage corresponding to the output frequency with a preset voltage range to control the capacitor bank selected in the capacitor bank selector. | 02-10-2011 |
20110032012 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a control loop including a frequency divider configured to frequency-divide an output clock and to control a frequency of the output clock according to a phase difference between a local clock and a phase-divided local clock; and a control unit configured to control a frequency dividing ratio of the frequency divider according to a phase difference between the output clock and an input clock that corresponds to data taken in based on the output clock. | 02-10-2011 |
20110032013 | Digital Phase-Locked Loop Clock System - A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD. | 02-10-2011 |
20110043261 | PLL CIRCUIT - A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop. | 02-24-2011 |
20110050301 | Phase Locked Loop Circuitry Having Switched Resistor Loop Filter Circuitry, and Methods of Operating Same - Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry. The frequency detection circuitry includes (i) circuitry to generate a signal which is representative of the frequency of the output signal of the phase-locked loop circuitry, (ii) comparison circuitry to compare the signal which is representative of the frequency of the output signal of the phase-locked loop circuitry to a reference input to the phase-locked loop circuitry, and (iii) a switched capacitor network including at least one capacitor. | 03-03-2011 |
20110057693 | DIRECT DIGITAL INTERPOLATIVE SYNTHESIS - A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider. | 03-10-2011 |
20110063000 | HIERARCHICAL GLOBAL CLOCK TREE - Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed. | 03-17-2011 |
20110063001 | SIGNAL GENERATING METHOD FOR CLOCK RECOVERY AND CLOCK RECOVERY CIRCUIT - A signal generating method and circuit for reducing jitters occurring in a recovered clock signal CK since even when multiple items of specific data are inserted in one cycle of generation period for an enable period, a deviation of an output cycle of the enable period can be eliminated. | 03-17-2011 |
20110068840 | USE OF DATA DECISIONS FOR TEMPORAL PLACEMENT OF SAMPLERS - A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected position of the edges. A further correction to the sampling position is made in response to the recent history of the data received. The correction is modelled on predictable jitter, for example, that in a transmitter caused by changes in data causing the supply voltage to drop. | 03-24-2011 |
20110068841 | High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same - A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground. | 03-24-2011 |
20110074474 | PHASE-LOCKED-LOOP CIRCUIT - A phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from −180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal. | 03-31-2011 |
20110074475 | Frequency synthesizer - There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled. | 03-31-2011 |
20110074476 | APPARATUS FOR LOCK-IN AMPLIFYING AN INPUT SIGNAL AND METHOD FOR GENERATING A REFERENCE SIGNAL FOR A LOCK-IN AMPLIFIER - Apparatus ( | 03-31-2011 |
20110080196 | VCO Control Circuit and Method Thereof, Fast Locking PLL and Method for Fast Locking PLL - A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve. | 04-07-2011 |
20110080197 | APPARATUS AND METHODS FOR POWER QUALITY MEASUREMENT - A method for measuring characteristics of a power line signal having a fundamental frequency is provided. The method includes estimating the fundamental frequency of the power line signal, and generating a sampling clock that is substantially synchronized to the estimated fundamental power line frequency. The power line signal is sampled with the substantially synchronized sampling clock to generate data samples that include one or more substantially complete cycles of the power line signal. The data samples are processed to detect zero crossings of the power line signal, and the detected zero crossings are used to calculate an r.m.s. voltage of the power line signal measured over one full cycle, commencing at a zero crossing, and refreshed each half-cycle. Other aspects are also provided. | 04-07-2011 |
20110084741 | FAST-LOCKING BANG-BANG PLL WITH LOW OUPUT JITTER - The present invention relates to a gigitaol phaselocked loop DPLL ( | 04-14-2011 |
20110089982 | Fast Lock-In All-Digital Phase-Locked Loop with Extended Tracking Range - An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock. | 04-21-2011 |
20110102030 | SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES - A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse. | 05-05-2011 |
20110102031 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage. | 05-05-2011 |
20110109353 | DIGITAL PLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value. | 05-12-2011 |
20110109354 | AUTOMATIC CONTROL OF CLOCK DUTY CYCLE - In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops. | 05-12-2011 |
20110115534 | OPTICAL FREQUENCY SOURCE - A frequency reference, comprising: an optical waveguide closed on itself so that a light pulse inserted into the waveguide circulates therein; a light source coupled to the waveguide and controllable to generate a light pulse that circulates in the waveguide; and a detector coupled to a region of the waveguide that generates an output pulse each time the circulating light pulse passes the region. | 05-19-2011 |
20110121871 | CURRENT CONVERTING METHOD, TRANSCONDUCTANCE AMPLIFIER AND FILTER CIRCUIT USING THE SAME - The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output. | 05-26-2011 |
20110121872 | SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL - A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value. | 05-26-2011 |
20110121873 | Phase Locked Loop Including A Frequency Change Module - A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur. | 05-26-2011 |
20110128054 | PHASE LOCK LOOP WITH TRACKING FILTER FOR SYNCHRONIZING AN ELECTRIC GRID - Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. Voltage vectors may be synchronized in a phase-locked-loop configured to maintain synchronous operation of the grid even when the voltages are unbalanced. For example, a phase-locked-loop may be coupled to one or more tracking filters designed to estimate a disturbance in an error signal of the voltages. The estimated disturbance(s) may be removed from the error signal before the phase lock loop determines an estimate of the grid frequency. Thus, adverse affects of voltage unbalance, such as abnormal current behavior, may be mitigated. | 06-02-2011 |
20110128055 | DLL FOR PERIOD JITTER MEASUREMENT | 06-02-2011 |
20110133794 | PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION - A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO). | 06-09-2011 |
20110133795 | DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY - There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively. | 06-09-2011 |
20110133796 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED THEREWITH - It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal. | 06-09-2011 |
20110133797 | NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING - A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL). | 06-09-2011 |
20110133798 | SYNTHESIZER AND RECEPTION DEVICE AND ELECTRONIC DEVICE USING THE SAME - A synthesizer includes: a synthesizer unit that outputs an oscillation signal based on a reference oscillation signal; a temperature detecting unit that detects a temperature; a time variation detecting unit that detects a time variation in frequency of the reference oscillation signal based on a result of temperature detection by the temperature detecting unit; and a control unit that adjusts a frequency of the oscillation signal outputted from the synthesizer unit based on a result of detection by the time variation detecting unit. With such a configuration, frequency compensation control is performed on a transducer having a large temperature coefficient. | 06-09-2011 |
20110140745 | Method for Modeling Variation in a Feedback Loop of a Phase-Locked Loop - A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay. | 06-16-2011 |
20110140746 | DUAL-BAND WIDEBAND LOCAL OSCILLATION SIGNAL GENERATOR - A dual-band wideband local oscillation signal generator includes an oscillation unit, a division unit, a poly phase filter (PPF), a switch unit, and a single side band (SSB) mixer. The oscillation unit is configured to generate a positive in-phase (IP) signal, a negative in-phase (IN) signal, a negative quadrature-phase (QN) signal, and a positive quadrature-phase (QP) signal. The division unit is configured to divide frequencies of the IP signal and the IN signal and generate an RF signal. The PPF is configured to receive the IP signal and the IN signals inputted to the division unit, and generate an LO IP signal, an LO IN signal, an LO QP signal, and an LO QN signal. The switch unit is configured to receive the generated LO signals and select a high band frequency signal or a low band frequency signal. | 06-16-2011 |
20110140747 | ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE - The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation. | 06-16-2011 |
20110156773 | Low Noise Fractional Divider Using A Multiphase Oscillator - A frequency synthesis circuit is disclosed. The circuit includes a phase-locked loop and multi-phase oscillator such as a rotary traveling wave oscillator (RTWO). The oscillator provides a plurality of phases that are applied to a selection circuit. The selection circuit, in response to the output of a delta-sigma modulator, selects one of the phases of the multi-phase oscillator to minimize phase shift noise when the divider ratio in the loop changes, thereby eliminating a source of noise that contaminates the synthesized frequency. This permits the use of the frequency synthesis in applications requiring a high degree of spectral purity. | 06-30-2011 |
20110156774 | CIRCUIT AND METHOD FOR GENERATING A CLOCK SIGNAL - A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator. | 06-30-2011 |
20110156775 | PHASE LOCK LOOP DEVICE AND CONTROL METHOD THEREOF - A phase lock loop device and a control method is disclosed in the present invention. The phase lock loop device includes a phase lock loop circuit and a memory unit. The phase lock loop generates a phase lock clock signal according to a control voltage. The memory unit couples the phase lock loop circuit. The memory unit provides an initial signal to the phase lock loop circuit for recovering the control voltage to a preset value according to a digital value while the phase lock loop circuit is enabled. | 06-30-2011 |
20110156776 | Locked Loop Circuit With Clock Hold Function - A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal. | 06-30-2011 |
20110169535 | FREQUENCY AND PHASE ACQUISITION OF A CLOCK AND DATA RECOVERY CIRCUIT WITHOUT AN EXTERNAL REFERENCE CLOCK - A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics. | 07-14-2011 |
20110169536 | SYSTEM AND METHOD OF ASYNCHRONOUS LOGIC POWER MANAGEMENT - Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals are received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled. A voltage supplied to the processing circuit is adjusted based on the composite difference. | 07-14-2011 |
20110175653 | CLOCK DEVICE - There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part. | 07-21-2011 |
20110181327 | PLL oscillator circuit - Disclosed is a PLL oscillator circuit capable of examining an unlock state while being equipped with an auto retry function enabling automatic relock. In the PLL oscillator circuit, a MPU receives a lock detection signal from the PLL-IC that receives an external reference signal and an output signal from a VCXO and outputs a control voltage to the VCXO, sets data for unlock alarm test at the PLL-IC, the data turning a lock state into an unlock state, when determining an unlock state with the lock detection signal from the PLL-IC, outputs an unlock alarm output signal to the outside, determines whether the unlock state continues for a first time period, and when the unlock state continues for the first time period, executes retry to set data for relock at the PLL-IC. | 07-28-2011 |
20110187422 | Temperature compensation for an oscillator crystal - An electronic device is equipped with an oscillator interface to be coupled to an oscillator crystal of an oscillator element. The electronic device includes an oscillator circuit which is coupled to the oscillator interface and generates an oscillator signal. The electronic device is further provided with a temperature measurement interface to be coupled to a temperature sensor of the oscillator element so as to receive the temperature signal. For accomplishing temperature compensation, the electronic device is provided with a measurement controller coupled to the measurement interface and configured to measure a first value of the temperature signal at a first point of time and a second value of the temperature signal at a second point of time. A frequency drift estimator is provided so as to estimate a frequency drift of the oscillator signal on the basis of the first value of the temperature signal and a second value of the temperature signal. By means of a compensation logic, a frequency compensation signal for the oscillator circuit is generated on the basis of the estimated frequency drift. | 08-04-2011 |
20110187423 | MULTI-OUTPUT PLL OUTPUT SHIFT - Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal. Controlling also includes coupling the shifter circuit output to a first frequency divider. | 08-04-2011 |
20110187424 | TIME-DOMAIN MEASUREMENT OF PLL BANDWIDTH - A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) ( | 08-04-2011 |
20110193600 | Methods of Frequency versus Temperature Compensation of Existing Crystal Oscillators - Methods for compensating the existing crystal oscillator frequencies in extended temperature ranges. These are utilizing existing crystal oscillators on any system design which may have quartz crystals with associated circuitry to deliver frequency or timing reference signals. They are increasing these existing circuitry's accuracy simply by adding small integrated circuit component. | 08-11-2011 |
20110193601 | FRACTIONAL TYPE PHASE-LOCKED LOOP CIRCUIT WITH COMPENSATION OF PHASE ERRORS - A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value. | 08-11-2011 |
20110199135 | Pll circuit - A PLL circuit is provided capable of reducing phase noise and facilitating design. In the PLL circuit, a PLL receives a reference frequency and an output from a VC-TCXO, performs a lock operation. In a lock state, a selector selects an output of a first divider that divides the reference frequency. When PLL detects input of reference frequency being lost or an unlock state, the PLL outputs an alarm signal to the selector. When receiving the alarm signal from the PLL, the selector switches from the output of the first divider to an output of a second divider that frequency-divides an output of the VC-TCXO, and outputs the same. Then, a PLL receives an output of the selector and an output of a VCXO and performs a lock operation. | 08-18-2011 |
20110204935 | PLL circuit - Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC. | 08-25-2011 |
20110204936 | APPARATUS AND METHODS FOR REDUCING NOISE IN OSCILLATING SIGNALS - Methods and apparatus are described for reducing noise, such as phase noise, in an oscillating signal. The oscillating signal may be generated by a signal generator having a mechanical resonator, such as a crystal oscillator. A filter may be coupled to the output of the mechanical resonator and may have its center frequency adjusted using a phase-locked loop (PLL). A feedback signal from the filter to the signal generator may also be used. | 08-25-2011 |
20110221489 | AUTOMATIC FREQUENCY CALIBRATION CIRCUIT AND AUTOMATIC FREQUENCY CALIBRATION METHOD - An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency divider unit according to a required precision. A first and a second frequency detecting units detect a reference frequency and an output frequency of the frequency divider unit, respectively. A judging interval unit defines at least one judging period in a total comparison time. A comparator compares the outputs of the first and the second frequency detecting units and outputs a comparison result at the judging period. Wherein, the state machine changes the capacitor configuration of a voltage-controlled oscillator when the comparison result shows that the reference frequency does not match the output frequency of the frequency divider unit. | 09-15-2011 |
20110221490 | PLL apparatus - There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator according to whether the amplitude level falls within the proper range or not. The PLL apparatus includes: a switching unit switching a signal that is to be supplied to a control voltage output unit between a signal of a phase comparison unit and a preset signal of a preset signal output unit; a protection circuit provided between a signal path of a reference frequency signal and a ground and having diodes that are connected in inverse parallel in order to regulate an amplitude level of the reference frequency signal; a temperature detection unit detecting an atmospheric temperature of the protection circuit; and a level detection unit detecting the amplitude level of the external reference frequency signal, and threshold values as references for the switching are set according to the detected temperature, thereby coping with a change in the amplitude level due to a temperature characteristic of the diodes. | 09-15-2011 |
20110221491 | RECEIVING CIRCUIT AND SAMPLING CLOCK CONTROL METHOD - A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value. | 09-15-2011 |
20110221492 | DIGITALLY CONTROLLED OSCILLATOR - Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal. | 09-15-2011 |
20110221493 | Constant Phase Angle Control for Frequency Agile Power Switching Systems - Power switching systems often benefit from controlling the instant at which the power devices change state so as to minimize dissipation in these devices. Such systems often require fairly tight tolerances on reactive components and a relatively narrow frequency operating range to be certain these switching times occur as intended. This invention defines a system that can adapt the required switching instant over very wide changes in the reactive components. | 09-15-2011 |
20110227614 | TCXO Replacement for GPS - To determine the level of frequency drift of a crystal oscillator as a result of a change in the its temperature, the temperature of the crystal oscillator is sensed and used together with previously stored data that includes a multitude of drift values of the frequency of the crystal oscillator each associated with a temperature of the crystal oscillator. Optionally, upon initialization of a GPS receiver in which the crystal oscillator is disposed, an initial temperature of the crystal oscillator is measured and a PLL is set to an initial frequency in association with the initial temperature. When acquisition fails in a region, the ppm region is changed. The temperature of the crystal oscillator is periodically measured and compared with the initial temperature, and the acquisition process is reset if there is a significant change in temperature. The GPS processor enters the tracking phase when acquisition is successful. | 09-22-2011 |
20110234270 | LOCAL OSCILLATOR AND PHASE ADJUSTING METHOD FOR THE SAME - According to one embodiment, a local oscillator includes a digitally-controlled oscillator that outputs an oscillating signal having a frequency N times as large as an oscillating frequency according to an oscillator tuning word; a frequency divider that performs a 1/N frequency division of the oscillating signal, and outputs a 2N phase clock; a counter that counts the clock and outputs the count value as integer oscillator phase data based upon a reference signal; a first flip-flop that latches the clock with the reference signal, and outputs the resultant as first phase information; a variable delay circuit that delays the reference signal and outputs the resultant as a delay reference signal; a second flip-flop that latches the clock with the delay reference signal, and outputs the resultant as second phase information; a delay control unit that controls a delay amount of the variable delay circuit; a data conversion unit that outputs fractional oscillator phase data based upon the first and second phase information; an adder that adds the integer oscillator phase data and the fractional oscillator phase data, and outputs the added value as third phase information; and a filter that smoothes the difference between a reference phase for setting the oscillating frequency of the digitally-controlled oscillator and the third phase information so as to output the oscillator tuning word. | 09-29-2011 |
20110234271 | HIGH RESOLUTION CLOCK SIGNAL GENERATOR - A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period T | 09-29-2011 |
20110248753 | Suppression of Low-Frequency Noise from Phase Detector in Phase Control Loop - The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance. | 10-13-2011 |
20110248754 | SYNCHRONIZATION SCHEME WITH ADAPTIVE REFERENCE FREQUENCY CORRECTION - An apparatus and a method provide synchronization of an output signal to a synchronization information. The synchronization is accomplished by providing coupling of a correction control information that controls a signal generator, e.g. a phase locked loop arrangement or a direct digital synthesis arrangement, to its exact frequency to a frequency conversion unit that converts an uncorrected reference frequency to a correct or exact reference frequency. Thereby, the uncorrected reference frequency for the signal generator can be provided by a simple crystal oscillator without any frequency controller. The setting of the signal generator and the frequency conversion unit can be done in a predetermined sequence which enables a user equipment to synchronize its reference frequency to the synchronization information emitted by a communication network. | 10-13-2011 |
20110254599 | Method and Apparatus for MEMS Phase Locked Loop - The proper operation of a phase locked loop is determined by monitoring certain signals within the loop for their phase relationship or duty cycle. If a malfunction of the loop is detected, proper operation may be imposed or restored by resetting a phase-frequency detector, or by flipping the output of the phase-frequency detector. | 10-20-2011 |
20110254600 | PHASE LOCKED LOOP, SEMICONDUCTOR DEVICE, AND WIRELESS TAG - An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit. | 10-20-2011 |
20110260761 | TEMPERATURE COMPENSATION IN A PHASE-LOCKED LOOP - An integrated circuit comprises a digital phase-locked loop for a wireless communications unit. The digital phase-locked loop comprises a voltage controlled oscillator and a digital tuning subsystem. An input of the digital tuning subsystem receives the output signal from the voltage controlled oscillator, and an output of the digital tuning subsystem is supplied to the voltage controlled oscillator. A digital voltage generator is adapted to store at least two predetermined forcing voltages. The digital voltage generator is adapted to select one of the at least two predetermined forcing voltages, in dependence on a current temperature value, and to supply it as a forcing voltage to an input of the voltage controlled oscillator, prior to the phase locked loop achieving lock. A wireless communication unit and a method of tuning a phase-locked loop are also provided. | 10-27-2011 |
20110260762 | APPARATUS AND METHOD FOR VCO CALIBRATION USING FAST FREQUENCY COMPARISON BASED ON PHASE MANIPULATION - An apparatus and a method for calibrating a Voltage Controlled Oscillator (VCO) using a fast frequency comparison based on phase manipulation are provided. The calibrating apparatus includes a phase shifter for comparing an input reference frequency and an input divided frequency and shifting a phase of the reference frequency to make the phase of the reference frequency align with a phase of the divided frequency; a frequency comparator for determining which one of the phase-shifted reference frequency and the divided frequency is higher; and a cap-bank control for determining a frequency to use based on a comparison result of the frequency comparator. | 10-27-2011 |
20110267116 | METHOD AND CIRCUIT FOR DISPLAYPORT VIDEO CLOCK RECOVERY - A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system. | 11-03-2011 |
20110267117 | DATA INPUT/OUTPUT APPARATUS AND METHOD FOR SEMICONDUCTOR SYSTEM - A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received. | 11-03-2011 |
20110285433 | SYSTEM AND METHOD FOR CORRECTING PHASE NOISE IN DIGITAL-TO-ANALOG CONVERTER OR ANALOG-TO-DIGITAL CONVERTER - A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal. | 11-24-2011 |
20110285434 | HETEROGENEOUS PHYSICAL MEDIA ATTACHMENT CIRCUITRY FOR INTEGRATED CIRCUIT DEVICES - An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry. | 11-24-2011 |
20110285435 | PLL FREQUENCY SYNTHESIZER - A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof. | 11-24-2011 |
20110285436 | INTEGRATED CIRCUITS WITH FREQUENCY GENERATING CIRCUITS - An integrated circuit comprises at least first and second frequency generating circuits, wherein each frequency generating circuit comprises a reference frequency source; a voltage controlled oscillator; and a feedback control circuit for controlling the voltage controlled oscillator to provide a desired output frequency signal. The output of the voltage controlled oscillator of the first frequency generating circuit is switched into the feedback control circuit of the second frequency generating circuit to provide a test signal for testing one or more components of the feedback control circuit of the second frequency generating circuit. | 11-24-2011 |
20110285437 | SYSTEM AND A METHOD FOR CONTROLLING AT LEAST ONE VOLTAGE CONVERTER HAVING A PLURALITY OF CELLS IN SERIES - A method of controlling at least one voltage converter having a plurality of cells in series, comprising an AC part and a DC part, characterized in that the AC input voltage (Vei) of each cell is determined directly by the use of a high speed current control loop relating to the AC part and a lower speed voltage control loop relating to the cells, the method including choosing the following voltage control law: | 11-24-2011 |
20110291714 | Phase-Locked Loop With Novel Phase Detection Mechanism - A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to D2A module, D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection does not rely on edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input, as opposed to the aforementioned fixed external source, such as, a crystal. | 12-01-2011 |
20110298505 | LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal. | 12-08-2011 |
20110298506 | INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE - An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source. | 12-08-2011 |
20110298507 | SYSTEM AND METHOD FOR CALIBRATING OUTPUT FREQUENCY IN PHASE LOCKED LOOP - A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC. | 12-08-2011 |
20110309866 | DELAY-LOCKED LOOP HAVING A LOOP BANDWIDTH DEPENDENCY ON PHASE ERROR - Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance. | 12-22-2011 |
20110316595 | VCO FREQUENCY TEMPERATURE COMPENSATION SYSTEM FOR PLLS - The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input. | 12-29-2011 |
20110316596 | PHASE LOCKING FOR MULTIPLE SERIAL INTERFACES - An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock. In this way, each high speed serial interface loop between the main board and the individual system boards is controllably adjusted in phase, compensating for interconnection path lengths and providing synchronism between the received signal and the common, static-phase, master reference clock which supplies all the main controller board receivers. | 12-29-2011 |
20110316597 | SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY - Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent. | 12-29-2011 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
20120007641 | ELECTRONIC PART AND METHOD OF DETECTING FAULTS THEREIN - An electronic component includes an oscillator element, a driving circuit outputting a driving signal to the oscillator element, a clock frequency generator outputting a clock signal to the driving circuit, a clock frequency controller controlling a frequency of the clock signal, a consumption-current detection unit detecting a consumption current of the driving circuit, and a fault detection unit electrically connected to the consumption-current detection unit and the clock frequency controller. When the clock frequency controller changes the frequency of the clock signal, the detected consumption current changes, and allows the consumption-current detection unit to detect the change of the consumption current. The fault detection unit detects a fault based on the change of the frequency of the clock signal and the change of the consumption current. This electronic component can have a fault detection function and a small size. | 01-12-2012 |
20120007642 | REFERENCE FREQUENCY GENERATING DEVICE - The disclosed is a reference frequency generating device ( | 01-12-2012 |
20120013375 | FREQUENCY SYNTHESIZER DEVICE AND MODULATION FREQUENCY DISPLACEMENT ADJUSTMENT METHOD - A frequency synthesizer device that includes two modulation paths and suitably adjusts the amplitude of a control voltage that is outputted from a digital-to-analog converter (DAC) to a voltage-controlled oscillator. The frequency synthesizer device is provided with a voltage-controlled oscillator, a programmable frequency divider, a frequency phase comparator, a DAC, a switch and a modulation frequency displacement correction circuit. The voltage-controlled oscillator oscillates at an oscillation frequency depending on an input voltage. The programmable frequency divider frequency-divides a signal from the voltage-controlled oscillator. The frequency phase comparator outputs a phase difference between the frequency-divided signal and a reference clock. The DAC outputs an adjustment voltage. The switch connects the voltage-controlled oscillator to a reference voltage power source at a time of correction of the adjustment voltage. The modulation frequency displacement correction circuit specifies adjustment data that corresponds to the adjustment voltage corresponding to the target frequency displacement. | 01-19-2012 |
20120013376 | USE OF PLL STABILITY FOR ISLANDING DETECTION - A phase detector for a phase-locked loop includes a phase detector that is configured to become unstable, oscillate and drift rapidly in frequency in a predictable manner when a reference frequency signal is not available. When applied, for example, to a power converter connected to a power distribution grid, the predictable oscillatory and rapid frequency drift behavior when the phase detector is unstable allows very rapid and reliable detection of disconnection from the grid, referred to as islanding. | 01-19-2012 |
20120019293 | DELAY LOCK LOOP PHASE GLITCH ERROR FILTER - A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter unit to provide filtering of noise on a phase control signal to substantially reduce a false delay lock loop state. | 01-26-2012 |
20120025879 | PLL CIRCUIT, METHOD FOR OPERATING PLL CIRCUIT AND SYSTEM - A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal. | 02-02-2012 |
20120025880 | Fractional Spur Reduction Using Controlled Clock Jitter - In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL. | 02-02-2012 |
20120032718 | Digital Phase Lock System with Dithering Pulse-Width-Modulation Controller - A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths. | 02-09-2012 |
20120038400 | METHOD AND APPARATUS FOR JITTER REDUCTION - A low bandwidth phase lock loop (PLL) arranged in a dual-loop configuration is disclosed. The first loop is a standard loop configuration using a crystal oscillator as a reference clock. The loop parameters for this first PLL can be optimized to work over a wide range of output frequencies, and with a minimum amount of jitter. The first loop outputs a reference signal, which is a VCO output. The second loop comprises a bang-bang detector configured to drive a digital loop filter, which then drives a phase interpolator. The phase interpolator manipulates the output phase. Since phase and frequency are related, where frequency is the derivative of phase, small frequency offsets can be made using a phase control signal, generated within the second loop based on the relation between the reference signal and the clock input signal. The second loop sets the jitter transfer bandwidth of the system. | 02-16-2012 |
20120038401 | METHOD OF COMPENSATING AN OSCILLATION FREQUENCY AND PLL - A method for compensating an oscillation frequency, a device, and a phase locked loop (PLL) is applied in the LC oscillating loop, including: sending voltage control signals to one end of a variable capacitor of an LC oscillating loop to generate oscillating signals in the LC oscillating loop through the voltage control signals; obtaining variable bias voltage that reflects changes of external parameters; and sending the variable bias voltage to the other end of the variable capacitor to compensate changes to the oscillation frequency of oscillation signals generated in the LC oscillating loop. This disclosure compensates the changes to the oscillation frequency of the circuit that contains the LC oscillating loop and improves the stability of the circuit oscillation frequency by sending bias voltage to one end of the variable capacitor of the LC oscillating loop. | 02-16-2012 |
20120044000 | Method and Apparatus for Accurate Clock Synthesis - Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor. | 02-23-2012 |
20120044001 | SIGNAL PROCESSING APPARATUS - A signal processing apparatus of the present invention includes an input unit configured to receive a reference signal supplied from an external device, a phase detection unit configured to detect a phase difference between the reference signal received from the input unit and a clock signal, a generation unit configured to generate the clock signal with a frequency corresponding to an output of the phase detection unit, and a control unit configured to detect an error between a frequency of the reference signal received from the input unit and the frequency of the clock signal based on an output of the phase detection unit and to output information, which indicates the status of a frequency change in the reference signal, to a display device based on the detected error. | 02-23-2012 |
20120056651 | FREQUENCY CALIBRATION CIRCUIT FOR AUTOMATICALLY CALIBRATING FREQUENCY AND METHOD THEREOF - A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period. | 03-08-2012 |
20120062287 | INJECTION-LOCKED FREQUENCY DIVIDING APPARATUS - An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary. | 03-15-2012 |
20120062288 | Device and Method for Generating a Signal of Parametrizable Frequency - Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider. | 03-15-2012 |
20120062289 | LOCAL OSCILLATOR - A local oscillator of an embodiment includes a digitally-controlled oscillator, a phase data generator, a subtractor, a loop filter, a multiplier, and a coefficient calculator. The digitally-controlled oscillator variably controls an oscillation frequency of an oscillation signal by using a first oscillator control value. The oscillation frequency is equal to a product of the first oscillator control value multiplied by an amount of change in the oscillation frequency per unit first oscillator control value. Set frequency data is calculated by dividing a set frequency by a reference frequency of a reference signal. The multiplier outputs the first oscillator control value obtained by multiplying a normalized control value from the loop filter by a first coefficient. The coefficient calculator divides, by the set frequency data, the first oscillator control value which makes the oscillation frequency roughly equal to the set frequency, and sets the quotient as a new first coefficient in the multiplier. | 03-15-2012 |
20120062290 | METHODS AND SYSTEMS FOR DIGITAL PULSE WIDTH MODULATOR - In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed. | 03-15-2012 |
20120068742 | METHOD AND APPARATUS FOR EFFICIENT TIME SLICING - Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit. | 03-22-2012 |
20120068743 | Feedback-Based Linearization of Voltage Controlled Oscillator - Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodiments enable constant VCO gain over a wide input tuning range and across PVT variations. Further, embodiments can be nested within a PLL, for example, with negligible area and power consumption overhead. | 03-22-2012 |
20120074995 | Fractional-N PLL Using Multiple Phase Comparison Frequencies to Improve Spurious Signal Performance - SEARCHES A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies F | 03-29-2012 |
20120081158 | REFERENCE CLOCK SAMPLING DIGITAL PLL - A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the period representation of a desired frequency, and the frequency error signal is integrated in a loop filter and applied as a control input to the DCO. To prevent spurious emissions resulting from the accumulation of quantization errors in the frequency determination and comparison operations, the arrival time of state transition edges of the reference frequency clock signal are randomized prior to sampling. The edge randomization control signal preferably has a triangular probability density function, and its spectrum has most significant energy outside the loop bandwidth of the DPLL; hence, the spurious emissions caused by the accumulation of quantization errors are filtered out by the loop filter. | 04-05-2012 |
20120081159 | METHOD USING DIGITAL PHASE-LOCKED LOOP CIRCUIT INCLUDING A PHASE DELAY QUANTIZER - A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power. | 04-05-2012 |
20120086482 | VOLTAGE-CONTROLLED OSCILLATOR MODULE HAVING ADJUSTABLE OSCILLATOR GAIN AND RELATED OPERATING METHODS - Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency. | 04-12-2012 |
20120086483 | OSCILLATOR CIRCUIT AND ELECTRIC-CURRENT CORRECTION METHOD - A PLL circuit includes a storage unit for storing a control voltage at a desired frequency obtained when a reference signal is synchronized with a referenced signal; a current generator circuit that includes a pull-up circuit and a pull-down circuit, each of which outputs an electric current at a predetermined timing; a voltage detecting unit that detects an output voltage corresponding to an electric current output by the current generator circuit; and a current control unit that changes a current value of at least one of the pull-up circuit and the pull-down circuit so that respective current values match each other, and controls the respective current values of the pull-up circuit and the pull-down circuit so that the output voltage detected by the voltage detecting unit matches the control voltage stored in the storage unit. | 04-12-2012 |
20120092048 | COMPENSATION OF PHASE LOCK LOOP (PLL) PHASE DISTRIBUTION CAUSED BY POWER AMPLIFIER RAMPING - Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances. | 04-19-2012 |
20120092049 | EQUALIZATION DEVICE, EQUALIZATION METHOD, AND PROGRAM - Provided is an equalization device which receives a signal transmitted from a transmission side of the signal as an input signal, and equalizes the deterioration of a wave shape of the received input signal, wherein a bit value indicated by the input signal is judged in accordance with a clock on the basis of the wave shape of the input signal. From judged signals which result from the judgment and which are composed of a plurality of bits, a two-bit transition signal is detected so that the two-bit transition signal has two adjacent bit values having the same value, and bit values located before and after the two adjacent bit values are different from the bit value of the two adjacent bit values, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal. | 04-19-2012 |
20120098578 | Phase-Locked Loop - A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensation signal in dependence on the output of the oscillator and a reference signal; a correlator configured to frequency correlate an interferer signal and the low frequency compensation signal, and in dependence on that correlation generate a correlation signal; and an adaptive filter configured to adapt the interferer signal in dependence on the correlation signal to output a high frequency compensation signal; and a summation unit configured to combine the low frequency compensation signal and the high frequency compensation signal to form a control signal to drive the input of the oscillator. | 04-26-2012 |
20120105114 | SPREAD SPECTRUM CLOCK GENERATING CIRCUIT - Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio. | 05-03-2012 |
20120105115 | CLOCK AND DATA RECOVERY CIRCUIT - A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal. | 05-03-2012 |
20120105116 | FREQUENCY SYNTHESIZER - There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency. | 05-03-2012 |
20120105117 | Phase-Lock Loop - A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency. | 05-03-2012 |
20120112807 | TEST AND MEASUREMENT INSTRUMENT WITH OSCILLATOR PHASE DEJITTER - A test and measurement instrument including an oscillator configured to generate a periodic signal; a mixer configured to mix an input signal with the periodic signal to generate a frequency-shifted signal; a trigger system configured to generate a trigger signal; a phase detector configured to sense a phase between the trigger signal and the periodic signal; and a controller configured to adjust processing of the frequency-shifted signal in response to the phase. | 05-10-2012 |
20120112808 | PHASE-LOCKED LOOP CIRCUIT - A gm-C VCO oscillates at a frequency that corresponds to an input control voltage. A divider divides the frequency of an oscillation signal output from the gm-C VCO. A phase comparison signal generating unit generates a phase difference signal that corresponds to the phase difference between the oscillation signal thus frequency-divided by the divider and a reference clock signal. A loop filter performs filtering of the phase difference signal so as to generate the control voltage. A startup circuit injects a seed pulse into the gm-C VCO at a timing determined based upon the level of a detection signal that corresponds to the control voltage. | 05-10-2012 |
20120119801 | Phase-Locked Loop - A phase-locked loop (PLL) including an active filter, a voltage-controlled oscillator (VCO), two phase detectors, a charge pump and a digital-to-analog converter (DAC) is provided. The VCO generates an oscillation signal according to a control signal provided at an output of the active filter. The first phase detector generates a phase difference signal according to a reference signal and a feedback signal associating with the oscillation signal. The charge pump provides a charging current to a first input of the active filter according to the phase difference. The second phase detector generates a digital reference signal according to the phase difference between the reference signal and the feedback signal. The DAC converts the digital reference signal to an analog reference voltage and provides the analog reference voltage to the second input of the active filter. | 05-17-2012 |
20120133402 | SEMICONDUCTOR DEVICE HAVING MULTIPLEXER - A semiconductor device includes: a DLL circuit that generates an internal clock signal based on an external clock signal; a clock dividing circuit that generates two complementary internal clock signals having different phases based on the internal clock signal; and a multiplexer that outputs two internal data signals in synchronization with the two clock signals based on internal data signals, respectively. An internal power supply voltage supplied to the clock dividing circuit and an internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device. This prevents interaction among noises. | 05-31-2012 |
20120133403 | TWO-POINT MODULATION DEVICE USING VOLTAGE CONTROLLED OSCILLATOR, AND CALIBRATION METHOD - Included are: a modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount. | 05-31-2012 |
20120139592 | Method and Apparatus for Frequency Synthesizing - Systems and methods for frequency synthesis are disclosed. Exemplary embodiments of the digital frequency synthesizer can produce a fixed frequency and/or a modulated signal. An exemplary digital frequency synthesizer includes series-coupled delay cells, a linear feedback shift register, and an accumulator. The series-coupled delay cells generate, from an input clock signal, multiple clock edges corresponding to fractional clock periods. A linear feedback shift register selects clock edges to pass to a combinational logic circuit, based on a sign/enable control signal received from an accumulator and a clock signal received from the combinational logic circuit's output. The accumulator receives a control signal and controls the phase of the synthesizer output based upon the received control signal. | 06-07-2012 |
20120139593 | CIRCUIT AND METHOD FOR RECEIVING SERIAL DATA AND SERIAL DATA TRANSMISSION SYSTEM AND METHOD USING THE SAME - A receiving circuit which receives serial data, includes: a voltage controlled oscillator which generates a sampling clock signal having a frequency based on an input control voltage; a first frequency divider which divides the frequency of the sampling clock signal at a division rate M; a second frequency divider which divides a frequency of a clock signal based on the received serial data at a division rate N, N being a real number represented by M×q/p; a frequency comparator which generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider; and a control voltage generating circuit which generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal. | 06-07-2012 |
20120139594 | METHOD AND APPARATUS FOR A TEMPERATURE COMPENSATED PHASE LOCKED LOOP SUPPORTING A CONTINUOUS STREAM RECEIVER IN AN INTEGRATED - An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load. | 06-07-2012 |
20120146691 | METHODS, ALGORITHMS, CIRCUITS, AND SYSTEMS FOR DETERMINING A REFERENCE CLOCK FREQUENCY AND/OR LOCKING A LOOP OSCILLATOR - Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies. | 06-14-2012 |
20120161829 | FREQUENCY LOCKED LOOP - A locked loop circuit includes an oscillator and an extrapolator. The oscillator generates an output signal in response to a control value. The extrapolator determines, based on a first state of the oscillator and a transfer function of the oscillator the control value for the oscillator to transition the oscillator to a second operating state. | 06-28-2012 |
20120161830 | DEVICE, SYSTEM AND METHOD OF CONFIGURABLE FREQUENCY SIGNAL GENERATION - Some demonstrative embodiments include devices, systems and/or methods of configurable frequency signal generation. For example, a device may include at least one configurable local-oscillator (LO) generator to receive an input frequency signal and one or more configurable input values and to convert the input frequency signal into at least one output frequency signal according to a configurable conversion ratio, which is based on the configurable input values. | 06-28-2012 |
20120161831 | DIGITAL PHASE LOCK LOOP - An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed. | 06-28-2012 |
20120161832 | FRACTIONAL DIGITAL PLL WITH ANALOG PHASE ERROR COMPENSATOR - Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator. | 06-28-2012 |
20120161833 | SEMICONDUCTOR DEVICE AND AUTOMOBILE CONTROL SYSTEM - Even after power-down, distinction between a transition from a PLL normal-oscillation state and a transition from a PLL self-oscillation is allowed. | 06-28-2012 |
20120161834 | DIGITAL PHASE LOCKED LOOP HAVING INSENSITIVE JITTER CHARACTERISTIC FOR OPERATING CIRCUMSTANCES - Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof. | 06-28-2012 |
20120169387 | OSCILLATOR WITH EXTERNAL VOLTAGE CONTROL AND INTERPOLATIVE DIVIDER IN THE OUTPUT PATH - An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter. | 07-05-2012 |
20120176169 | DIGITAL PHASE LOCKED LOOP WITH REDUCED SWITCHING NOISE - A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics. | 07-12-2012 |
20120176170 | DELAY LOCKED LOOP CIRCUIT FOR PREVENTING FAILURE OF COARSE LOCKING - A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. Accordingly, a failure of a coarse locking may be prevented thus facilitating improved circuit performance. | 07-12-2012 |
20120187986 | LATCH CIRCUIT, CDR CIRCUIT, AND RECEIVER - A receiving circuit that consumes less electric power is provided. The present invention provides a latch circuit that latches a differential signal by interrupting an electric current generated by a differential input using a corresponding differential output when the differential signal is differentially amplified. By using the latch circuit, transmitted data can be received even if the voltage difference of the differential signal components of the received signal is small. As a result, the number of amplifiers can be reduced, thereby enabling the power consumption of the receiver to be reduced. | 07-26-2012 |
20120187987 | STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal. | 07-26-2012 |
20120187988 | Signal Distribution Networks and Related Methods - A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit. | 07-26-2012 |
20120194233 | DEVICE CHARACTERISTIC COMPENSATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage. | 08-02-2012 |
20120194234 | APPARATUS FOR COMMUNICATING ANOTHER DEVICE - A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal. | 08-02-2012 |
20120194235 | HIGH-SPEED FREQUENCY DRIVER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 08-02-2012 |
20120194236 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO. | 08-02-2012 |
20120200324 | Frequency Offset Tracking and Jitter Reduction Method Using Dual Frequency-locked Loop and Phase-locked Loop - A method is provided for tracking large static or low-frequency frequency offset, such as SSC, in clock recovery of data communication or phase-locked loops based on a dual frequency-locked loop and phase-locked loop architecture. Instant PFD outputs are filtered to separate the phase errors due static/low-frequency frequency offset from the other phase mis-alignment. The static/low-frequency instant errors are used to drive a frequency-locked loop to track out static/low-frequency frequency offset completely. The phase-locked loop only needs to track the instant phase alignment other than the static/low-frequency frequency offset. Its gain or loop bandwidth does not need to be high so that the intrinsic jitter due to high gain or loop bandwidth can be avoided. | 08-09-2012 |
20120200325 | LOW JITTER CLOCK RECOVERY CIRCUIT - A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter. | 08-09-2012 |
20120200326 | Method and Apparatus for Reducing Signal Edge Jitter in an Output Signal from a Numerically Controlled Oscillator - A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal. | 08-09-2012 |
20120206176 | COARSE LOCK DETECTOR AND DELAY-LOCKED LOOP INCLUDING THE SAME - A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock. | 08-16-2012 |
20120206177 | DEVICE FOR GENERATING CLOCK SIGNALS FOR ASYMMETRIC COMPARISON OF PHASE ERRORS - A device for generating a clock signal, including a phase-locked loop including: a controlled oscillator to deliver a clock signal; plural phase comparators to compare a phase of the clock signal delivered by the controlled oscillator with plural clock signal phases applied at an input of the phase-locked loop; a mechanism for weighted summation of output signals of the plural phase comparators such that one or more of the weighting coefficients applied to one of the output signals has an absolute value that overrides the absolute values of the other weighting coefficients applied to the other output signals; and a mechanism filtering the weighted sum of the output signals of the plural phase comparators, to deliver at an output a control signal to the controlled oscillator. | 08-16-2012 |
20120212266 | ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE - The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation. | 08-23-2012 |
20120218013 | NONLINEAR AND CONCURRENT DIGITAL CONTROL FOR A HIGHLY DIGITAL PHASE-LOCKED LOOP - A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function. | 08-30-2012 |
20120218014 | Methods and Devices for Multiple-Mode Radio Frequency Synthesizers - Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively. | 08-30-2012 |
20120223751 | Generating an Oscillator Signal Having a Desired Frequency in a Continuous Frequency Range - A method of generating a first oscillator signal having a desired frequency in a first frequency range comprises generating in a voltage controlled oscillator unit a second oscillator signal having a frequency in a second frequency range of at least one octave. The method further comprises selecting said second continuous frequency range to have a lower endpoint in said first frequency range and an upper endpoint above said range; and selectively using the oscillator signal unchanged or dividing it by a division ratio selected from integer powers of the number 2 to obtain said first oscillator signal. By centering the VCO higher than otherwise required and using an additional divider, so that the VCO signal can selectively be used unchanged or divided, a sufficient margin below as well as above the desired range for e.g. drift and tolerances of the VCO is achieved. It also simplifies the VCO design. | 09-06-2012 |
20120235717 | SPREAD SPECTRUM CLOCK GENERATOR - A spread spectrum clock generator includes a phase comparator to detect a phase difference between a reference input clock signal and a feedback signal and output a control voltage, a voltage controlled oscillator to generate an output clock signal with a frequency in line with the control voltage, a phase selector to select any of equally divided phases of one cycle of the output clock signal, generate and transmit a phase shift clock signal to the phase comparator as the feedback signal, and a phase controller to decide a phase of the rising edge of the phase shift clock signal and control the phase selector to select the decided phase, and generate a second phase shift amount, decide the rising edge of the phase shift clock signal to and subject the output clock signal to spread spectrum modulation by the second phase shift amount. | 09-20-2012 |
20120242383 | PHASE PROFILE GENERATOR - Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile. | 09-27-2012 |
20120249195 | CLOCK GENERATING APPARATUS AND FREQUENCY CALIBRATING METHOD OF THE CLOCK GENERATING APPARATUS - A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency. | 10-04-2012 |
20120249196 | SIGNAL GENERATING DEVICE AND FREQUENCY SYNTHESIZER - A frequency synthesizer using a PLL has a simple structure and excellent spurious characteristics. A reference frequency signal inputted into a phase comparison unit is generated based on a clock when a zero cross point of a sawtooth wave composed of a digital signal is detected. However, in this case, since the digital values are skipped values, the digital value does not always become zero when its positive/negative sign is inverted. Hence, where the clock signals reading the digital value immediately before and the to digital value immediately after the zero cross time when the positive/negative sign is inverted in a region where the digital value gradually changes are P | 10-04-2012 |
20120249197 | Large signal VCO - An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network. | 10-04-2012 |
20120256665 | DELAY LOCK LOOP WITH A CHARGE PUMP, LOOP FILTER, AND METHOD OF PHASE LOCKING OF A DELAY LOCK LOOP - A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter. | 10-11-2012 |
20120262208 | FAULT TOLERANT REDUNDANT CLOCK CIRCUIT - A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives. | 10-18-2012 |
20120268177 | FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER - A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO. | 10-25-2012 |
20120274370 | Reducing Spurs in Injection-Locked Oscillators - Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms. | 11-01-2012 |
20120274371 | METHOD FOR ENCODER FREQUENCY SHIFT COMPENSATION - The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input encoder signal to determine values of frequency-shifts and compensating for the values of the frequency-shifts to generate a frequency-shift compensated clock. | 11-01-2012 |
20120280729 | ADAPTIVE DIGITAL PHASE LOCKED LOOP - In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error. | 11-08-2012 |
20120286834 | PHASE LOCKED LOOP - A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal. | 11-15-2012 |
20120286835 | PLL CIRCUIT - A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as a digital value; a selector configured to select either the digital value or a fixed value; a digitally controlled oscillator configured to oscillate at a frequency corresponding to the value selected by the selector; and a control section configured to instruct the selector to select the fixed value until receiving a start signal, and after receiving the start signal, instruct the selector to select the digital value, and the frequency division section to start output, at timing of an edge of the reference clock signal. | 11-15-2012 |
20120293221 | DELAY LOCK LOOP AND DELAY LOCK METHOD - A delay lock loop comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, selectively detecting phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result; and a delay control circuit, for generating a first and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop. | 11-22-2012 |
20120293222 | PLL CIRCUIT - A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop. | 11-22-2012 |
20120313676 | HYBRID DIGITAL-ANALOG PHASE LOCKED LOOPS - A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine. | 12-13-2012 |
20120313677 | PHASE LOCKED LOOP - A phase locked loop ( | 12-13-2012 |
20120313678 | DIGITAL FREQUENCY LOCKED LOOP - Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage. | 12-13-2012 |
20120326758 | FREQUENCY SYNTHESIS DEVICE WITH FEEDBACK LOOP - A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit. | 12-27-2012 |
20130002317 | DIGITAL PHASE LOCKED LOOP CIRCUITS WITH MULTIPLE DIGITAL FEEDBACK LOOPS - Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals. | 01-03-2013 |
20130002318 | WIDE-RANGE CLOCK MULTIPLIER - A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies | 01-03-2013 |
20130009680 | TEMPERATURE COMPENSATION CIRCUIT AND SYNTHESIZER USING THE TEMPERATURE COMPENSATION CIRCUIT - A temperature compensation circuit includes: a sensing circuit arranged to sense a temperature to generate a sensing signal; an operational circuit arranged to sample the sensing signal to generate a sample signal during a first phase, and arranged to generate an output signal according to the sensing signal and the sample signal during a second phase; and a capacitive circuit arranged to provide a capacitance adjusted by the output signal. | 01-10-2013 |
20130009681 | ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE - The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation. | 01-10-2013 |
20130009682 | FREQUENCY AND PHASE ACQUISITION OF A CLOCK AND DATA RECOVERY CIRCUIT WITHOUT AN EXTERNAL REFERENCE CLOCK - A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics. | 01-10-2013 |
20130015894 | DIFFERENTIAL RING OSCILLATOR-TYPE VOLTAGE CONTROL OSCILLATORAANM KOUYAMA; KunihikoAACI Yokohama-shiAACO JPAAGP KOUYAMA; Kunihiko Yokohama-shi JP - A voltage control oscillator according to the present invention includes: a voltage-current converter circuit that converts an inputted voltage to a current according to the value of the voltage; a current mirror circuit; a ring oscillator including differential inverters connected in multiple stages; an inverting amplifier; and a buffer. The ring oscillator outputs, from each of the differential inverters, a signal amplitude-limited by a “current converted by the voltage-current converter circuit and the current mirror circuit” and a “voltage applied from the inverting amplifier” and the ring oscillator outputs an oscillatory frequency in response to the output signal. | 01-17-2013 |
20130015895 | TEMPERATURE COMPENSATION CIRCUITAANM Nguyen; Darin DungAACI PhoenixAAST AZAACO USAAGP Nguyen; Darin Dung Phoenix AZ US - A temperature compensation circuit is disclosed. A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal is negatively-proportional-to-absolute-temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature. | 01-17-2013 |
20130015896 | PHASE-LOCKED LOOP APPARATUS AND TUNING VOLTAGE PROVIDING CIRCUIT THEREOFAANM Li; Hsiang-ChiAACI Hsinchu CityAACO TWAAGP Li; Hsiang-Chi Hsinchu City TW - A phase-locked loop apparatus (PLL apparatus) and a tuning voltage providing circuit thereof are provided. The PLL apparatus is for receiving an input signal and producing an output signal according to the received input signal. The PLL apparatus includes a voltage-controlled oscillator (VCO), a loop filter and a tuning voltage providing circuit. The VCO receives a control voltage and produces the output signal according to the received control voltage. The loop filter has a resistor-capacitor network and the network receives the control voltage and is coupled to a reference voltage. The tuning voltage providing circuit receives the output signal and the input signal and provides a tuning voltage to the resistor-capacitor network according to the input signal and the output signal. | 01-17-2013 |
20130027096 | System Including Circuitry For Controlling A Characteristic of a Periodic Signal and Method for Adjusting a Signal - System and circuitry controlling characteristics of periodic signals. In one embodiment adjustment circuitry modifies periodic signal characteristic. A phase detector generates analog input signals indicative of a phase difference between the periodic signal and a reference signal. Conversion circuitry translates the analog input signals into digital signals. Signal driving circuitry, comprising a current source, provides control signals to the signal driving circuitry based on the digital signals. First input circuitry provides a first adjustment signal to the adjustment circuitry. Second input circuitry provides a second adjustment signal to the adjustment circuitry in response to the control signal. The first adjustment signal is based on input of analog signals to a circuit element in the first input circuitry to control the first adjustment signal. The second input circuitry is responsive to the control signal to provide the second adjustment signal with the digital version of the input signals. | 01-31-2013 |
20130027097 | System Including Circuitry Providing Multiple Circuit Paths For Controlling A Characteristic of A Period Signal - System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference. | 01-31-2013 |
20130027098 | System and Method Providing Bandwidth Adjustment In Integral Path of Phase Locked Loop Circuitry - A system incorporating and method of operating phase locked loop circuitry. In one embodiment, having programmable circuitry for adjustment of loop dynamics, a VCO has a first input terminal for selecting phase and frequency characteristics of an output signal and an output terminal on which the output signal is provided. A detector generates first VCO input signals indicative of phase and frequency differences between the VCO output signal and a reference signal. Circuitry digitizes the first VCO input signals and generates an integral path input signal therefrom. Slow integral path circuitry comprising, a first transistor device and a programmable low pass filter: receives the integral path input signal, and provides a low pass filtered version of the integral path input signal to control conduction through the first transistor device and provide a first adjustment signal for adjustment of the frequency of the VCO output signal. | 01-31-2013 |
20130027099 | System, Method and Emulation Circuitry Useful For Adjusting a Characteristic of A Periodic Signal - Systems, methods and circuitry useful for adjusting a periodic signal such as with a voltage controlled oscillator or a delay line. In one series of embodiments, circuits and methods are provided for controlling current flow through first and second parallel paths where an impedance device in one path emulates the impedance characteristics of a different device in the other path. A phase or frequency characteristic of the periodic signal may be adjusted by alternate switching of current through the two paths. | 01-31-2013 |
20130027100 | System and Method for Adjusting a Characteristic of A Periodic Signal with Use of a Filtered Bias Voltage - Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal. | 01-31-2013 |
20130033293 | PHASE LOCKED LOOP WITH PHASE CORRECTION IN THE FEEDBACK LOOP - A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter coupled to the comparator circuit. The frequency synthesizer circuit also includes an oscillator coupled to the loop filter. The frequency synthesizer circuit also includes a fractional divider coupled to an output of the oscillator. The frequency synthesizer circuit also includes phase correction circuitry that corrects a phase of an output of the fractional divider to produce the phase-corrected output signal. | 02-07-2013 |
20130038364 | OSCILLATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals. | 02-14-2013 |
20130049829 | VARIABLE DELAY LINE FOR DELAY LOCKED LOOP - In a multi-stage switching-type delay circuit, occurrence of a hazard is inhibited at the time of the switching of the number of stages. With the multi-stage switching-type delay circuit, an input IN of the delay circuit is connected to a stage that is not selected as a path for causing a delay in order to prevent a logic state of each of the internal nodes of the delay circuit from being changed between before and after the switching of the number of stages. | 02-28-2013 |
20130057327 | REDUCING PHASE LOCKED LOOP PHASE LOCK TIME - There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected. | 03-07-2013 |
20130063191 | Methods and Circuits for Duty-Cycle Correction - A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle. | 03-14-2013 |
20130069699 | Microwave Synthesizer - A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer. | 03-21-2013 |
20130076412 | CDR CIRCUIT - When the comparison result signal indicates that the amplitude of the received data signal in synchronization with the data sampling clock signal is larger than the reference voltage, the lock detecting circuit determines that a lock condition occurs in which the data sampling clock signal locks the phase of the data of the received data signal, and outputs a lock flag signal. | 03-28-2013 |
20130076413 | SEMICONDUCTOR DEVICE INCLUDING DLL CIRCUIT HAVING COARSE ADJUSTMENT UNIT AND FINE ADJUSTMENT UNIT - Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system. | 03-28-2013 |
20130082752 | RESISTOR LADDER BASED PHASE INTERPOLATION - An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal. | 04-04-2013 |
20130082753 | APPLICATION OF PHASE-LOCKED LOOP (PLL) IN OSCILLATION MONITORING FOR INTERCONNECTED POWER SYSTEMS - The present invention relates to a method for accurately detecting oscillations and improving stability of power systems. The method includes the steps of providing a phase-locked loop having a phase detector, a loop filter, and a number-controlled oscillator. The method further includes the steps of extracting an input signal from the power system, using the phase-locked loop to track the frequency and phase of a targeted mode in the input signal, and creating a locally generated reference signal to fit the input signal and to allow the input signal's modal information to be obtained. The method further includes the step of performing mode shape analysis utilizing the reference phase signals constructed from the tracked frequencies. | 04-04-2013 |
20130088269 | IMPLEMENTING CONTROL VOLTAGE MIRROR - A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization. | 04-11-2013 |
20130088270 | METHOD AND APPARATUS FOR DETERMINING DUTY CYCLE OF A CLOCK IN A CIRCUIT USING A CONFIGURABLE PHASE LOCKED LOOP - An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples. | 04-11-2013 |
20130088271 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a clock period reflector configured to reflect time corresponding to period information of an internal clock signal to an input data signal, a data-clock converter configured to generate a synchronization clock signal having phases corresponding to an output signal of the clock period reflector, and a synchronization output unit configured to synchronize and output the input data signal in response to the synchronization clock signal. | 04-11-2013 |
20130093477 | SYSTEMS AND METHODS FOR GENERATING A HIGH FREQUENCY LOCAL OSCILLATOR SIGNAL - One embodiment of the present invention relates to a system that provides a high frequency local oscillator (LO) signal. The system comprises a first LO that generates a first frequency LO signal component, a mixer that generates a difference signal from the first frequency LO signal component and a second frequency LO signal component, and a second LO that generates the second frequency LO signal component that is a harmonic of the difference signal. | 04-18-2013 |
20130093478 | DIFFERENTIATOR BASED SPREAD SPECTRUM MODULATOR - A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal. | 04-18-2013 |
20130093479 | SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION TERMINAL MOUNTING THE SAME - A phase detector, which forms a semiconductor device, detects a phase difference between a reference signal and a feedback signal obtained by feeding back an output signal of an oscillator, and generates a phase difference value indicating a value in accordance with the phase difference. An amplifier amplifies the phase difference value at a gain determined in accordance with a control signal from outside the device. A filter smoothes an output value of the amplifier. The oscillator controls a frequency of the output signal in accordance with an output value of the filter. | 04-18-2013 |
20130093480 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 04-18-2013 |
20130106476 | TEMPERATURE COMPENSATION IN A PLL | 05-02-2013 |
20130106477 | Method for control of phase in an oscillatory circuit | 05-02-2013 |
20130120035 | LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP - A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods. | 05-16-2013 |
20130120036 | APPARATUS AND METHOD FOR RECOVERING BURST-MODE PULSE WIDTH MODULATION (PWM) AND NON-RETURN-TO-ZERO (NRZ) DATA - A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits. | 05-16-2013 |
20130120037 | Agile Clocking with Receiver PLL Management - A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface. | 05-16-2013 |
20130120038 | Phase-Locked-Loop with Quadrature Tracking Filter for Synchronizing an Electric Grid - Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications. A frequency estimator estimates the grid frequency of the electric grid and outputs the estimated frequency to the QTF algorithms. The frequency estimator may include a three-phase phase-locked-loop (three-phase PLL) suitable for estimating the center frequencies of multiple phases of the electric grid. The frequency estimator may also include means for reducing the harmonics in the grid system. | 05-16-2013 |
20130120039 | Phase-Locked-Loop with Quadrature Tracking Filter for Synchronizing an Electric Grid - Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the second state of either of the two QTF transformations may be either positive or negative. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications. | 05-16-2013 |
20130147529 | NEAR-INTEGER CHANNEL SPUR MITIGATION IN A PHASE-LOCKED LOOP - A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop. | 06-13-2013 |
20130154694 | PHASE-LOCKED LOOP FREQUENCY STEPPING - A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division. | 06-20-2013 |
20130162309 | RECEIVING CIRCUIT - Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit. | 06-27-2013 |
20130169327 | Charge-to-Digital Timer - The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load. | 07-04-2013 |
20130169328 | CDR CIRCUIT, RECEPTION CIRCUIT, AND ELECTRONIC DEVICE - An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals. | 07-04-2013 |
20130181755 | SYNCHRONIZATION METHOD FOR CURRENT DIFFERENTIAL PROTECTION - A synchronization method for current differential protection comprises: selecting a point on the transmission line protected by the current differential protection; measuring the current and the voltage of each of the terminals of said transmission line; calculating the compensating voltage at the selected point respectively according to the measured current and the voltage of the each terminal; detecting and calculating the synchronization error by comparing all the compensating voltages. | 07-18-2013 |
20130187688 | POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF - A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result. | 07-25-2013 |
20130214829 | CLOCK RECOVERY SYSTEM - In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator. | 08-22-2013 |
20130214830 | APPARATUS AND METHOD FOR PHASE LOCKED LOOP BANDWIDTH EXPANSION - An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response. | 08-22-2013 |
20130214831 | CIRCUIT FOR DETECTING A VOLTAGE CHANGE USING A TIME-TO-DIGITAL CONVERTER - A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal. | 08-22-2013 |
20130214832 | Apparatus to Remove the Loop Filter Resistor Noise in Charge-Pump PLL - An improved charge pump based phase locked loop where the loop filter resistor noise is reduced by about an order is presented. The voltage controlled oscillator generates a clock signal, and this is input to the phase detector, which, compares the oscillator clock with the reference clock and using the Charge pump it generates a current output proportional to the phase difference. The loop filter converts this proportional current to a voltage and connects it to the oscillator input. The loop filter consists of a capacitor, resistor and the apparatus that bypasses most of the resistor noise. | 08-22-2013 |
20130214833 | DATA OUTPUT TIMING CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS - A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal. | 08-22-2013 |
20130214834 | Phase-Locked Loop Control Voltage Determination - A method and circuit is provided for determining a control voltage of a voltage controlled oscillator with fast frequency lock of a phase-locked loop and which is advantageous to the situation when an ultra-low frequency reference is used. The method and circuit determines a current error between a reference clock signal and a feedback clock signal, and checks if the error is larger than the threshold value which checks if an error sign indicator is set, i.e. the error has switched sign since startup of feedback loop; if the error sign indicator is not set, the circuit determines a divisor, k | 08-22-2013 |
20130222023 | DIGITAL PHASE LOCK LOOP AND METHOD THEREOF - An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code. | 08-29-2013 |
20130229212 | PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION - A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed. | 09-05-2013 |
20130241610 | PLL CIRCUIT, METHOD OF CONTROLLING PLL CIRCUIT, AND DIGITAL CIRCUIT - A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value. | 09-19-2013 |
20130241611 | FREQUENCY GENERATOR FOR RADIOFREQUENCY EQUIPMENT AND METHOD FOR GENERATING AN OUTPUT SIGNAL - A frequency generator generating an output signal having a predetermined output frequency, including: a local oscillator generating a reference signal having a reference frequency, and a phase-locked loop, the phase-locked loop provided with a controlled oscillator generating the output signal having the output frequency as a function of the signal at its input, and a comparator providing a signal to the controlled oscillator as a function of a phase and/or frequency comparison of a first comparison signal based on an input signal applied to a first input of the phase-locked loop with a second comparison signal based on the output signal, the frequency generator further including at least one harmonic generator generating, from the reference signal, a harmonic signal including a predetermined harmonic of the reference signal, the frequency generator applying the harmonic signal of one of the harmonic generators to the first input of the phase-locked loop. | 09-19-2013 |
20130249609 | SEMICONDUCTOR INTEGRATED CIRCUIT - An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example. | 09-26-2013 |
20130257494 | Systems, Circuits, and Methods for a Sigma-Delta Based Time to Digital Converter - Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal. | 10-03-2013 |
20130257495 | LOOP FILTER - A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter. | 10-03-2013 |
20130278308 | METHODS AND SYSTEMS FOR CONTROLLING A POWER CONVERTER - A stabilizer system associated with a power converter controller is described. The stabilizer system includes a regulator stabilizer configured to receive a phase locked loop (PLL) error signal and to generate a regulator stabilization signal based at least partially on the PLL error signal. The stabilizer system also includes a regulator coupled to the regulator stabilizer and a converter interface controller. The regulator is configured to receive the regulator stabilization signal, generate a first command signal, based at least partially on the regulator stabilization signal, that reduces system oscillations, and transmit the first command signal to the converter interface controller. | 10-24-2013 |
20130278309 | SEMICONDUCTOR WAFER AND METHOD FOR AUTO-CALIBRATING INTEGRATED CIRCUIT CHIPS USING PLL AT WAFER LEVEL - In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete. | 10-24-2013 |
20130278310 | DEVICE INCLUDING A CLOCK GENERATION CIRCUIT AND A METHOD OF GENERATING A CLOCK SIGNAL - A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit. | 10-24-2013 |
20130285720 | MULTIPLE CHANNEL PHASE DETECTION - A signal processing device to utilize multiple channel phase detection includes a first phase detector for a first Phase Locked Loop (PLL) of a first channel, the first phase detector to generate phase error information from an input of the first channel. The device also includes a second phase detector of a second PLL of a second channel, the second phase detector to generate phase error information from an input of the second channel. Both the first PLL and the second PLL are to receive phase error information from both the first phase detector and the second phase detector. | 10-31-2013 |
20130300467 | HIGHER-ORDER PHASE NOISE MODULATOR TO REDUCE SPURS AND QUANTIZATION NOISE - A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function. | 11-14-2013 |
20130300468 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped. | 11-14-2013 |
20130321047 | DISTORTION TOLERANT CLOCK AND DATA RECOVERY - A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal. | 12-05-2013 |
20130321048 | COMMON REFERENCE CRYSTAL SYSTEMS - One embodiment of communication system comprises a crystal oscillator configured to output a reference clock; cellular radio frequency (RF) and baseband phase locked loops configured to receive the reference clock within a cellular module and compensate for calculated frequency errors between a received cellular downlink signal and a cellular local oscillator signal during operation of the cellular module; global positioning system (GPS) frequency compensation circuitry configured to receive the reference clock within a GPS module and compensate for calculated frequency errors during operation of the GPS module; and a temperature sensing circuit which includes a plurality of sensing resistors and is configured to output a signal corresponding to a temperature of a reference crystal which is translated to a frequency deviation, wherein the (GPS) frequency compensation circuitry is configured to offset the frequency deviation and output a temperate compensated signal to meet GPS clock frequency requirements. | 12-05-2013 |
20130321049 | SMART CARD CLOCK GENERATOR CIRCUITS WTH AUTONOMOUS OPERATION CAPABILITY AND METHOD OF OPERATING THE SAME - An apparatus includes a reference clock signal generator circuit configured to generate a reference clock signal in response to a carrier signal and a clock selection signal generator circuit configured to generate a clock selection signal in response to the carrier signal. The apparatus further includes a multiplexer (MUX) circuit configured to selectively output the reference clock signal and a PLL output clock signal in response to the clock selection signal and a phase-locked loop (PLL) circuit configured to receive the selectively output signal between the reference clock signal and the PLL output clock signal at a reference input thereof and to generate the PLL output clock signal therefrom. An ISO 14443 type A smart card may include such apparatus. | 12-05-2013 |
20130328602 | DUTY RATIO CORRECTION CIRCUIT, DOUBLE-EDGED DEVICE, AND METHOD OF CORRECTING DUTY RATIO - A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. | 12-12-2013 |
20140002150 | PHASE DETECTION CIRCUIT AND SYNCHRONIZATION CIRCUIT USING THE SAME | 01-02-2014 |
20140002151 | FRACTIONAL PLL CIRCUIT | 01-02-2014 |
20140009194 | PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS - In one embodiment, a phase locked loop (PLL) circuit in a device includes selectable feedback paths and a multiplexer. An internal feedback path is adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of the device and an external feedback path is adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device. The multiplexer is provided for selecting between the internal and external feedback paths. | 01-09-2014 |
20140015574 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a reference clock signal in response to a second delay amount tracked using a first delay amount as an initial delay amount, and track the second delay amount again by adjusting the first delay amount in response to a reset signal, and a DLL controller configured to activate the reset signal when the second delay amount deviates from a given range. | 01-16-2014 |
20140015575 | SYNCHRONOUS SEMICONDUCTOR DEVICE HAVING DELAY LOCKED LOOP FOR LATENCY CONTROL - A synchronous semiconductor device includes an internal command generation unit configured to generate an internal command corresponding to a source command, a delay locked loop configured to delay a source clock by a first delay time required for delay-locking to generate a delay locked clock, a delay time determination unit configured to determine a second delay time for delay-locking the internal command using the source clock, the second delay time being determined by reflecting a third delay time generated on a command path, and a latency control unit configured to shift the internal command by a shifting period, in which the second delay time is reflected, in response to the delay locked clock. | 01-16-2014 |
20140015576 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop. | 01-16-2014 |
20140021986 | SYNTHESIZER METHOD UTILIZING VARIABLE FREQUENCY COMB LINES AND FREQUENCY TOGGLING - A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency. | 01-23-2014 |
20140021987 | INJECTION-LOCKED-TYPE FREQUENCY-LOCKED OSCILLATOR - Provided is an injection-locked-type frequency-locked oscillator capable of stable operation and exhibiting low phase noise. This injection-locked-type frequency-locked oscillator comprises: a locked loop ( | 01-23-2014 |
20140035637 | REFERENCE CLOCK COMPENSATION FOR FRACTIONAL-N PHASE LOCK LOOPS (PLLS) - In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity. | 02-06-2014 |
20140035638 | SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION - A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal. | 02-06-2014 |
20140043074 | Frequency Tuning Based on Characterization of an Oscillator - Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. In this regard, a frequency of an oscillator in an integrated circuit may be controlled based on a first digital control word, a frequency of a tuned circuit may be controlled based on a second digital control word, and the second control word may be determined utilizing a mapping between the first control word and the second control word. The frequency of the oscillator and the tuned circuit may be controlled by adjusting a capacitance of the oscillator and tuned circuit, respectively. The mapping may be based on a relationship between the oscillator and the tuned circuit, such as logical and/or mathematical relationship between the capacitance of the oscillator and the capacitance of the tuned circuit and/or the relationship between the frequency of the oscillator and the frequency of the tuned circuit. | 02-13-2014 |
20140055179 | INTERPOLATIVE DIVIDER LINEARITY ENHANCEMENT TECHNIQUES - A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal. | 02-27-2014 |
20140055180 | DISTRIBUTED RESONATE CLOCK DRIVER - A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards. | 02-27-2014 |
20140055181 | CLOCK GENERATING CIRCUIT - A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal. | 02-27-2014 |
20140055182 | POWER CONTROL SYSTEM AND METHOD - A system and method for controlling an electrical device is provided. The method comprises receiving three phase power from a source, decomposing signals representative of power in each phase of the three phase power to provide a positive-sequence component of each phase and tracking the positive-sequence component of each phase via a phase locked loop and a tracking filter. | 02-27-2014 |
20140062549 | DIGITAL PLL WITH DYNAMIC LOOP GAIN CONTROL - The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which dynamically generates loop-filter parameters for the digital loop filter based on an observed pattern of up/down values from the phase-detector output over a specified period of time. A digitally controlled oscillator (DCO) receives the loop-filter output signal and produces a PLL output signal. Finally, a feedback path returns the PLL output signal to the phase detector. | 03-06-2014 |
20140070857 | MULTI-PHASE FRACTIONAL DIVIDER - Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider. | 03-13-2014 |
20140070858 | SIGNAL TRANSMISSION CIRCUIT - A clock generation circuit | 03-13-2014 |
20140077849 | PHASE-LOCKED LOOP WITH LOOP GAIN CALIBRATION, GAIN MEASUREMENT METHOD, GAIN CALIBRATION METHOD AND JITTER MEASUREMENT METHOD FOR PHASE-LOCKED LOOP - The invention provides a phase-locked loop with loop gain calibration and methods for measuring an oscillator gain, gain calibration and jitter measurement for a phase-locked loop. The method for measuring an oscillator gain of a phase-locked loop includes the steps of providing a varying code at an input end of the oscillator; outputting excess reference phase information by a reference phase integral path and outputting excess feedback phase information based on the varying code by a feedback phase integral path; and obtaining an estimated gain information of the oscillator based on the excess reference phase information and the excess feedback phase information. | 03-20-2014 |
20140084975 | VOLTAGE TRANSLATION CIRCUIT - A voltage translation circuit ( | 03-27-2014 |
20140097878 | SERIALIZER-DESERIALIZER CLOCK AND DATA RECOVERY GAIN ADJUSTMENT - In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain, change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve. | 04-10-2014 |
20140097879 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 04-10-2014 |
20140103973 | SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE - Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system. | 04-17-2014 |
20140103974 | Synchronization Signal Processing Method and Apparatus - The present invention provides a synchronization signal processing method and apparatus, which solves problems of low accuracy and a slow speed of synchronization operation executed on the synchronization signal. The specific steps include: acquiring multiple to-be-processed signals of a power supply, where the to-be-processed signals are signals changing periodically; generating a synchronization signal that has the same period as the to-be-processed signals by generating pulses in each period of the to-be-processed signals, where each period of the synchronization signal includes at least two pulses; detecting whether the synchronization signal is normal by determining whether parameters of all the pulses in the synchronization signal are accurate; and if the synchronization signal is normal, synchronizing the to-be-processed signals by performing time alignment on the pulses in the synchronization signal. The synchronization signal processing method and apparatus can be applied in a synchronization operation between signals. | 04-17-2014 |
20140132318 | PLL LOCKING CONTROL IN DAISY CHAINED MEMORY SYSTEM - A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller. | 05-15-2014 |
20140152358 | SEMICONDUCTOR APPARATUS AND DUTY CYCLE CORRECTION METHOD THEREOF - A semiconductor apparatus includes a duty cycle correction block and a delay locked loop. The duty cycle correction block generates a duty corrected clock by correcting a duty cycle of an internal clock, adjusts a phase of a rising edge of the duty corrected clock when a delay locked loop is reset, and adjusts a phase of a falling edge of the duty corrected clock when the delay locked loop is locked. The delay locked loop receives an external clock to output the internal clock, and delays the external clock by a variable delay amount to output the internal clock when the adjustment of the phase of the rising edge of the duty corrected clock by the duty cycle correction block is completed. | 06-05-2014 |
20140159787 | SPREAD-SPECTRUM CLOCK GENERATOR - A spread-spectrum clock generator includes a frequency comparator, for generating a compensation signal according to a reference signal and a frequency signal corresponding to an output frequency signal; a triangle-wave generator, for generating a triangle-wave signal according to a frequency control signal; an adder, coupled between the triangle-wave generator and the frequency comparator, for adding the compensation signal to the triangle-wave signal to generate an addition result; and a frequency synthesizer, coupled between the frequency comparator and the adder, for generating the output frequency signal to adjust the output frequency signal according to the addition result so as to reduce a shift of the output frequency signal. | 06-12-2014 |
20140159788 | SIGNAL PROCESSING APPARATUS AND ASSOCIATED METHOD - A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal. | 06-12-2014 |
20140176204 | Phase locked loop system and working method thereof - A PLL system includes: an input end; an output end; a first PFD; a first CHP connected to the first PFD; a first LPF connected to the first CHP; a first VCO connected to the first CHP and the first LPF; a second PFD connected to the first VCO; a second CHP connected to the second PFD; a second LPF connected to the second CHP; a second VCO connected to the second CHP and the second LPF; a first DIV connected to the first PFD and the second VCO; and a second DIV connected to the second PFD and the second VCO. A working method of the PLL system is also provided, which can restrain input noise as well as phase noise of the second VOC in such a manner that noise of the PLL system is well restrained. | 06-26-2014 |
20140176205 | SIGNAL CONVERSION CIRCUIT, PLL CIRCUIT, DELAY ADJUSTMENT CIRCUIT, AND PHASE CONTROL CIRCUIT - A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC | 06-26-2014 |
20140184289 | METHOD AND APPARATUS FOR SINGLE PORT MODULATION USING A FRACTIONAL-N MODULATOR - A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth. | 07-03-2014 |
20140184290 | Translational Phase Lock Loop and Synthesizer That Eliminates Dividers - This invention describes a method by which a low cost low phase noise Phase Locked Loop or Phase Locked Loop based Frequency Synthesizer can be realized. The new method, called a Translational Phase Lock Loop or TPLL, allows the conversion of a traditional voltage controlled oscillator or VCO signal so that the phase noise of the VCO signal is substantially identical to the noise that the loop is aimed to correct via comparison to a low noise reference oscillator. It overcomes additional problems associated with traditional and prior art phase lock loops in terms of unwanted spurious signals, complexity, and cost. | 07-03-2014 |
20140184291 | CIRCUIT FOR CONTROLLING VARIATION IN FREQUENCY OF CLOCK SIGNAL - Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked. | 07-03-2014 |
20140210527 | INDUCTION-COUPLED CLOCK DISTRIBUTION FOR AN INTEGRATED CIRCUIT - An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package. | 07-31-2014 |
20140210528 | PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC) - One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal. | 07-31-2014 |
20140240012 | REFERENCE CLOCK COMPENSATION FOR FRACTIONAL-N PHASE LOCK LOOPS (PLLS) - In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity. | 08-28-2014 |
20140247075 | INTERFACE CIRCUIT FOR SIGNAL TRANSMISSION - An interface circuit for signal transmission includes an amplifying circuit, a de-skew circuit and a latching unit. The amplifying circuit receives an input clock signal and outputs an output clock signal after amplifying the input clock signal. The de-skew circuit receives the output clock signal and outputs a de-skew clock signal as a trigger signal after removing a skew time of the output clock signal. The latching unit includes multiple sampling circuits, respectively receives multiple inputting data signals. The sampling circuits are controlled by the trigger signal to sample the inputting data signals and output multiple outputting data signals. The voltage amplitudes of the outputting data signals are larger than the voltage amplitudes of the inputting data signals and satisfy a required voltage amplitude by a subsequent circuit. | 09-04-2014 |
20140266339 | METHOD AND APPARATUS FOR GAPPING - Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider. | 09-18-2014 |
20140266340 | INTEGRATED CLOCK DIFFERENTIAL BUFFERING - Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal. | 09-18-2014 |
20140266341 | DIGITAL PHASE-LOCKED LOOP USING PHASE-TO-DIGITAL CONVERTER, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME - A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code. | 09-18-2014 |
20140266342 | HIGH-FREQUENCY SIGNAL PROCESSING DEVICE - A high-frequency signal processing device having a frequency synthesizer (PLL: Phase Locked Loop) is provided. A control circuit measures oscillation frequencies obtained upon setting a bias current of an oscillation circuit to first and second bias setting values and acquires a frequency difference amount of the oscillation frequencies. The frequency difference amount may be acquired as difference amount of setting values of a coarse adjustment capacitance setting signal (CTRM) using, for example, an automatic frequency selector unit. The control circuit retains a relationship of a difference amount of bias setting values and a difference value of setting values of the CTRM and approximating the relationship to a linear function. Thereafter, the control circuit defines, upon switching the bias current during locking of the PLL, the CTRM based on the linear function and switches the CTRM together with the bias current. | 09-18-2014 |
20140292386 | CLOCK GENERATION DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, AND CLOCK GENERATION METHOD - A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+α (α is zero or a positive number)) is input and some clocks of the clock signal are masked. | 10-02-2014 |
20140312943 | PHASE-LOCKED LOOP DEVICE WITH MANAGED TRANSITION TO RANDOM NOISE OPERATION MODE - A phase-locked loop device is configured to manage a transition from a relaxation-oscillation mode to a random noise operation mode. It is designed for progressively reducing proportional and integral coefficients that are implemented in a loop filter of the PLL device. Recovering the last values formerly used for the proportional and integral coefficients is also provided, in case the PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator within the PLL device, which has several control inputs. | 10-23-2014 |
20140320181 | PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS - A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference. | 10-30-2014 |
20140320182 | GEOGRAPHIC LOCATING REMOTE ENDPOINT MONITOR DEVICE, SYSTEM, AND METHODOLOGY THEREOF - A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal. | 10-30-2014 |
20140327477 | PHASE LOCKED LOOP SYSTEM WITH BANDWIDTH MEASUREMENT AND CALIBRATION - A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times. | 11-06-2014 |
20140333351 | AUTOMATIC LOOP-BANDWIDTH CALIBRATION FOR A DIGITAL PHASED-LOCKED LOOP - A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided. | 11-13-2014 |
20140333352 | SYSTEMS AND METHODS FOR ACQUIRING A RECEIVED DATA SIGNAL IN A CLOCK AND DATA RECOVERY CIRCUIT - A clock a data recovery circuit (CDR) operates recovers data from a serial input signal. The CDR uses oversampling to sample the serial input signal at multiple phases. The multiple phases are generated from a reference clock that is not locked to the data rate of the serial input signal. A maximum of two phases are used at a time. The resulting CDR provides high performance while having low power consumption. | 11-13-2014 |
20140333353 | MANAGING CLOCK AND RECOVERY DATA - Disclosed are various embodiments for a clock and data recovery (CDR) system. The CDR system comprises a transition detection stage and a clock recovery stage. The transition detection stage is responsible for receiving the data signal and detecting whether a transition exists in the data signal by oversampling the data signal. The clock recovery stage generates a recovery clock based on whether there is a transition in the data signal. | 11-13-2014 |
20140340131 | REDUCING SETTLING TIME IN PHASE-LOCKED LOOPS - A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled. | 11-20-2014 |
20140347105 | COMPENSATION OF SLOW TIME-VARYING VARIATIONS IN VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY IN CELLULAR TRANSCEIVERS - Various configurations and arrangements of systems and methods for compensating for variations in VCO output frequencies are described. A system in accordance with the disclosure can include an oscillator circuit including an oscillator, a first variable capacitance diode coupled to the oscillator and a second variable capacitance diode coupled to the oscillator. The system further includes a voltage source configured to apply a first voltage to the oscillator circuit to cause the output signal to comprise a selected frequency, the selected frequency being based on a received reference voltage. The system further includes a controller circuit configured to compare an operating voltage of the oscillator to the reference voltage while the first voltage is applied to the oscillator; and apply a second voltage to the oscillator circuit based on the comparison. The second voltage compensates for a difference between the reference voltage and the first voltage. | 11-27-2014 |
20140361817 | PHASE-LOCKED LOOP DEVICE WITH SYNCHRONIZATION MEANS - A phase-locked loop (PLL) device includes synchronization means suitable for synchronizing a frequency-converted signal produced by a frequency divider of the PLL device, with a reference signal supplied to the PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization units allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state. | 12-11-2014 |
20140368242 | METHOD AND APPARATUS FOR CONTROL OF A DIGITAL PHASE LOCKED LOOP (DPLL) WITH EXPONENTIALLY SHAPED DIGITALLY CONTROLLED OSCILLATOR (DCO) - Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width. | 12-18-2014 |
20150061736 | SPREAD-SPECTRUM PHASE LOCKED LOOP CIRCUIT AND METHOD - A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency. | 03-05-2015 |
20150070058 | Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion - A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. | 03-12-2015 |
20150070059 | PHASE LOCKED LOOP CIRCUIT, PHASE LOCKED LOOP MODULE, AND PHASE LOCKED LOOP METHOD - Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply. | 03-12-2015 |
20150084678 | PHASE LOCKED LOOP CIRCUIT - A Phase Locked Loop (PLL) circuit is provided. The PLL includes a voltage controlled oscillator (VCO) for outputting an oscillation signal of a frequency corresponding to an inputted voltage, a frequency divider for dividing the oscillation signal and output a frequency-divided signal, a phase comparator for comparing a phase of the frequency-divided signal and the phase of an input signal from the outside and output a first phase comparison signal and a second phase comparison signal which have different polarities, a differential amplifier circuit for outputting a control voltage based on a voltage difference between the first phase comparison signal and the second phase comparison signal to the VCO, a level shift circuit for outputting a level-shifted signal which is made by shifting a direct current level of the second phase comparison signal, and an amplifier circuit for outputting an amplified signal which is an amplified level-shifted signal. | 03-26-2015 |
20150102843 | OSCILLATION CIRCUIT, OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - An oscillation circuit, an oscillator, an electronic device and a moving object, having at least a serial interface and an output enabling function, which are capable of implementing the control of output enabling without performing exclusive switching control using a switch, are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element, and includes a first terminal to which characteristic control data for controlling characteristics of the oscillation signal including at least a frequency is input and to which control data of a first output control signal for controlling an output of the oscillation signal is input. | 04-16-2015 |
20150109034 | DELAY ARCHITECTURE FOR REDUCING DOWNTIME DURING FREQUENCY SWITCHING - A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface. | 04-23-2015 |
20150130520 | TIMING ADJUSTMENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage. | 05-14-2015 |
20150137863 | Large Signal VCO - An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network. | 05-21-2015 |
20150145567 | CANCELLATION OF SPURIOUS TONES WITHIN A PHASE-LOCKED LOOP WITH A TIME-TO-DIGITAL CONVERTER - A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency. | 05-28-2015 |
20150303930 | MULTI-PHASE CLOCK GENERATOR - Embodiments provide a multi-phase clock generator. The clock generator includes a loop oscillator, a RC filter, a bias current source and a frequency injection source. The loop oscillator includes N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1. The N levels of CMOS phase inverters have the same structures, each of which includes a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source. As an effect of RC filter, a clock input signal inputted by the frequency injection source is applied to the first level tail current source, while other tail current sources are not influenced. Injection locking is induced, such that phase noise and frequency stray can be reduced. | 10-22-2015 |
20150311904 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal. | 10-29-2015 |
20150318858 | Clock generation circuit and method thereof - This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature. | 11-05-2015 |
20150326232 | Crystal Oscillator Noise Compensation Method for a Multi-Loop PLL - A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k. | 11-12-2015 |
20150326234 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED THEREWITH - It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal. | 11-12-2015 |
20150341041 | Phase Lock Loop Circuit Having a Wide Bandwidth - A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal. | 11-26-2015 |
20150341042 | DIGITAL PHASE LOCK LOOP CIRCUIT INCLUDING FINITE IMPULSE RESPONSE FILTERING TO REDUCE ALIASING OF QUANTIZATION NOISE - A digital phase lock loop circuit includes a phase detector, loop filter, finite impulse response filter (FIR), a plurality of digital to analog converters (DACs), a voltage controlled oscillator (VCO), and a divider. The FIR filter includes a predetermined number of taps, where each tap is connected to an input of one DAC in the plurality of DACs. The FIR filter attenuates high-frequency quantization error in a digital control signal that the plurality of DACs converts to an analog control signal for the VCO. The FIR filtered control signal reduces or eliminates quantization noise higher-frequency components that would otherwise be generated as DC quantization noise in a feedback signal generated by the divider. | 11-26-2015 |
20150349788 | CIRCUITS AND METHODS FOR ELIMINATING REFERENCE SPURS IN FRACTIONAL-N FREQUENCY SYNTHESIS - Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL. | 12-03-2015 |
20150364953 | Adaptive Holdover Timing Error Estimation and Correction - Disclosed herein are a variety of various systems and method for adaptive holdover time error estimation. In one embodiment a system may include a local time source configured to generate a local time signal and an external time source interface configured to receive an external time signal. A time source subsystem may be configured to compare the local time signal and the external time signal and to determine a temperature-dependent signal drift rate of the local time signal relative to the external time signal. The time source subsystem may be a time-dependent signal drift rate of the local time signal relative to the external time signal. A holdover subsystem may detect a loss of reception of the external time signal during a holdover period and may estimate a total maximum error based on an estimated maximum time-dependent error and an estimated maximum temperature-dependent error. | 12-17-2015 |
20150365071 | CAPACITANCE PHASE INTERPOLATION CIRCUIT AND METHOD THEREOF, AND MULTI-PHASE GENERATOR APPLYING THE SAME - A capacitance phase interpolation circuit including a first capacitance phase interpolation unit and a second capacitance phase interpolation unit is disclosed. The first capacitance phase interpolation unit includes a first capacitance group, wherein a plurality of capacitors in the first capacitance group are in a ring coupling, and the first capacitance phase interpolation unit receives a plurality of reference clock signals. The second capacitance phase interpolation unit is coupled to the first capacitance phase interpolation unit and includes a second capacitance group, wherein a plurality of capacitors in the second capacitance group are in a ring coupling, and each of the output clock signals is obtained via the first capacitance phase interpolation unit and the second capacitance phase interpolation unit by performing phase interpolation on all the reference clock signals. | 12-17-2015 |
20150372682 | SAMPLED ANALOG LOOP FILTER FOR PHASE LOCKED LOOPS - An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter. | 12-24-2015 |
20150372690 | CIRCUIT, A TIME-TO-DIGITAL CONVERTER, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER AND A TRANSCEIVER - A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values. | 12-24-2015 |
20150381187 | PHASE LOCK LOOP WITH CASCADE TRACKING FILTERS FOR SYNCHRONIZING AN ELECTRIC GRID - Present embodiments relate to a method for synchronizing an electric grid. The method includes receiving a phase voltage of the electric grid. The method further includes determining one or more disturbance frequencies in the phase voltage via a plurality of sequential tracking filters, wherein each of the plurality of tracking filters corresponds to a harmonic of the received phase voltage. The method further includes removing the disturbance frequencies components sequentially to produce a minimally distorted frequency, and performing a PLL operation on the clean frequency to determine a phase angle of the frequency. | 12-31-2015 |
20160013797 | METHODS RELATED TO FREQUENCY SYNTHESIS CONTROL | 01-14-2016 |
20160020776 | PHASE-LOCKED LOOP (PLL) - A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal. | 01-21-2016 |
20160036453 | PHASE LOCK LOOP WITH DYNAMIC LOCK RANGES - A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates. | 02-04-2016 |
20160065221 | SYNCHRONIZATION FOR MULTIPLE ARBITRARY WAVEFORM GENERATORS - A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs, and a sync hub having a sync controller and sync phase detector. The method operates by receiving at the sync hub a divided down clock (SystemRefClock) signal from a master arbitrary waveform generator (AWG). The method then derives a clock signal (SystemClock) from the SystemRefClock signal received from the master AWG and outputs the SystemClock signal to the master AWG and to the one or more slave AWGs Finally, the SystemClock signal is used to clock a synchronous trigger for the master AWG and one or more slave AWGs to play a waveform. In one aspect, the synchronous trigger includes AlignmentFiducial and Run signals to effect trigger and play commands. | 03-03-2016 |
20160065228 | APPARATUS AND METHOD FOR PHASE LOCKED LOOP BANDWIDTH EXPANSION - An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response. | 03-03-2016 |
20160079988 | FRACTIONAL N-PLL CIRCUIT, OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - In order to appropriately set an operation range of a voltage controlled oscillator without excessively increasing a frequency at which delta-sigma modulation is performed, a fractional N-PLL circuit includes: a voltage controlled oscillator that is configured to set plural output frequency ranges; a frequency selection circuit that selects one output frequency range; a division circuit; and a division setting circuit that sets a division ratio of the division circuit. The division setting circuit performs, while the frequency selection circuit is searching for the plural output frequency ranges of the voltage controlled oscillator, the delta-sigma modulation at a frequency lower than a frequency after the frequency selection circuit terminates the search. | 03-17-2016 |
20160079989 | PREDICTION BASED DIGITAL CONTROL FOR FRACTIONAL-N PLLS - Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error. | 03-17-2016 |
20160094334 | PHASE LOCKED LOOP WITH MODIFIED LOOP FILTER - A loop filter in a modified phase locked loop has a proportional path generating first output signal that is proportional to an input signal and an integral path for generating a second output signal that is an integral of the input signal. An additional functional path generates a third output signal that is a predetermined function of the input signal. The predetermined function is of the form f(s)/g(s), where f and g are polynomial functions. An adder combines the first, second, and third output signals into a common output signal. | 03-31-2016 |
20160112053 | Fractional-N Phase-Locked Loop - A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators. | 04-21-2016 |
20160118990 | AUTOMATICALLY PLACED-AND-ROUTED ADPLL WITH PWM-BASED DCO RESOLUTION ENHANCEMENT - An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (f | 04-28-2016 |
20160126960 | OPERATING PARAMETER CIRCUITRY AND METHOD - An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry. Consequently, the generator circuitry is able to produce an operating parameter signal that has been compensated for noise in the circuit. | 05-05-2016 |
20160126961 | PHASE DETECTOR - A phase detector including a first latch and a control logic is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal. | 05-05-2016 |
20160142065 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 05-19-2016 |
20160173067 | SYSTEM AND METHOD FOR ENHANCED CLOCKING OPERATION | 06-16-2016 |
20160173109 | XOR PHASE DETECTOR, PHASE-LOCKED LOOP, AND METHOD OF OPERATING A PLL | 06-16-2016 |
20160173111 | MODIFIED DELTA-SIGMA MODULATOR FOR PHASE COHERENT FREQUENCY SYNTHESIS APPLICATIONS | 06-16-2016 |
20160182065 | COARSE TUNING SELECTION FOR PHASE LOCKED LOOPS | 06-23-2016 |
20160191023 | IMPLEMENTING CLOCK RECEIVER WITH LOW JITTER AND ENHANCED DUTY CYCLE - A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current minors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry. | 06-30-2016 |
20160191064 | FREQUENCY MODULATION CIRCUIT AND SEMICONDUCTOR DEVICE - A frequency modulation circuit includes a calibration-operating part which calculates primary calibration values of modulation index at central frequencies of respective ones of n pieces of TF bands which constitute the entire TF range. Interpolation-calculation part performs an interpolation-calculation with respect to the n pieces of primary calibration values and calculates calibration values at intermediate frequencies of central frequencies of neighboring ones of TF bands while calculating calibration values at frequencies at both ends of entire TF range to obtain (n+ | 06-30-2016 |
20160380639 | PHASE LOCK METHOD - A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal. | 12-29-2016 |
20170237444 | DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE | 08-17-2017 |