Class / Patent application number | Description | Number of patent applications / Date published |
327148000 | With charge pump | 20 |
20080290916 | System Clock Generation Circuit - A system clock signal generator circuit comprising a first PLL circuit that is frequency and phase locked to a wobble signal; a frequency and phase comparator for comprising a first output signal from the first PLL circuit with a system clock signal as frequency divided by M and for outputting a second output signal based on the differences in frequency and in phase; a PLL filter for providing a predetermined cutoff to the second output signal to output a third output signal; a pulse width modulating circuit for generating a pulse wave, the carrier frequency of which is a second reference clock signal, and for outputting a fourth output signal obtained by modulating the pulse width of the pulse wave by the third output signal; a low pass filter for smoothing the fourth output signal to output a fifth output signal; a VCO circuit the control voltage of which is the fifth output signal; a first frequency divider circuit for frequency dividing an output signal of the VCO circuit by N to output a system clock signal; and a second frequency divider circuit for frequency dividing, by M, and feeding the system clock signal back to the frequency and phase comparator. | 11-27-2008 |
20090096496 | PHASE-LOCKED LOOP AND CONTROL METHOD UTILIZING THE SAME - A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode. | 04-16-2009 |
20090108888 | Switched-Capacitor Charge Pumps - A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors. | 04-30-2009 |
20090146702 | CHARGE PUMP AND METHOD FOR OPERATING THE SAME - A charge pump comprises a ring oscillator and a pumping circuit. The ring oscillator provides a plurality of oscillating clocks. The pumping circuit includes a plurality of pumping blocks coupled to each other for outputting a boosted voltage, and each pumping block is connected to a corresponding oscillating clock. | 06-11-2009 |
20090261873 | SIGNAL GENERATING CIRCUIT - A signal generating circuit includes a detecting circuit, a charge pump, a first level shifter, a filtering circuit, a second level shifter and a controllable oscillator. The detecting circuit outputs a detecting signal according to a reference signal and an oscillating signal. The charge pump outputs a first output signal by performing a charging or discharging operation according to the detecting signal. The first level shifter adjusts a voltage level of the first output signal to thereby output a second output signal. The filtering circuit generates a first filtered control signal according to the second output signal. The second level shifter adjusts a voltage level of the first filtered controlling signal to output a second filtered control signal. The controllable oscillator outputs the oscillating signal according to the second filtered control signal. | 10-22-2009 |
20100090731 | SELF-CALIBRATION METHOD FOR A FREQUENCY SYNTHESIZER USING TWO POINT FSK MODULATION - The frequency synthesizer ( | 04-15-2010 |
20100127739 | SPREAD SPECTRUM CONTROL PLL CIRCUIT AND ITS START-UP METHOD - A calibration circuit ( | 05-27-2010 |
20110148484 | PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER - Described is a frequency synthesizer having a wide output frequency range and small frequency tuning steps. In-band spurious components are maintained at low levels and phase noise is significantly reduced. The frequency synthesizer can be fabricated as an integrated circuit device having a small area and low power dissipation. The frequency synthesizer can be used in wideband frequency systems to reduce cost and size by replacing multiple frequency synthesizers each devoted to a portion of the overall system frequency range. | 06-23-2011 |
20110175652 | FRACTIONAL-N PHASE-LOCKED LOOP - A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference. | 07-21-2011 |
20110181326 | PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR - A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value. | 07-28-2011 |
20110215846 | PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF - A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock. | 09-08-2011 |
20110260760 | VOLTAGE CONTROL OSCILLATOR AND CONTROL METHOD THEREOF - A voltage control oscillator and a control method thereof is disclosed in the invention. The voltage control oscillator increases frequency of an output frequency as a control signal is increased under a first mode. The voltage control oscillator decreases frequency of the output frequency as a control signal is increased under a second mode. | 10-27-2011 |
20110279154 | Clock Generating Circuit and Clock Generating Method - A clock generating circuit includes a phase detector for detecting a phase difference between a first clock and a second clock to generate a detecting result associated with the phase difference, a first filtering device for filtering the detecting result, a charge pump for generating a control signal according to the filtered detecting result, a second filtering device for filtering the control signal, and a controllable oscillator for generating an output clock according to the filtered control signal, wherein the output clock is utilized to generate the second clock. | 11-17-2011 |
20120062286 | TERAHERTZ PHASED ARRAY SYSTEM - Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission. | 03-15-2012 |
20120139591 | PHASE INTERPOLATOR AND SEMICONDUCTOR CIRCUIT DEVICE - A first mixer generates a first and a second clock signal having a phase opposite to that of the first clock signal. A second mixer generates a third clock signal having a phase lead angle of 90 degrees with respect to the first clock signal and a fourth clock signal having a phase opposite to that of the third clock signal. An ADC generates a digital signal from a signal that is generated on the basis of a composite signal of a voltage signal formed on the basis of the exclusive OR of the first and the third clock signal and a voltage signal formed on the basis of the exclusive OR of the second and the fourth clock signal. An adder adds the digital signal to the first control signal to generate the second control signal and supplies the second control signal to the second mixer. | 06-07-2012 |
20120223750 | TRANSCEIVER, VOLTAGE CONTROL OSCILLATOR THEREOF AND CONTROL METHOD THEREOF - A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock. | 09-06-2012 |
20130099836 | GYROSCOPE WITH PHASE AND DUTY-CYCLE LOCKED LOOP - A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint. | 04-25-2013 |
20130106475 | METHOD OF OPERATING PHASE-LOCK ASSISTANT CIRCUITRY | 05-02-2013 |
20130113534 | CLOCK DATA RECOVERY CIRCUIT AND TRANSCEIVER SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING THE SAME - A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than −1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of −1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state. | 05-09-2013 |
20140218080 | METHOD AND SYSTEM FOR FAST SYNCHRONIZED DYNAMIC SWITCHING OF A RECONFIGURABLE PHASE LOCKED LOOP (PLL) FOR NEAR FIELD COMMUNICATIONS (NFC) PEER TO PEER (P2P) ACTIVE COMMUNICATIONS - A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock. | 08-07-2014 |