| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327146000 | With feedback | 89 |
| 20130120033 | CHARGE-DOMAIN FILTER AND METHOD THEREOF - A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal. | 05-16-2013 |
| 20100052744 | Multiphase Clock Generator with Enhanced Phase Control - A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing. | 03-04-2010 |
| 20080290914 | Self-Clearing Asynchronous Interrupt Edge Detect Latching Register - A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one. | 11-27-2008 |
| 20080284473 | PHASE SYNCHRONOUS CIRCUIT - An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable. | 11-20-2008 |
| 20110221486 | DIGITALLY CALIBRATED HIGH SPEED CLOCK DISTRIBUTION - An electronic circuit for distributing a clock signal to a plurality of clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; and loop filters for generating and transmitting respective DC voltage feedback signals. | 09-15-2011 |
| 20080204090 | Glitch-free clock regeneration circuit - A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output. | 08-28-2008 |
| 20120126865 | CLOCK REGENERATION CIRCUIT - A clock regeneration circuit according to an exemplary embodiment of the present invention is characterized in that a phase comparison result of serial data being inputted and a clock signal is shaped with use of the clock signal or another clock signal having a predetermined phase difference from the clock signal, and a phase of the clock signal is controlled with use of the shaped phase comparison result. | 05-24-2012 |
| 327147000 | Phase lock loop | 82 |
| 20120200323 | PHASE-LOCK ASSISTANT CIRCUITRY - A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal. | 08-09-2012 |
| 20130057325 | AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE - Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation. | 03-07-2013 |
| 20130113533 | TEMPERATURE COMPENSATED FREQUENCY REFERENCE COMPRISING TWO MEMS OSCILLATORS - A temperature compensated frequency reference comprising first MEMS oscillator (MEMS | 05-09-2013 |
| 20120235716 | ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE - An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop. | 09-20-2012 |
| 20110298503 | Dynamic voltage-controlled oscillator calibration and selection - A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically. Another selection routine comprises a successive voltage-controlled oscillator routine that executes every time a frequency is requested by comparing a requested frequency to different frequency thresholds without executing a calibration operation. | 12-08-2011 |
| 20090278577 | SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR - A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal. | 11-12-2009 |
| 20090289672 | Method of processing signal data with corrected clock phase offset - The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained. | 11-26-2009 |
| 20080284474 | Techniques for integrated circuit clock management - A clock generator ( | 11-20-2008 |
| 20080290915 | SYSTEM AND METHOD FOR FAST RE-LOCKING OF A PHASE LOCKED LOOP CIRCUIT - A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles. | 11-27-2008 |
| 20100201412 | OSCILLATOR, AND RECEIVING DEVICE AND ELECTRONIC DEVICE USING THE OSCILLATOR - An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices. | 08-12-2010 |
| 20110006818 | CLOCK SYNCHRONIZATION SYSTEM, NODE, CLOCK SYNCHRONIZATION METHOD, AND PROGRAM - The invention provides a clock synchronization system which synchronizes the clock of a slave node with the clock of a master node by use of a timestamp packet transmitted from the master node to the slave node on the packet network, wherein the slave node includes a phase comparison part | 01-13-2011 |
| 20120068741 | PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal. | 03-22-2012 |
| 20110221487 | CLOCK SYNCHRONISER - A clock synchroniser for generating a local clock signal synchronised to a received clock signal. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. | 09-15-2011 |
| 20090051395 | DC/DC converter with spread spectrum switching signals - A DC/DC converter includes a converting circuit for converting a first voltage into a second voltage; a controller for generating spread spectrum switching signals; and a switch according to the spread spectrum switching signals controlling the on/off state of the switch. | 02-26-2009 |
| 20120194231 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal. | 08-02-2012 |
| 20100277210 | THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION - a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews. | 11-04-2010 |
| 20080309385 | ELECTRONIC DEVICE AND METHOD FOR ON CHIP SKEW MEASUREMENT - The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value. | 12-18-2008 |
| 20080231332 | Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method - The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL. | 09-25-2008 |
| 20100213992 | Delay locked loop circuit and operation method thereof - A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal. | 08-26-2010 |
| 20080218226 | CIRCUITS AND APPARATUS TO IMPLEMENT DIGITAL PHASE LOCKED LOOPS - Circuits and apparatus to implement digital phase locked loops are disclosed. A disclosed example digital phase locked loop circuit comprises a phase detector to detect a phase difference between a reference signal and a feedback signal, a time digitizer to convert the phase difference to a digital value, and an adder to add an offset to the digital value, the offset selected to reduce a digital phase locked loop dead zone | 09-11-2008 |
| 20110304364 | Device For Removing Electromagnetic Interference And Semiconductor Package Including The Same - Provided is an electromagnetic interference (EMI) removing device for active reduction of electromagnetic interference and a semiconductor package including the same. The EMI removing device may include a film substrate having an antenna pattern configured to generate a second electromagnetic wave, which may have substantially the same frequency band, modulation mode, and directivity as a first electromagnetic wave generated by a first semiconductor chip and a phase opposite to a phase of the first electromagnetic wave | 12-15-2011 |
| 20110316593 | Phase Locked Loop with Startup Oscillator and Primary Oscillator - A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator. | 12-29-2011 |
| 20120043999 | MEMS STABILIZED OSCILLATOR - A voltage controlled crystal oscillator (VCXO) is locked to a MEMS oscillator with a variable frequency ratio that is a function of a sensed temperature. That allows the long-term stability of the MEMS oscillator and temperature compensation to be reflected in a VCXO output signal having good short-term stability. | 02-23-2012 |
| 20110156771 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal. | 06-30-2011 |
| 20120013374 | PHASE-LOCK ASSISTANT CIRCUITRY - Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. | 01-19-2012 |
| 20120161826 | COMPENSATING DFLL WITH ERROR AVERAGING - A compensating DFLL (CDFLL) is disclosed that utilizes temperature readings at regular intervals in combination with production characterization data of a reference oscillator to compensate for frequency drift and nominal frequency error. In some implementations, the CDFLL selects a calibration value that is not optimal for frequency accuracy to minimize accumulated frequency error over time. More particularly, during a calibration run, mismatch between an ideal frequency and an actual frequency is measured, and the measurement is used as a starting point for a next calibration run, such that the accumulated frequency error is averaged almost to zero over time. | 06-28-2012 |
| 20120133401 | PLL CIRCUIT, ERROR CORRECTING METHOD FOR THE SAME, AND COMMUNICATION APPARATUS INCLUDING THE SAME - A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity. | 05-31-2012 |
| 20120161827 | CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE - A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals. | 06-28-2012 |
| 20120074993 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component. | 03-29-2012 |
| 20130009679 | BANG-BANG PHASE DETECTOR WITH HYSTERESIS - In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state. | 01-10-2013 |
| 327148000 | With charge pump | 18 |
| 20090108888 | Switched-Capacitor Charge Pumps - A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors. | 04-30-2009 |
| 20130113534 | CLOCK DATA RECOVERY CIRCUIT AND TRANSCEIVER SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING THE SAME - A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than −1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of −1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state. | 05-09-2013 |
| 20120223750 | TRANSCEIVER, VOLTAGE CONTROL OSCILLATOR THEREOF AND CONTROL METHOD THEREOF - A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock. | 09-06-2012 |
| 20130099836 | GYROSCOPE WITH PHASE AND DUTY-CYCLE LOCKED LOOP - A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint. | 04-25-2013 |
| 20110279154 | Clock Generating Circuit and Clock Generating Method - A clock generating circuit includes a phase detector for detecting a phase difference between a first clock and a second clock to generate a detecting result associated with the phase difference, a first filtering device for filtering the detecting result, a charge pump for generating a control signal according to the filtered detecting result, a second filtering device for filtering the control signal, and a controllable oscillator for generating an output clock according to the filtered control signal, wherein the output clock is utilized to generate the second clock. | 11-17-2011 |
| 20110215846 | PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF - A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock. | 09-08-2011 |
| 20090146702 | CHARGE PUMP AND METHOD FOR OPERATING THE SAME - A charge pump comprises a ring oscillator and a pumping circuit. The ring oscillator provides a plurality of oscillating clocks. The pumping circuit includes a plurality of pumping blocks coupled to each other for outputting a boosted voltage, and each pumping block is connected to a corresponding oscillating clock. | 06-11-2009 |
| 20090261873 | SIGNAL GENERATING CIRCUIT - A signal generating circuit includes a detecting circuit, a charge pump, a first level shifter, a filtering circuit, a second level shifter and a controllable oscillator. The detecting circuit outputs a detecting signal according to a reference signal and an oscillating signal. The charge pump outputs a first output signal by performing a charging or discharging operation according to the detecting signal. The first level shifter adjusts a voltage level of the first output signal to thereby output a second output signal. The filtering circuit generates a first filtered control signal according to the second output signal. The second level shifter adjusts a voltage level of the first filtered controlling signal to output a second filtered control signal. The controllable oscillator outputs the oscillating signal according to the second filtered control signal. | 10-22-2009 |
| 20090096496 | PHASE-LOCKED LOOP AND CONTROL METHOD UTILIZING THE SAME - A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode. | 04-16-2009 |
| 20120139591 | PHASE INTERPOLATOR AND SEMICONDUCTOR CIRCUIT DEVICE - A first mixer generates a first and a second clock signal having a phase opposite to that of the first clock signal. A second mixer generates a third clock signal having a phase lead angle of 90 degrees with respect to the first clock signal and a fourth clock signal having a phase opposite to that of the third clock signal. An ADC generates a digital signal from a signal that is generated on the basis of a composite signal of a voltage signal formed on the basis of the exclusive OR of the first and the third clock signal and a voltage signal formed on the basis of the exclusive OR of the second and the fourth clock signal. An adder adds the digital signal to the first control signal to generate the second control signal and supplies the second control signal to the second mixer. | 06-07-2012 |
| 20100127739 | SPREAD SPECTRUM CONTROL PLL CIRCUIT AND ITS START-UP METHOD - A calibration circuit ( | 05-27-2010 |
| 20110260760 | VOLTAGE CONTROL OSCILLATOR AND CONTROL METHOD THEREOF - A voltage control oscillator and a control method thereof is disclosed in the invention. The voltage control oscillator increases frequency of an output frequency as a control signal is increased under a first mode. The voltage control oscillator decreases frequency of the output frequency as a control signal is increased under a second mode. | 10-27-2011 |
| 20110148484 | PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER - Described is a frequency synthesizer having a wide output frequency range and small frequency tuning steps. In-band spurious components are maintained at low levels and phase noise is significantly reduced. The frequency synthesizer can be fabricated as an integrated circuit device having a small area and low power dissipation. The frequency synthesizer can be used in wideband frequency systems to reduce cost and size by replacing multiple frequency synthesizers each devoted to a portion of the overall system frequency range. | 06-23-2011 |
| 20100090731 | SELF-CALIBRATION METHOD FOR A FREQUENCY SYNTHESIZER USING TWO POINT FSK MODULATION - The frequency synthesizer ( | 04-15-2010 |
| 20120062286 | TERAHERTZ PHASED ARRAY SYSTEM - Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission. | 03-15-2012 |
| 20110181326 | PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR - A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value. | 07-28-2011 |
| 20110175652 | FRACTIONAL-N PHASE-LOCKED LOOP - A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference. | 07-21-2011 |
| 20080290916 | System Clock Generation Circuit - A system clock signal generator circuit comprising a first PLL circuit that is frequency and phase locked to a wobble signal; a frequency and phase comparator for comprising a first output signal from the first PLL circuit with a system clock signal as frequency divided by M and for outputting a second output signal based on the differences in frequency and in phase; a PLL filter for providing a predetermined cutoff to the second output signal to output a third output signal; a pulse width modulating circuit for generating a pulse wave, the carrier frequency of which is a second reference clock signal, and for outputting a fourth output signal obtained by modulating the pulse width of the pulse wave by the third output signal; a low pass filter for smoothing the fourth output signal to output a fifth output signal; a VCO circuit the control voltage of which is the fifth output signal; a first frequency divider circuit for frequency dividing an output signal of the VCO circuit by N to output a system clock signal; and a second frequency divider circuit for frequency dividing, by M, and feeding the system clock signal back to the frequency and phase comparator. | 11-27-2008 |
| 327149000 | With variable delay means | 32 |
| 20130043916 | Wave Clocking - Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC. | 02-21-2013 |
| 20090128201 | CLOCK GENERATORS AND CLOCK GENERATION METHODS THEREOF - Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency. | 05-21-2009 |
| 20130038363 | DELAY LOCKED LOOP - A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal. | 02-14-2013 |
| 20130099837 | PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME - A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node. | 04-25-2013 |
| 20120306551 | CIRCUIT AND METHOD FOR PREVENTING FALSE LOCK AND DELAY LOCKED LOOP USING THE SAME - The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal. | 12-06-2012 |
| 20110285432 | CLOCK DATA RESTORATION DEVICE - A clock data restoration device | 11-24-2011 |
| 20110298504 | CLOCK GENERATOR AND METHODS USING CLOSED LOOP DUTY CYCLE CORRECTION - Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments. | 12-08-2011 |
| 20080238502 | Delay cell and phase locked loop using the same - A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock. | 10-02-2008 |
| 20100123489 | PROCESS INSENSITIVE DELAY LINE - A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line. | 05-20-2010 |
| 20090309637 | DELAY LINE OFF-STATE CONTROL WITH POWER REDUCTION - A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state. | 12-17-2009 |
| 20090115471 | DELAY LOCKED LOOP AND OPERATING METHOD THEREOF - A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit. | 05-07-2009 |
| 20090278578 | DELAY LOCKED LOOP CIRCUIT AND DELAY LOCKING METHOD - A delay locked loop circuit includes a phase detecting unit for detecting a phase difference between a reference clock signal and a feedback clock signal, and for producing a phase difference detection signal, a code generating unit for producing a digital code signal according to the phase difference detection signal, a control current generating unit for generating a control current using the digital code signal, and a current controlled delay line for producing the feedback clock signal by delaying the reference clock signal by a delay time varied by the control current. | 11-12-2009 |
| 20080284475 | Semiconductor device having delay locked loop and method for driving the same - A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal. | 11-20-2008 |
| 20090121757 | DATA CENTER TRACKING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal. | 05-14-2009 |
| 20090167379 | Method and Apparatus for Digital VCDL Startup - Methods and apparatus are provided fox improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The control signal can be, for example, a delay control current or a delay control voltage. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. The determined control signal can optionally be stored in a table for each of the plurality of PVT combinations | 07-02-2009 |
| 20090079477 | DATA DRIVER CIRCUIT AND DELAY- LOCKED LOOP - A data driver circuit and a delay-locked loop (DLL) are provided. The data driver circuit and DLL can operate normally in spite of errors, etc., caused when an analog data signal is applied to a display panel. The DLL, which receives a first clock signal and outputs a second clock signal, includes a phase detector for outputting a phase difference signal according to the first clock signal, the second clock signal and at least one delay signal, and a delay line for generating the second clock signal and the delay signal by delaying the first clock signal. Here, the phase difference signal has a value corresponding to a phase difference between the first clock signal and the second clock signal, according to the first clock signal or the second clock signal, and a value corresponding to a case in which there is no phase difference according to the delay signal, and a first delay that is a delay of the second clock signal with respect to the first clock signal changes according to the phase difference signal. | 03-26-2009 |
| 20100237915 | METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP - Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. | 09-23-2010 |
| 20100237916 | DELAY LOCKED LOOP WITH FREQUENCY CONTROL - Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed. | 09-23-2010 |
| 20100237914 | CLOCK DISTRIBUTION DEVICE AND CLOCK DISTRIBUTION METHOD - A clock distribution device to an exemplary aspect of the invention includes: a first clock output unit outputting a first clock synchronized to a reference clock; a second clock output unit outputting a second clock synchronized to the reference clock; a first clock distribution unit including a first branch point, branching the first clock at the first branch point and outputting a third clock; a second clock distribution unit including a second branch point, branching the second clock at the second branch point and outputting a fourth clock; and a phase difference detecting unit detecting a first phase difference between a phase of the third clock and a phase of the fourth clock, and the second clock output unit controls a second phase difference between a phase of the first clock and a phase of the second clock so that the first phase difference is reduced. | 09-23-2010 |
| 20110102029 | DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value. | 05-05-2011 |
| 20090066379 | Delay Stage-Interweaved Analog DLL/PLL - A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 03-12-2009 |
| 20110025384 | DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT - Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port. | 02-03-2011 |
| 20100039148 | APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME - A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL. | 02-18-2010 |
| 20100295585 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLK | 11-25-2010 |
| 20080204091 | Semiconductor chip package and method for fabricating semiconductor chip - A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved. | 08-28-2008 |
| 20090102523 | LINEAR DIGITAL PHASE INTERPOLATOR AND SEMI-DIGITAL DELAY LOCKED LOOP (DLL) - Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL. | 04-23-2009 |
| 20100013530 | DLL-Based Multiplase Clock Generator - The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range. | 01-21-2010 |
| 20100052745 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 03-04-2010 |
| 20100271087 | DELAY LOCKED LOOP AND OPERATING METHOD THEREOF - A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit. | 10-28-2010 |
| 20120319747 | PHASE-LOCKED LOOP LOCK DETECT - Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time. | 12-20-2012 |
| 20120268176 | CIRCUIT AND METHOD FOR GENERATING MULTIPHASE CLOCK SIGNALS AND CORRESPONDING INDICATION SIGNALS - A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals. | 10-25-2012 |
| 20100164566 | DELAY LOCKED LOOP CIRCUIT AND OPERATIONAL METHOD THEREOF - A delay locked loop circuit includes a clock buffering block to generate first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal, respectively, wherein generation of the second internal clock is controlled by a duty correcting operation terminating signal and a delay locking signal, a delay locking block to compare phases of the first and second internal clocks with those of first and second feedback clocks, respectively, to enable the delay locking signal according to a delay locking and delay the first and second internal clocks as many as times corresponding to the comparison results, respectively, thereby outputting first and second delay locking clocks, a duty correcting block to mix phases of the first and second delay locking clocks, and a first signal generating block to generate the duty correcting operation terminating signal. | 07-01-2010 |
| 327150000 | With digital element | 2 |
| 20130043917 | HARDWARE CONTROLLED PLL SWITCHING - A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL. | 02-21-2013 |
| 20090256600 | INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM - An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal. | 10-15-2009 |
