Class / Patent application number | Description | Number of patent applications / Date published |
327145000 | Having different frequencies | 35 |
20080231331 | Spread spectrum clock generator - Disclosed are embodiments of methods and circuits to generate spread spectrum clocks. | 09-25-2008 |
20080252339 | METHOD AND APPARATUS FOR GENERATING SYNCHRONOUS CLOCK SIGNALS FROM A COMMON CLOCK SIGNAL - A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and generate a second output clock signal having a second pre-determined frequency relative to the first pre-determined frequency of the first output clock signal. The first output clock signal is substantially synchronous to the second output clock signal. | 10-16-2008 |
20080290913 | CLOCK SIGNAL SWITCHING DEVICE, CLOCK SIGNAL SWITCHING METHOD, DATA BUS SWITCHING DEVICE, AND DATA BUS SWITCHING METHOD - A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals. | 11-27-2008 |
20090021290 | Method and System for Improved Efficiency of Synchronous Mirror Delays and Delay Locked Loops - A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output. | 01-22-2009 |
20090058477 | Method and system for reclocking a digital signal - A method and system are disclosed for reclocking a digital time-based signal. An exemplary method includes receiving a digital signal output at a first clock rate. Data transitions of the received digital signal are measured using a master clock having a second clock rate. The digital signal is filtered to determine approximate edge positions of the data transitions. A tolerance is enforced between the approximate edge positions to reconstruct the digital signal. The reconstructed signal is output. The exemplary system for reclocking a digital time-based signal includes an input section, a processor and a reconstruction section. | 03-05-2009 |
20090058478 | EFFICIENT CLOCKING SCHEME FOR ULTRA HIGH-SPEED SYSTEMS - There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal. | 03-05-2009 |
20090267660 | Circuit and design structure for synchronizing multiple digital signals - Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path. | 10-29-2009 |
20100073044 | SYNCHRONIZING TIMING DOMAINS BASED ON STATE VARIABLES - Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This synchronization circuit synchronizes clock signals in different timing domains using state variables. In particular, the synchronization circuit generates a synchronization acquisition curve based on a temporal history of state-variable differences between the clock signals. Next, the synchronization circuit synchronizes the clock signals (without a discontinuous temporal transient in one or more state variables of a dependent one of the clock signals) based on the sum of the synchronization acquisition curve and the state-variable differences between the clock signals. This state variable may include: a phase of the dependent clock signal, a frequency of the dependent clock signal, and/or a rate of change of the frequency of the dependent clock signal. | 03-25-2010 |
20100295584 | PLL CIRCUIT AND OPTICAL DISC APPARATUS - A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data. | 11-25-2010 |
20100315134 | SYSTEMS AND METHODS FOR MULTI-LANE COMMUNICATION BUSSES - Multi-lane PCI express busses devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used for synchronizing data transfers between IC dies of a plurality of integrated-circuits (IC) dies. In a first IC die, a synchronizing signal is received and latched in a first clock domain and in the first IC die to produce a first latched output signal. The latched output signal is provided for use by each of the plurality of IC dies. In each of the plurality of IC dies, the first latched output signal is latched in the first clock domain to produce a second latched output signal. The second latched output signal is latched in a second clock domain to produce a third latched output signal. The third latched output signal is used to synchronize a respective communication lane. | 12-16-2010 |
20100315135 | Redriver With Two Reference Clocks And Method Of Operation Thereof - A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register. | 12-16-2010 |
20100327923 | BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. | 12-30-2010 |
20110089981 | SEMICONDUCTOR DEVICE AND COMMUNICATION METHOD - It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit. The communication timing control circuit generates the communication timing signal determined by a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal. | 04-21-2011 |
20110204932 | Asynchronous Scheme for Clock Domain Crossing - Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element. | 08-25-2011 |
20110204933 | ELECTRIC CIRCUIT AND SIGNAL PROCESSING METHOD - An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern. | 08-25-2011 |
20110260759 | DATA SYNCHRONIZER FOR SYNCHRONIZING DATA AND COMMUNICATION INTERFACE INCLUDING THE SAME - According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency. A reception timing generator is configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal. The reception timing generator comprises flip-flops connected in cascade. An update timing adjusting module is configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal. | 10-27-2011 |
20120062285 | DISCRETE TIME POLYPHASE MIXER - Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a polyphase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response. | 03-15-2012 |
20120112806 | FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD - The present invention relates to a frequency synthesizer comprising a main unit and a side unit. The main unit comprises a main phase detector to obtain a main control signal, a main oscillator that generates a main synthesized frequency output signal representing the frequency synthesizer output signal based on said main control signal, and a mixer that mixes said main synthesized frequency output signal with a side synthesized frequency output signal to obtain said mixer output signal. The side unit generates said side synthesized frequency output signal and comprises a frequency signal generation unit that provides a linear frequency sweep signal or a fixed-frequency control signal at a fine frequency resolution from said fixed-frequency side reference signal, and a side oscillator that generates said side synthesized frequency output signal based on said frequency sweep signal or said fixed-frequency control signal. | 05-10-2012 |
20120176168 | SIGNAL CIRCUIT - A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data. | 07-12-2012 |
20120242381 | FLOATING POINT TIMER TECHNIQUES - Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications. | 09-27-2012 |
20130021072 | Dynamic Frequency Control Using Coarse Clock Gating - A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal. | 01-24-2013 |
20130043915 | CIRCUITS AND METHODS FOR SIGNAL TRANSFER BETWEEN DIFFERENT CLOCK DOMAINS - In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse. | 02-21-2013 |
20130169325 | SYSTEMS AND METHODS OF SIGNAL SYNCHRONIZATION FOR DRIVING LIGHT EMITTING DIODES - System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch. | 07-04-2013 |
20140070855 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
20140070856 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
20140118037 | PHASE-LOCKED LOOP - The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output dock signal. The frequency down conversion circuit is configured to receive the output dock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal to generate a feedback clock signal. By detecting the strength of the feedback clock signal, it provides an auxiliary signal to adjust the frequency of the output clock signal. The PFD is configured to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal. The adjusting circuit is configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal. | 05-01-2014 |
20150091623 | CLOCK MULTIPLEXING AND REPEATER NETWORK - A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs. | 04-02-2015 |
20150137862 | SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS - A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses. | 05-21-2015 |
20150349787 | SLOW TO FAST CLOCK SYNCHRONIZATION - A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal. | 12-03-2015 |
20160013783 | SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING PLURALITY OF CHANNELS | 01-14-2016 |
20160077546 | METHOD FOR SYNCHRONIZING INDEPENDENT CLOCK SIGNALS - An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal. | 03-17-2016 |
20160142058 | DELAY CIRCUIT - A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit. | 05-19-2016 |
20160173080 | SYSTEM FOR REDUCING NOISE IN A CHEMICAL SENSOR ARRAY | 06-16-2016 |
20160173090 | APPARATUS AND METHOD FOR DETECTING OR REPAIRING MINIMUM DELAY ERRORS | 06-16-2016 |
20160182058 | METHOD FOR CLOCK CALIBRATION | 06-23-2016 |