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Using multiple clocks

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327141000 - Synchronizing

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
327146000 With feedback 92
327153000 With delay means 30
327145000 Having different frequencies 23
327151000 With counter 7
327152000 With choice between multiple delayed clocks 2
20110062998Semiconductor device having level shift circuit, control method thereof, and data processing system - To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.03-17-2011
20110057691RECEIVING APPARATUS AND RECEIVING METHOD THEREOF - The receiving apparatus according to the present invention includes a multi-phase clock generating circuit, a latch component, an error check component, and a selector circuit. The multi-phase clock generating circuit generates a plurality of clocks, phases of which are different from each other. The latch component receives an external data divided into two or more and the plurality of the clocks, and concurrently obtains a plurality of data, clock-timing of which is different from each other, by latching the external data by different clocks. The error check component detects an error of the respective data. The selector circuit selects data judged as no-error data from the plurality of the data, and outputs the selected data as received data. According to the circuit configuration like this, it is possible to precisely receive the data.03-10-2011
Entries
DocumentTitleDate
20100117692MULTI-PHASE CLOCK GENERATION CIRCUIT HAVING A LOW SKEW IMPRECISION - A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases.05-13-2010
20090121756PSEUDO-SYNCHRONOUS SMALL REGISTER DESIGNS WITH VERY LOW POWER CONSUMPTION AND METHODS TO IMPLEMENT - Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides.05-14-2009
20100073043NETWORK AND METHOD FOR SETTING A TIME-BASE OF A NODE IN THE NETWORK - A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronisation system connected to the master clocks. The synchronisation system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronisation data source for generating slave clock synchronisation data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronisation data source. The time-base controller may receive the slave clock synchronisation data and control one or more of the one or more slave clocks in accordance with the slave clock synchronisation data.03-25-2010
20090160507Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates - In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the adder unit, the adder unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an adder unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the adder unit. it.06-25-2009
20100001770NETWORK AND METHOD FOR SETTING A TIME-BASE OF A NODE IN THE NETWORK - A data communication network may include two or more master clocks, and a synchronisation system connected to the master clocks. The synchronisation system may determine a time-base for the master clocks. The synchronisation system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.01-07-2010
20110057690CLOCK CONTROL CIRCUIT AND TRANSMITTER - A transmitter 03-10-2011
20090128199BIASED CLOCK GENERATOR - A method and system for generating a pair of synchronized clock signals is described. The system includes a first device connected between a first output voltage and an input reference voltage, wherein the first device generates a first output clock signal. Further, the system includes a second device connected in series with the first device. In particular, the second device is connected between the input reference voltage and a second output voltage, wherein the second device generates a second output clock signal. In addition, a first switching circuit is connected in parallel with the first device and a second switching circuit is connected in parallel with the second device. The first switching circuit operates to toggle the first device on and off and the second switching circuit operates to toggle the second device on and off. The first and second switching circuits are coupled to a comparator, which receives a first input clock and a second input clock signal.05-21-2009
20110285431Self-Gating Synchronizer - A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.11-24-2011
20110298502Switching Clock Sources - A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.12-08-2011
20110291712SCANNING-LINE DRIVE CIRCUIT - A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.12-01-2011
20100066419SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.03-18-2010
20090146700DUTY RATIO CORRECTION CIRCUIT - A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.06-11-2009
20080265956Semiconductor device having input circuits activated by clocks having different phases - Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.10-30-2008
20090261872FAST, LOW POWER FORMATTER FOR AUTOMATIC TEST SYSTEM - Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set and reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.10-22-2009
20110199134TEST APPARATUS, TRANSMISSION APPARATUS, RECEIVING APPARATUS, TEST METHOD, TRANSMISSION METHOD AND RECEIVING METHOD - Provided is a test apparatus that tests a device under test, comprising a phase comparing section that compares a phase of an internal clock generated in the test apparatus and a phase of a clock superimposed on a device signal output by the device under test; an adjusting section that adjusts a phase shift amount of the internal clock with respect to the device signal, based on the phase comparison result; an acquiring section that acquires the device signal according to the internal clock whose phase shift amount with respect to the device signal is adjusted; and an inhibiting section that inhibits change of the phase shift amount based on the phase comparison result, for at least a portion of a period during which the clock is not superimposed on the device signal. Also provided is a test method relating to the test apparatus.08-18-2011
20090140781CIRCUIT FOR DATA SYNCHRONIZATION OF I2C TIME CONTROLLER IN DISPLAY DEVICE AND METHOD THEREOF - A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master.06-04-2009
20090045854Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization - A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.02-19-2009
20120229184All Digital Serial Link Receiver with Low Jitter Clock Regeneration and Method Thereof - An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.09-13-2012
20090128200RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.05-21-2009
20090315597Clock Selection for a Communications Processor having a Sleep Mode - A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.12-24-2009
20090045853TIMING CONTROLLER, DISPLAY APPARATUS HAVING THE SAME AND METHOD FOR DRIVING THE DISPLAY APPARATUS - A timing controller, a display apparatus having the timing controller and a method for driving the display apparatus, the timing controller includes a control part, an inner clock and a control signal. The control part detects whether an external clock signal and image data received from an external image apparatus are abnormal. The inner clock generating part includes a reference voltage generating circuit outputting a reference voltage independent of temperature, and generates an inner clock signal using the reference voltage. The control signal generating part generates a first driving control signal using the external clock signal and generates a second driving control signal using the inner clock signal. Accordingly, the inner clock signal that is stable with respect to the surrounding temperature and voltage variation is generated when the external clock signal and the image data are abnormal, and thus driving reliability may be enhanced.02-19-2009
20080265955SYNCHRONIZATION CIRCUIT AND METHOD - An integrated circuit comprises a system clock and an interface clock. A synchronizing circuit is provided for synchronizing a control signal associated with a predetermined command, for example a PENABLE signal associated with a WRITE command, when the system clock of the integrated circuit is present and bypassing the synchronization circuitry when the system clock is not present. Thus, whenever the system clock of the integrated circuit is active, all the control interface write operations are synchronized to the system clock, and hence there are no timing issues due to different clock domains. If the system clock is not present, the asynchronous writes cannot cause any timing problems, and the synchronization circuit is therefore bypassed.10-30-2008
20110102028MULTIPHASE CLOCK GENERATION CIRCUIT - The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase.05-05-2011
20090146701SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER - A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.06-11-2009
20110068839SYSTEM EMPLOYING SYNCHRONIZED CRYSTAL OSCILLATOR-BASED CLOCK, TO BE USED IN EITHER DISCRETE OR INTEGRATED APPLICATIONS - A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.03-24-2011
20110163785SIMPLE INTERLEAVED PHASE SHIFT CLOCK SYNCHRONIZATION FOR MASTER/SLAVE SCHEME - An apparatus for interleaved phase shift clock synchronization includes a master clock generator and at least one slave clock generator. The master clock generator provides a ramp signal or reset signal for each slave clock generator to generate a clock synchronized with the clock of the master clock generator, and the master and slave clock generators have different reference voltages for generating clocks. Therefore, the clocks generated will be synchronized and interleaved phase with each other.07-07-2011
20080218225Semiconductor Device and Communication Control Method - The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores.09-11-2008
20100019811Self-Stabilizing Byzantine-Fault-Tolerant Clock Synchronization System and Method - Systems and methods for rapid Byzantine-fault-tolerant self-stabilizing clock synchronization are provided. The systems and methods are based on a protocol comprising a state machine and a set of monitors that execute once every local oscillator tick. The protocol is independent of specific application specific requirements. The faults are assumed to be arbitrary and/or malicious. All timing measures of variables are based on the node's local clock and thus no central clock or externally generated pulse is used. Instances of the protocol are shown to tolerate bursts of transient failures and deterministically converge with a linear convergence time with respect to the synchronization period as predicted.01-28-2010
20110050300Clock Generator - A data processing system comprises a plurality of sub-circuits (03-03-2011
20100289538CLOCK CONDITIONING CIRCUIT - A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.11-18-2010
20090058476RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT - A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.03-05-2009
20100052743SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD - The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.03-04-2010
20100271086DUAL-BAND COUPLED VCO - In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCO10-28-2010
20100001769Method and Apparatus for Synchronizing Time Stamps - Various apparatuses and methods for synchronizing time stamps are disclosed herein. For example, some embodiments of the present invention provide apparatuses for synchronizing a coarse time stamp with a fine time stamp. Such apparatuses include an event signal input, a clock input, a coarse time stamp generator having an input connected to the clock input, and a fine time stamp generator having a first input connected to the clock input, a second input connected to the event signal input, and a synchronization signal output. The apparatuses also include a synchronizer having a first input connected to the clock input, a second input connected to the event signal input, a third input connected to the synchronization signal output and an output connected to the coarse time stamp generator. The synchronizer is adapted to synchronize the coarse time stamp generator to the fine time stamp generator based at least in part on the synchronization signal output. The apparatuses are adapted to combine a synchronized coarse time stamp from the coarse time stamp generator with a fine time stamp from the fine time stamp generator to form a time stamp indicating when an event signal transitioned on the event signal input.01-07-2010
20110221485Time synchronization method and apparatus - The present invention discloses a time synchronization method and apparatus. The method comprises: each net element node locks a clock synchronization signal of its upper-level net element node through a physical channel, and a clock synchronization network is established; and each net element node performs time counting by using the locked clock synchronization signal and performs time compensation according to the time counting through a time synchronization protocol to realize time synchronization. Through the present invention, each net element node performs the time counting by using the locked clock signal, and performs the time compensation according to the time counting to realize the time synchronization, thus the problem that the accumulative effect of phase transfer results in very obvious phase delay in the related technologies is solved, so as to reduce the phase delay and realize high precision, high interference resistance and reliability.09-15-2011
20130207698CLOCK DISTRIBUTION SYSTEM AND METHOD FOR A MULTI-BIT LATCH - A clock distribution system for a multi-bit latch. The clock distribution system may include a plurality of branches, each connected to a common clock input. Each branch may be driven by an input clock buffer. Each branch may be connected to clock inputs of a predetermined number of latch stages within the multi-bit latch. A predetermined number of clock branches may include a clock output buffer. The number of clock output buffers may be less than the total number of latch stages. In this manner the clock distribution system may reduce the feed through capacitance of the latch stages, which may mitigate the latch transition skew for each latch stage.08-15-2013

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