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Responsive to power supply

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

327141000 - Synchronizing

327142000 - Reset (e.g., initializing, starting, stopping, etc.)

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Entries
DocumentTitleDate
20130043914TIME-BASED APPARATUS AND METHOD TO MITIGATE SEMICONDUCTOR AGING EFFECTS - Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be.02-21-2013
20100164564STARTING APPARATUS AND STARTING METHOD - A starting apparatus includes: a storage unit storing an identifier; a rectifying unit rectifying a reception signal; a generating unit comparing the reception signal rectified in the rectifying unit to a reference signal and generating a digital signal from the reception signal; a judging unit judging whether or not the digital signal contains information of the identifier; a reference changing unit changing the reference signal when the judging unit judges that the reception signal does not contain information of the identifier; and a start instructing unit instructing start of an electric appliance when the judging unit judges that the reception signal contains information of the identifier.07-01-2010
20100164565SEMICONDUCTOR START CONTROL DEVICE, METHOD, AND SYSTEM - A semiconductor device provided which includes: an external power supply detection circuit which detects that an external power supply is turned on and outputs a first detection signal; an internal power supply voltage generation circuit which generates an internal power supply voltage based on the external power supply; a reference voltage generation circuit which generates a first reference voltage in response to the first detection signal; a reference voltage detection circuit which detects that the first reference voltage reaches a given level and outputs a second detection signal; a bias voltage generation circuit which, in response to the second detection signal, generates a bias voltage based on a second reference voltage dependent on the first reference voltage; and a power supply voltage detection circuit which, in response to the second detection signal, compares the bias voltage with a third reference voltage and outputs a start signal.07-01-2010
20120176167SEMICONDUCTOR DEVICE INCLUDING POWER-ON RESET CIRCUIT - A semiconductor device including a power-on-reset (POR) circuit. The semiconductor device includes a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope and a first POR signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time.07-12-2012
20090085618WAKE-UP CIRCUIT - Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.04-02-2009
20090121755SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.05-14-2009
20090121754Power-On Reset Circuit - An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.05-14-2009
20100073042SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a initialization signal generating unit configured to vary a voltage level of an external voltage in response to a detection signal, the external voltage enables a power-up signal, an internal voltage generating unit configured to produce an internal voltage, the internal voltage generating unit is initialized by the power-up signal, and a detection signal generating unit configured to produce the detection signal in response to a voltage level of the internal voltage.03-25-2010
20100073041METHOD AND APPARATUS TO SELECT A PARAMETER/MODE BASED ON A MEASUREMENT DURING AN INITIALIZATION PERIOD - Techniques are disclosed to select functional parameters and/or operating modes of a circuit based on a measurement during an initialization period. In one aspect an integrated circuit includes a threshold detection circuit coupled to measure during an initialization period of the integrated circuit a signal from a first external circuit comprising one or more components coupled to a first external terminal of the integrated circuit. A selection circuit is coupled to the threshold detection circuit to select a parameter/mode of the integrated circuit in response to the signal from the first external circuit during the initialization period of the integrated circuit. The first external terminal is further coupled to one or more additional external circuits, each of which comprising one or more components. The one or more additional external circuits are coupled to provide one or more signals at the first external terminal to be used by the integrated circuit during normal operation at times other than the initialization period to provide at least one additional function for the integrated circuit after the initialization period of the integrated circuit is complete.03-25-2010
20130076410POWER ON RESET SIGNAL GENERATING APPARATUS AND METHOD - A power on reset signal generating apparatus is provided. The power on reset signal generating apparatus includes a trigger capacitor, a reference current supplying circuit, and a current regulator. One end of the trigger capacitor is coupled to a ground voltage, and the other end of the trigger capacitor generates a power on reset signal. The reference current supplying circuit is coupled to a signal generating end. The current regulator is coupled to the signal generating end, and the signal generating end draws a splitting current to adjust the value of the current received by the trigger capacitor.03-28-2013
20090160506POWER-ON CLEAR CIRCUIT - Provided is a power-on clear circuit which normally operates. Even when a rising speed of a power supply voltage is slow, or when the power supply voltage rises from a voltage other than a ground voltage, a voltage of a node (C) is unlikely to become unstable owing to provision of a pull-down element (06-25-2009
20130038361POWER-SWITCH TEST APPARATUS AND METHOD - Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.02-14-2013
20090066378SOURCE DRIVER AND METHOD FOR RESTRAINING NOISE THEREOF - The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a data bus, a plurality of channels, a multiplexer and a plurality of output pads. The channels are connected to the output pads via the multiplexer. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The source driver is powered by a first supply voltage from the power supply. The method comprises determining whether the first supply voltage is insufficient, and if yes, performing the following steps. First, set the data transmitted on the data bus to be a predetermined value. Then, keep the latch units turned on, thereby the data is sent out from the latch units. Then, keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads.03-12-2009
20130038362SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and is configured to output the first potential in response to input of high level and to output the second potential in response to input of low level. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator.02-14-2013
20100109723POWER-UP SIGNAL GENERATING CIRCUIT AND INTEGRATED CIRCUIT USING THE SAME - A power-up signal generating circuit includes a detecting unit configured to output a bias signal having a voltage level corresponding to an external power voltage in response to an internal voltage and a deep power down (DPD) signal; and a signal generating unit configured to generate a power-up signal having a logic level corresponding to the voltage level of the external power voltage in response to the DPD signal and the bias signal, wherein the internal voltage increases during an activation time of the power-up signal to reach a predetermined voltage level after a predetermined time, and maintains a ground voltage level during an inactivation period of the power-up signal.05-06-2010
20090302903DRIVING APPARATUS, LIQUID CRYSTAL DISPLAY HAVING THE SAME AND DRIVING METHOD THEREOF - A driving apparatus resets driving circuits provided therein after an internal supply voltage reaches a sufficient voltage level. The driving apparatus includes a reset signal generator that resets the driving circuits when the internal supply voltage exceeds the external supply voltage in a rising period of the internal supply voltage. Accordingly, the driving circuits may be prevented from being reset before the internal supply voltage reaches the sufficient voltage level, thereby preventing an abnormal operation of the driving circuits.12-10-2009
20090302902POWER UP SIGNAL GENERATION CIRCUIT AND METHOD FOR GENERATING POWER UP SIGNAL - A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.12-10-2009
20120218012ON-CHIP POWER-UP CONTROL CIRCUIT - A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.08-30-2012
20130057324CIRCUIT FOR CLEARING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INFORMATION - A circuit for clearing complementary metal oxide semiconductor (CMOS) information of a CMOS chip includes a battery, first to fifth resistors, first and second electronic switches, a switching unit, and first and second diodes. The circuit can clear information of the CMOS chip when one or more switches are activated.03-07-2013
20090267659POWER-ON RESET CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A power-on reset circuit, connected to an external direct current (DC) power source, to receive DC power signals and generate a reset signal, includes a delay circuit, a combination circuit and a shaping circuit. The delay circuit comprises a plurality of delay units, to delay the received DC power signals and output a plurality of delayed DC power signals. The combination circuit is connected to the delay circuit, to combine the delayed DC power signals into a combination signal, and output the combination signal. The shaping circuit is connected to and turns the combination circuit on and off according to the combination signal and outputs the reset signal.10-29-2009
20110012650MICROCONTROLLER UNIT AND METHOD THEREFOR - A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.01-20-2011
20090237130Dual power-up signal generator - A dual power-up signal generator includes a power-up signal generator which generates a first power-up signal by using a first voltage signal obtained by detecting a level of a power supply voltage, and generates a second power-up signal by using a second voltage signal obtained by detecting the level of the power supply voltage.09-24-2009
20100085087AUTOMATIC ON-CHIP DETECTION OF POWER SUPPLY CONFIGURATION-MODES FOR INTEGRATED CHIPS - A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.04-08-2010
20080297212START-UP CIRCUITY FOR PROVIDING A START-UP VOLTAGE TO AN APPLICATION CIRCUIT - A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit, the startup circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit having a low voltage terminal; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and a second terminal, the dropping resistor dropping the high voltage DC bus voltage to a reduced voltage and providing the reduced voltage at the second terminal; further comprising a low voltage regulator coupled to the second terminal for using the reduced voltage for enabling generation of a regulated startup low voltage DC output at a preset level at the low voltage terminal for powering at least one part of the application circuit during startup of the application circuit, wherein the high voltage DC bus voltage is the only voltage source provided externally to the integrated circuit package.12-04-2008
20100060331POWER-ON-RESET CIRCUITRY - Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.03-11-2010
20120032717POWER-ON RESET CIRCUIT - When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit (02-09-2012
20110285430HOT-SWAP CONTROLLER - According to one embodiment, a hot-swap controller includes an output circuit, a voltage generator, a detector, and a compensator. The output circuit is configured to generate an enabling signal. The enabling signal is capable of switching an output signal of a semiconductor device provided on a hot-swap board to be disabled when a supply voltage is lower than a release voltage and to be enabled when the supply voltage is higher than the release voltage. The voltage generator includes a bias transistor supplied with the supply voltage and is configured to generate a first voltage. The first voltage varies depending on the supply voltage and is referred to detect the release voltage. The detector is configured to detect the first voltage. The compensator is configured to compensate the first voltage to a certain value depending on an output of the detector.11-24-2011
20110298501Methods and Apparatuses for Delay-Locked Loops and Phase-Locked Loops - A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.12-08-2011
20110291711POWER-UP SIGNAL GENERATION APPARATUS AND METHOD - A power-up signal generation apparatus includes: a pre-power-up signal generation unit configured to generate a pre-power-up signal depending on a level of a power supply voltage; and a control unit configured to output the pre-power-up signal as a power-up signal in response to an active signal.12-01-2011
20100090730Circuit and method of adjusting system clock in low voltage detection, and low voltage reset circuit - The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.04-15-2010
20080238499CUSTOMIZABLE POWER-ON RESET CIRCUIT BASED ON CRITICAL CIRCUIT COUNTERPARTS - A power-on-reset circuit (POR) for integrated circuits that detects the minimum power levels needed to operate the most critical circuit(s) reliably. The circuit is implemented in a customized POR built into a custom IC, and emulates the critical circuit transistors in the custom IC using mimicking counterparts which are similarly affected by changes in temperature and process variations as the main circuit components. The mimicking counterparts may have smaller dimensions, to draw less current but still emulate the characteristics of the main working circuit components. Each critical sub-circuit of the main circuit may have a mimicking POR, and the multiple PORs may have their outputs combined by logic so that subtle failure modes can be modeled in the POR. The POR allows operation of the main circuit to continue at the lowest possible voltage levels while reducing the risk of unexpected results or undetected non-catastrophic failures. The POR also implements safety margins for the operation of the main circuit and tracks process sensitivity.10-02-2008
20080238501Initialization signal generating circuit - An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.10-02-2008
20080238500Power-up signal generating circuit and method for driving the same - A power-up signal generating circuit that prevents repeatedly generating a power-up signal even when there is noise on an external voltage. The power-up signal generating circuit includes a level detector, a level comparator, and a reentry protector. The level detector is configured to deactivate a first level detection signal when a level of an external voltage increases above a upper limit reference voltage. The level comparator is configured to deactivate a second level detection signal when the level of the external voltage increases above a lower limit reference voltage. The reentry protector is configured to activate the power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal.10-02-2008
20100007388METHOD AND ARRANGEMENT RELATING POWER SUPPLY IN AN ELECTRICAL DEVICE - The present invention relates to an arrangement and method for eliminating power failures due to harmful motion. The device includes electrical components that use electrical power, a power source that connects to the electrical components, a motion sensor, and a processing unit. The motion sensor may sense a motion of the device substantially corresponding to free-fall condition, the processing unit may receive a signal from the motion sensor based on the first predetermined motion profile, and the processing unit may generate a signal supplied to at least some of the electrical components to cause a shut down operational mode.01-14-2010
20100085088Semiconductor device and method of supplying internal power to semiconductor device - Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage. The startup non-operating step-down circuit group includes the multiple step-down circuits sequentially selected from one having a shortest wiring distance from the power-on reset circuit.04-08-2010
20090206891Power Cycling Power On Reset Circuit for Fuse Initialization Circuitry - A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.08-20-2009
20110267115POWER-ON RESET CIRCUIT WITH SUPPRESSED CURRENT - A power-on reset circuit includes a first monitor circuit that monitors a power supply voltage, an output circuit that outputs a reset release signal upon detection, by the first monitor circuit, of the power supply voltage exceeding a first predetermined value, and a control circuit having lower current consumption than the first monitor circuit, wherein the control circuit includes a second monitor circuit that monitors the power supply voltage, a suppression circuit that suppresses current flowing through the first monitor circuit upon detection, by the second monitor circuit, of the power supply voltage exceeding a second predetermined value higher than the first predetermined value, and an output fixing circuit that fixes the output of the output circuit to a predetermined potential upon detection, by the second monitor circuit, of the power supply voltage exceeding the second predetermined value.11-03-2011
20090115470MEMORY RESET APPARATUS - A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.05-07-2009
20090273376AC/DC CONVERTERS AND METHODS OF MANUFACTURING SAME - The present invention discloses AC/DC converters and methods of manufacturing the same. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage.11-05-2009
20090102522POWER ON RESET CIRCUITRY - One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment includes providing a voltage to a POR circuit of the system, detecting when the voltage reaches a number of different trip levels, maintaining a count of the number of times an output signal of the POR circuit trips in response to a detected reaching of one of the number of different trip levels, and adjusting the trip level to be detected based at least partially on the count.04-23-2009
20090261871METHOD AND SYSTEM FOR POWER SAVING AND STATE RETENTION IN ELECTRONIC DEVICE - A method and a system for power saving and state retention in an electronic device are provided. The method for power saving and state retention in an electronic device includes recording a state variation of electronic components of a plurality of groups in a second circuit of the electronic device in a variation table stored in memory of a first circuit or the second circuit of the electronic device; before stopping providing power to the second circuit, selecting some groups from the plurality of groups according to the variation table and making a backup of states of electronic components of the selected groups; and after restoring power to the second circuit, restoring the states of electronic components of the selected groups according to states in the backup.10-22-2009
20090261870POWER-ON DETECTION CIRCUIT FOR DETECTING MINIMUM OPERATIONAL FREQUENCY - A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.10-22-2009
20090167377Semiconductor storage device and resetting method for a semiconductor storage device - An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.07-02-2009
20110267114SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal.11-03-2011
20090167378Method and System for Providing a Power-On Reset Pulse - Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.07-02-2009
20130021071LOW CURRENT, HIGH ACCURACY POWER-ON-RESET - The present disclosure relates generally to power-on-reset (POR) devices for activation of a circuit block powered by a battery. The POR devices activate a circuit block when a battery voltage level of a battery voltage generated by the battery is above a dead battery condition voltage level. So that the circuit block is activated after the battery voltage level of the battery voltage has reached the dead battery condition voltage level, the POR device includes a trigger circuit. The trigger circuit is operable to receive the battery voltage and is configured to generate a trigger signal in response to the battery voltage level being charged above a trigger voltage level, which is equal to or greater than the dead battery condition voltage level. The POR circuit is also operable to generate a POR signal in an activation state and activate the circuit block.01-24-2013
20100201411Semiconductor memory device - A semiconductor memory device includes a first power switch for interrupting supply of a first power voltage to a first node in a standby mode, and a second power switch connected between the first node and a second node applied with a second power voltage.08-12-2010
20100201410Power-up Control for Very Low-Power Systems - A power-on-reset (POR) circuit may comprise a first circuit powered by a first supply voltage and configured to generate a second supply voltage based on the first supply voltage, the second supply voltage having a nominal value lower than a nominal value of the first supply voltage. The POR circuit may also include a second circuit powered by the second supply voltage and configured to generate a POR signal. The second circuit may be configured to assert the POR signal when the second supply voltage reaches a value that is sufficiently high for the second circuit to become operational, keep the POR signal asserted until the first supply voltage reaches a second value that is higher than the nominal value of the second supply voltage by a specified difference voltage value, and deassert the POR signal once the first supply voltage reaches the second value.08-12-2010
20080309384Initialization Circuitry Having Fuse Leakage Current Tolerance - A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.12-18-2008
20080211552Controllable synchronous rectifier - The present controllable synchronous rectifier employs a Lus semiconductor to set synchronous rectification action in quadrant 1 of output characteristics of the conventional power MOSFETs. By controlling the voltage level of the gate-source voltage, the drain current can be controlled in the synchronous rectifier. Further, in combination with a protect opposite circuit to transfer a sinusoidal wave power supply or pulse power supply to a direct current power output, the synchronous rectifier is an indispensable high efficiency rectifier in the industry.09-04-2008
20090160505POWER-UP CIRCUIT REDUCING VARIATION IN TRIGGERING VOLTAGE CAUSED BY VARIATION IN PROCESS OR TEMPERATURE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up circuit that can reduce a variation of the triggering voltage that is caused by variations in process or temperature in a semiconductor integrated circuit is described. The power-up circuit includes a first detector for outputting a first triggering voltage signal according to a power voltage level and a second detector for outputting a second triggering voltage signal according to the power voltage level. The power-up circuit also includes an output unit generating and outputting a power-up signal according to the first triggering voltage signal and the second triggering voltage signal and providing the output to various internal circuits.06-25-2009
20120229183POWER-ON RESET CIRCUIT AND ELECTRONIC DEVICE HAVING THE SAME - A power-on reset circuit includes a current source circuit supplying a current that varies according to a temperature to a first node, a first transistor connected between the first node and a ground voltage and having a gate connected with a power supply voltage, and an output circuit connected with the first node and outputting a power-on reset signal in response to a signal applied to the first node.09-13-2012
20120229182SIGNAL GENERATING APPARATUS FOR GENERATING POWER-ON-RESET SIGNAL - A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.09-13-2012
20090085619POWER SUPPLY VOLTAGE MONITORS - The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry.04-02-2009
20110227613POWER CONTROL CIRCUIT - A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.09-22-2011
20090201056Preset Circuit of Audio Power Amplifier - A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold.08-13-2009
20110221484CIRCUIT FOR GENERATING POWER-UP SIGNAL OF SEMICONDUCTOR MEMORY APPARATUS - A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.09-15-2011
20090021289Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal - An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.01-22-2009
20090002037Reset control method and apparatus in power management integrated circuit - A reset control apparatus may include a first reference generator adapted to output a first reference value in response to an enable signal from an external power source, a second reference generator adapted to receive the first reference value and to output a second reference value, and a set signal generator adapted to output a set signal when the second reference value exceeds a predetermined value.01-01-2009
20090243669POWER-ON RESET CIRCUIT - A power-on reset circuit includes a voltage-dividing circuit, a first switch and a second switch. The voltage-dividing circuit includes a first resistor and a second resistor connected in series. A first terminal of the voltage-dividing circuit is configured for connect to a power source, a second terminal of the voltage-dividing circuit is grounded. A first switch includes an input terminal, a control terminal, and an output terminal. The input terminal of the first switch is connected to the first terminal of the voltage-dividing circuit via the first resistor, and the output terminal of the first switch is grounded. A second switch includes an input terminal connected to the first terminal of the voltage-dividing circuit, a control terminal connected to the control terminal of the first switch, and an output terminal connected to a reset terminal of an electronic device.10-01-2009
20090256597POWER-ON RESET CIRCUIT - A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal.10-15-2009
20100156478ELECTRONIC DEVICE AND SIGNAL GENERATOR THEREOF - An electronic device includes a signal generator and a processing module. The signal generator generates reset signals to reset the processing module. The signal generator includes a first capacitor, a second capacitor, and a switching unit. The first capacitor receives an input voltage and charges accordingly when the electronic device is powered on. The second capacitor generates the reset signals based on the input voltage. The switching unit transmits the input voltage to the second capacitor to charge the second capacitor when the electronic device is powered on, and grounds the second capacitor after the electronic device is powered off. The reset signals are generated during the charging and discharging process of the second capacitor.06-24-2010
20100156479POWER-ON RESET CIRCUIT AND ADJUSTING METHOD THEREFOR - A power-on reset circuit includes a detection-voltage producing circuit that produces a detection voltage proportional to a power-supply voltage, and a power-on determining circuit that activates a power-on reset signal when a detection voltage is less than the power-on determining voltage and inactivates the power-on reset signal when the detection voltage is equal to or greater than the power-on determining voltage. In the detection-voltage producing circuit, a fuse element used for adjusting a proportional constant between a power-supply voltage and the detection voltage is arranged. Thereby, the power-on determining voltage becomes adjustable. Accordingly, the power-on determining voltage can be made closer to a design value when there is a deviation from the design value in the power-on determining voltage after the semiconductor device is manufactured.06-24-2010
20100259304POWER DETECTING DEVICE, POWER SUPPLY DEVICE USING THE SAME AND REFERENCE VOLTAGE GENERATOR - A power detecting device, a power supply device using the same, and a reference voltage generator are provided. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device. Therefore, when the power voltage doesn't reach a stable, the power-on reset circuit will not be incorrectly started by increasing the reference voltage.10-14-2010
20100194453SEMICONDUCTOR DEVICE - A device includes a voltage converter circuit that includes an output node, a voltage drop circuit, and a first transistor. The first transistor is electrically coupled between the output node and the voltage drop circuit.08-05-2010
20100188123Power Sequencing With Logic Enabled Regulator - A power sequencing circuit includes a PNP transistor, a first, second and third resistor, and a logic enabled regulator. A voltage is coupled at a first node to the emitter of the transistor, the first resistor is coupled between the first node and the base of the transistor, the second resistor is coupled between the base and a grounded node, the third resistor is coupled between the grounded node and the collector of the transistor, and the logic enabled regulator has an enable pin coupled to and driven by the collector.07-29-2010
20100188124POWER-ON RESET CIRCUIT - Provided is a power-on reset circuit suitable for a semiconductor device that operates at a low supply voltage. When a supply voltage (VDD) becomes higher than a first output circuit reversal threshold voltage (Vz) after a reset signal is output, a first control circuit (07-29-2010
20100237913ELECTRONIC DEVICE - An electronic device includes a first reset signal generator arranged to output a first reset signal when a power supply voltage becomes lower than or equal to a first threshold, a second reset signal generator arranged to output a second reset signal when the power supply voltage becomes lower than or equal to a second threshold lower than the first threshold, a return reset signal generator arranged to output a return reset signal based on a termination of the output of the first reset signal, a first resetting device arranged to be reset based on the first reset signal, a second resetting device arranged to be reset based on the second reset signal and the return reset signal, and a pre-processor arranged in the second resetting device to start a preliminary process of resetting based on the first reset signal.09-23-2010
20100253399Circuit Arrangement for Operating Voltage Detection - A circuit arrangement for operating voltage detection has a detection block (10-07-2010
20100127738CIRCUIT SYSTEM, CIRCUIT BLOCK, AND ELECTRONIC DEVICE - According to one embodiment, a circuit system includes an adjusted module, a circuit adjusting module, a power controller, and a set value storage module. The adjusted module operates in a circuit state adjusted by calibration. The circuit adjusting module adjusts the circuit state of the adjusted module by calibration and obtains a set value corresponding to the adjusted circuit state. The power controller stops power supply to at least the adjusted module upon transition to power saving mode and resume the power supply upon return from the power saving mode. The set value storage module non-volatilely stores the set value even in the power saving mode. The circuit adjusting module causes the set value storage module to non-volatilely store the set value upon power-on, and adjusts the circuit state of the adjusted module according to the set value upon return from the power saving mode.05-27-2010
20100013529Reset signal generating circuit - A reset signal generating circuit outputs a reset signal having a sufficient pulse width even when the power supply voltage is fluctuated. A node B reaches a high level during a power-on reset and is at a low level during operation. When a power supply (Vcc) fluctuates during operation and as soon as a node C reaches a high level, a switch element MN01-21-2010
20090256598POWER-UP SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING THE SAME - A power-up signal generator of a semiconductor memory apparatus includes a power-up signal generating unit that includes a MOS transistor having a gate receiving a divided voltage of an external supply voltage, the power-up signal generating unit determining a level of a power-up signal according to a turn-ON state of the MOS transistor, and a bulk bias voltage generating unit that applies a bulk bias voltage to a bulk of the MOS transistor to adjust a threshold voltage of the MOS transistor, wherein the bulk bias voltage varies according to a temperature of the semiconductor memory device.10-15-2009
20100219866Apparatus and Methods for Programmable Power-Up Sequence - Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.09-02-2010
20090212834SEQUENCING CONTROL CIRCUIT - A sequencing control circuit includes an electronic component configured for controlling a signal output to a motherboard, and input voltages being input to the sequencing control circuit. The input voltages are connected to an input terminal of the electronic component. The electronic component includes a preset threshold and input voltage requirements. The electric component is configured such that only when all of the required input voltages rise to their peak values and the voltage of the input terminal of the electronic component reaches the threshold. The electronic component is triggered, and an output terminal of the electronic component outputs a high level signal to the motherboard.08-27-2009
20110032010POWER UP SIGNAL GENERATION CIRCUIT AND METHOD FOR GENERATING POWER UP SIGNAL - A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.02-10-2011
20090108887FAST POWER-ON DETECT CIRCUIT WITH ACCURATE TRIP-POINTS - A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.04-30-2009
20100301909STARTUP CIRCUITRY AND CORRESPONDING METHOD FOR PROVIDING A STARTUP CORRECTION TO A MAIN CIRCUIT CONNECTED TO A STARTUP CIRCUITRY - A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit.12-02-2010
20100308877POWER-ON RESET CIRCUIT - A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.12-09-2010
20100308876SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SAVING AND RECOVERING INTERNAL STATE THEREOF - A semiconductor integrated circuit includes: a first circuit; and a second circuit configured to control supply of a first power to the first circuit. The first circuit includes: a third circuit comprising a group of flip-flops, whose internal state is erased in response to stop of the supply of the first power; and a fourth circuit in which an internal state of the fourth circuit is saved in retention flip-flops before the supply of the first power is stopped and recovered from the retention flip-flops in response to restart of the supply of the first power.12-09-2010
20100134155POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME - A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.06-03-2010
20110241741SYSTEM AND METHOD TO CONTROL A POWER ON RESET SIGNAL - A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.10-06-2011
20110128053POWER-ON RESET SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.06-02-2011
20100156477BANDGAP REFERENCED POWER ON RESET (POR) CIRCUIT WITH IMPROVED AREA AND POWER PERFORMANCE - In an apparatus for monitoring a supply voltage, a current mirror coupled to the supply voltage provides a pair of matching currents. A resistor divider that includes a first resistor coupled in series with a second resistor to from a first node is disposed between the supply voltage and a voltage reference. A pair of transistors that have their bases coupled to the first node are coupled to receive a corresponding one of the pair of matching currents. A collector of a first transistor of the pair of transistors provides an output voltage in response to the supply voltage. A third resistor is disposed between an emitter of a second transistor of the pair of transistors and the voltage reference. A base and a collector of a third transistor are coupled to the first node and an emitter is coupled to the voltage reference.06-24-2010
20110115533POWER-ON-RESET CIRCUIT WITH BROWN-OUT RESET FOR MULTIPLE POWER SUPPLIES - A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.05-19-2011
20120242380SELECTABLE THRESHOLD RESET CIRCUIT - A low voltage testing circuit (09-27-2012
20110074473RESET CIRCUIT - In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.03-31-2011
20110121870VOLTAGE DETECTOR - A voltage detector includes a first input terminal, a second input terminal, a first voltage detection circuit, a second voltage detection circuit, and a logic holder circuit. The first input terminal receives a first input voltage. The second input terminal receives a second input voltage. The first voltage detection circuit outputs a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage. The second voltage detection circuit outputs a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage. The logic holder circuit retains the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.05-26-2011
20110074471SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.03-31-2011
20090219066POWER-ON RESET CIRCUIT - A power-on reset circuit produces a reset signal output configured by an upper trip-point in an input hysteresis characteristic of the circuit. The upper trip-point is configured by resistances of a first pair of resistors coupled in series at an internal voltage reference node. A temperature coefficient of the upper trip-point is configured by resistance values of a second pair of resistors where each resistor is coupled with a corresponding switching device with an associated switching threshold. A magnitude of the input hysteresis characteristic is configured by resistances of a third pair of resistors in series. The magnitude of hysteresis is configured independent of configuring either the level or the temperature coefficient of the upper trip-point.09-03-2009
20090219065Semiconductor Device and Electronic Apparatus - A read-start-timing set circuit is connected to a timing terminal (CT09-03-2009
20110210772DELTA PHI GENERATOR WITH START-UP CIRCUIT - A circuit comprises a delta phi generator, a startup circuit, and a level detector. The delta phi generator has a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state. The startup circuit is coupled to the delta phi generator. The startup circuit ensures that the delta phi generator does not operate in the undesirable operating state. The level detector comprises a comparator with an offset. The comparator has a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit. The level detector detects the delta phi voltage, and in response, disables the startup circuit.09-01-2011
20110074472SEMICONDUCTOR DEVICE AND POWER CONTROL METHOD USED FOR SAME - A semiconductor device includes an internal circuit; a plurality of power switches arranged in parallel configured to supply a current to the internal circuit; an instruction circuit configured to output a instruction signal for controlling power supply to the internal circuit; a variation detection circuit configured to detect the current and to output a detection result; and a logic circuit configured to control a timing when the plurality of power switches becomes a conducting state in accordance with the detection result and the instruction signal.03-31-2011
20110074470Low current power-on reset circuit and method - A power-on reset (POR) circuit includes a first transistor (MP03-31-2011
20110068838ELECTRONIC DEVICE FOR POWER-ON-RESET - An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.03-24-2011
20110068837APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.03-24-2011
20110148483INTEGRATED ELECTRONIC DEVICE WITH REFERENCE VOLTAGE SIGNAL GENERATION MODULE AND UVLO LOGIC SIGNAL GENERATION MODULE - An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.06-23-2011
20100295583Apparatus for awaking an electronic device from a standby mode - An apparatus is used to awake an electronic device to an active mode from a standby mode in case of change in the voltage of a power supply of the electronic device. The apparatus includes a power supply for supplying electricity, a switch connected to the power supply, a low-voltage reset unit connected to the switch, a micro-controller unit connected to the switch and a monitoring and awaking unit. The monitoring and awaking unit includes an actuator connected to the switch, a bias generator connected to the actuator and a comparator connected to the bias generator. The control over the power supply by the switch causes change in the voltage of the actuator which cooperates with the bias generator and the comparator to generate an awaking signal to awake the micro-processing unit.11-25-2010
20100097109RESET CIRCUIT AND SYSTEM HAVING RESET CIRCUIT - In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.04-22-2010
20100090729CIRCUIT FOR CLEARING CMOS INFORMATION - A circuit for clearing complementary metal oxide semiconductor (CMOS) information of a CMOS chip of a computer includes a resistor and an electronic switch. The electronic switch includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to a standby power supply of the computer. The second terminal is connected to a software reset pin of the CMOS chip. The third terminal is connected to a dual power supply of the computer via the resistor, and is connected to a hardware reset pin of the computer. The standby power supply is provided, and the first electronic switch is turned on before the computer is booted up. The software reset pin may be triggered to clear CMOS information of the CMOS chip upon the condition that the hardware reset pin is triggered.04-15-2010
20110254598VOLTAGE OPERATION SYSTEM - A voltage operation system is disclosed. The voltage operation system includes: a power on rest circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on rest circuit is used for generating a power on rest signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on rest circuit and the voltage detecting circuit, for outputting a operating signal. The electronic fuse circuit fuses or not according to a lock signal, a fuse signal, and the operating signal.10-20-2011
20110254597SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC INFORMATION DEVICE - The semiconductor integrated circuit according to the present invention includes a mode switching circuit for switching an operation mode of a main core circuit among a plurality of internal circuits between a normal operation mode and a stand-by mode; and a stand-by canceling circuit for instructing the mode switching circuit to cancel a stand-by mode, and the mode switching circuit and the stand-by canceling circuit are configured to operate in asynchronism with the system clock with stand-by voltage in the stand-by mode. Thus, the semiconductor integrated circuit is capable of achieving operations with reduced power consumption with restrained leakage current by further reducing power source voltage during a stand-by mode, while maintaining advantages of shortening a time required to return from the stand-by mode, and of requiring no additional circuitry, such as non-volatile memory, for returning from the stand-by mode and thus requiring no extra cost.10-20-2011
20110025383METHOD OF ENHANCING POWER SAVING IN AN INTEGRATED ELECTRONIC SYSTEM WITH DISTINCTLY POWERED ISLANDS OF FUNCTIONAL CIRCUITRIES AND RELATED DEVICE ARCHITECTURE - A method for power saving in an integrated circuit device may include defining an off-switchable analog circuit island including an internal clock generating circuit, and at power-on of the integrated circuit device, supplying to clocked digital circuits of the integrated circuit device an auxiliary clock from the external controller. The auxiliary clock has a frequency determined by the external controller and being lower than the root clock signal. The method includes supplying external reset commands to the integrated circuit device until an active functioning condition of the integrated circuit device is asserted, and interrupting the supply of the auxiliary clock and enabling supply of the root clock signal to the clocked digital circuits when the active functioning condition of the integrated circuit device is asserted.02-03-2011
20100060330POWER ON RESET GENERATING CIRCUIT AND METHOD THEREOF - The invention mainly relates to a power on reset signal generating circuit and method thereof wherein said reset signal remains as a constant being independent of rising or descending power or repeated switching. The power on reset signal circuit can be implemented by a conventional RC power on reset circuit together with a coupled N-type transistor switch to charge or discharge the capacitor inside the conventional RC power on reset circuit.03-11-2010
20080218224SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.09-11-2008
20110148482METHOD OF CHOOSING A FUNCTIONING MODE OF AN INTEGRATED CIRCUIT DEVICE AND RELATIVE DEVICE - A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold.06-23-2011
20090174444Power-on-reset circuit having zero static power consumption - A power-on-reset (POR) circuit having a zero or substantially zero current state while the supply voltage is in a predetermined, valid range is disclosed. The POR circuit includes a state machine, an oscillator, and output circuitry that are electrically coupled to one another and to a supply voltage. Output from the output circuitry is also provided to the integrated circuit to which the POR circuit is coupled. The state machine includes a plurality of sequential circuits such as latches, flip-flops, and the like that are electrically coupled in a cascade, to provide a ripple counter. The output circuitry is structured and arranged to reset or initialize all of the logic elements on the chip by generating a POR output logic HI (1) signal by Boolean operation of the logic circuitry signal of the state machine for all Boolean states except one. The oscillator is disabled when the POR output logic signal is LO (0), which causes the POR circuit to enter a zero or substantially zero current state.07-09-2009
20090174443Hard reset and manual reset circuit assembly - A simple inexpensive hard reset and manual reset circuit assembly that provides a delay time during reset for enabling other matched electronic devices to have sufficient time to reach ready status. The circuit assembly includes a power source, a first resistor, a first electric control switch, which has a control end and two bypasses being respectively connected to a reset terminal and a grounding terminal, a second resistor, a second electric control switch, which has a control end and two bypasses being respectively connected to the control end of the first electric control switch and the grounding terminal, a third resistor, a first capacitor, a second capacitor, a manual switch, which has two opposite ends respectively connected to the second capacitor and the grounding terminal, and a fourth resistor, which has two opposite ends respectively connected to the power source and the second end of the second capacitor.07-09-2009
20090206890RESET SIGNAL GENERATOR AND A METHOD FOR GENERATING RESET SIGNAL OF A SEMICONDUCTOR INTEGRATED CIRCUIT - A reset signal generator of a semiconductor integrated circuit includes a counter that counts a clock signal in response to activation of a power-up signal and activates a count-result signal when the counted value reaches a target value, and a reset signal generating unit that activates a reset signal in response to the activation of the count result signal.08-20-2009
20120306550SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.12-06-2012
20120306549SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a constant current circuit and a start-up circuit. The constant current circuit includes a first current mirror circuit including a first and second transistors; and a second current mirror circuit including a third transistor connected to a first node and a fourth transistor connected to a second node. The start-up circuit includes a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that controls the fifth based on a potential of the fourth node.12-06-2012
20090256599SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit.10-15-2009
20110012651POWER-ON RESET CIRCUIT, MODULE INCLUDING SAME, AND ELECTRONIC DEVICE INCLUDING SAME - A power-on reset circuit includes a charge-up circuit to charge a first capacitor after power is on, a first NOR circuit connected to an output terminal of the charge-up circuit and receive a power-on reset signal output from an output terminal of the power-on reset circuit, a first inverter connected to the first NOR circuit, a second capacitor connected between an input terminal of the first NOR circuit and an output terminal of the first inverter, a counter configured to count a clock, a clock selector configured to select whether to output or inhibit a clock signal based on an output signal from the counter, and a second inverter connected to the output terminal of the counter to output the power-on reset signal.01-20-2011
20090195273START-UP CIRCUIT FOR SMIA INPUT CLOCK BUFFER - A circuit for a buffer includes input and output nodes, in which the buffer provides a high level voltage output at the output node for a low level input leakage condition at the input node. The circuit includes a pull-up circuit, coupled to the input node, for providing a pull-up voltage to raise a common voltage level of an input signal. The buffer includes a transistor coupled to the input node, in which the transistor is turned on, in response to the pull-up voltage. A detector is coupled to the output node for detecting presence of the input signal. Upon the transistor turning on, the output node provides a buffered output signal corresponding to the input signal, and upon the detector detecting the presence of the input signal, the pull-up circuit is configured to remove the pull-up voltage. The input signal is an AC coupled signal having a peak-to-peak voltage excursion about a common DC voltage value. The input signal is an AC coupled clock signal adopted for standard mobile architecture (SMIA).08-06-2009
20100301908CIRCUIT FOR CONTROLLING PSON SIGNAL - A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.12-02-2010
20120062283SCAN-BASED RESET - Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.03-15-2012
20110156770AUTO-RESTART CIRCUIT AND AUTO-RESTART METHOD - Disclosed is an auto-restart circuit and auto-restart method.06-30-2011
20110156769POWER-UP SIGNAL GENERATION CIRCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up signal generation circuit includes a main driving unit configured to drive a power-up detection node according to power supply voltage level information; an auxiliary driving unit configured to additionally drive the power-up detection node according to temperature information; and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node in accordance with the operations of the main driving unit and the auxiliary driving unit.06-30-2011
20130154693TIMING CIRCUIT CALIBRATION IN DEVICES WITH SELECTABLE POWER MODES - Techniques are provided which may be implemented in various methods, apparatuses, and/or articles of manufacture for use by a device that is operable in a plurality of modes, including “higher power mode” and a “lower power mode”. A timing circuit may be set based, at least in part, on a phase value obtained from a signal from a ground-based transmitter, and operation of the device may be selectively transitioned to a lower power mode wherein the device uses the timing circuit. In certain example implementations, operation of the device to the lower power mode may be selectively transition and based, at least in part, on a determination that one or more attribute values satisfy a profile test indicating that the electronic device is likely to be within a characterized environment, and/or a determination that the electronic device is likely to be in a constrained motion state.06-20-2013
20090134922Start-up circuit for bias circuit - A start-up circuit for a bias circuit is disclosed. The start-up circuit uses a switch to provide an activating signal to pull the bias circuit out of the null mode. The switch is triggered by a pulse from an external pulse supply or a combined pulse generator. After the pulse, the bias circuit enters a steady operational state and the start-up circuit stops operating. Therefore the start-up circuit has advantages of wide supply range, no standby current, short start-up time and simple circuit topology.05-28-2009
20120062284LOW-VOLTAGE DATA RETENTION CIRCUIT AND METHOD - A low-voltage data retention circuit and method are provided. The circuit includes a reference voltage generating circuit generating a stable reference voltage, a voltage detecting circuit detecting a voltage of a power supply, a comparing circuit for comparing the detected voltage and the reference voltage, wherein when the detected voltage of the power supply is lower than the reference voltage, the comparing circuit generating a turn-off signal to turn off power consumption modules of an IC chip.03-15-2012
20080197895SYSTEM AND METHOD FOR POWER ON RESET AND UNDER VOLTAGE LOCKOUT SCHEMES - A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.08-21-2008
20110084740POWER-ON RESET CIRCUIT - A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.04-14-2011
20100289537SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON - An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.11-18-2010
20100244912CONTROLLER AND VOLTAGE DETECTION ENABLING CIRCUIT THEREOF - A voltage detection enabling circuit is disclosed. The voltage detection enabling circuit includes a reference voltage generating unit, an enabling protection unit, and an enabling judgment unit. The reference voltage generating unit is coupled to a driving voltage, and generates a reference voltage signal. The enabling protection unit receives the reference voltage signal and outputs an enabling judgment signal when the reference voltage signal is higher than a voltage parameter. Particularly, the voltage parameter is a component parameter of an electronic component. Then the enabling judgment unit determines whether an enabling signal is generated or not according to the enabling judgment signal and the driving voltage.09-30-2010
20100244911SUPPLY CIRCUITRY FOR SLEEP MODE - The invention concerns a supply circuitry system and method, including a supply circuitry arranged to control a power-up phase at the end of a sleep period of a circuit region of an integrated circuit, the supply circuitry comprising: first and second switches coupled between a supply rail and a supply node of the circuit region, the supply rail being coupled to receive a supply voltage (VDD) from a power supply unit; a comparator arranged to provide an output based on a comparison between a voltage at the supply node (VDD_INT) and a reference voltage (VREF); and control circuitry coupled to control terminals of the first and second switches and arranged to activate the first switch at the start of the power-up phase, and to activate the second switch once the output of the comparator indicates that the voltage at the supply node is greater than the reference voltage.09-30-2010
20120126864POWER-ON RESET - This document discusses, among other things, apparatus and methods for providing power-on reset (POR) functionality using an enable circuit. In an example, an apparatus can include a supply input configured to receive a supply voltage, an enable input configured to receive an enable signal, and an inversion network configured to control an enable output using the enable signal. The inversion network can include a delay element configured to delay a first transition of the enable output in response to a rising transition of the supply voltage.05-24-2012
20120161825START-UP SYSTEM AND METHOD FOR SWITCHING VOLTAGE REGULATOR - A switching voltage regulator system and method for providing a start-up mode. An on-chip voltage regulator can be integrated with an on-chip digital logic circuit to provide a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor and capacitor. A clock less start-up circuit automatically operates the on-chip voltage regulator in a start-up mode in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit. Such clock less start-up circuit provides soft start-up operation with respect to the on-chip voltage regulator without a clock signal.06-28-2012
20120256664POWER-ON-RESET CIRCUIT WITH LOW POWER CONSUMPTION - Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit includes a detector that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.10-11-2012
20090121753PROTECTIVE CIRCUIT FOR MICROPROCESSOR - A protective circuit for microprocessor comprises an input terminal, a bias circuit, a reset circuit, and an output terminal, wherein the bias circuit coupled to the input terminal is configured to receive an input signal and generate a bias signal. The reset circuit coupled to the bias circuit is configured to receive a bias signal and generate a reset signal. The output terminal outputs the reset signal to a reset pin of the microprocessor so that the microprocessor is reset and protected from getting failure.05-14-2009
20120074992CIRCUIT MODULE - A circuit module includes: control object circuits which start operations when a power supply voltage reaches a target value; a current sink circuit which consumes a current supplied thereto; and a power supply activation control unit which increases the current flowing into the current sink circuit at a predetermined rate before starting the operations of the control object circuits and which starts the operations of the control object circuits and simultaneously blocks the supply of the current to the current sink circuit in a case where an amount of the current flowing into the current sink circuit is equivalent to an amount of current to be increased by starting the operations of the control object circuits when the power supply voltage reaches the target value.03-29-2012
20120187985Low Power Brown Out Detector - A brown out detector (BOD), configured to provide a BOD reset in the event of a brown out event, is provided. The BOD includes means for tracking a reference voltage that is updated through duty cycling schemes so as to reduce power consumption, as well as means for detecting a falling flank of a supply voltage so as to optimize response times. More specifically, the BOD includes at least one track module, at least one sample module, at least one detector module and at least one comparator. The comparator is configured to compare a duty cycled tracked reference voltage with a duty cycled sampled reference voltage and to output a BOD reset if the tracked reference voltage is less than the sampled reference voltage. The comparator is further capable of exhibiting improved response times when a boost current is received. The boost current is provided by the detector module when the supply voltage falls beyond a predetermined threshold.07-26-2012
20080297211OPERATION MODE SETTING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT - An operation mode setting apparatus includes an operation mode setting control unit that discriminates the phase of a reference clock from the phase of a feedback clock and generates a locking suspension signal, and an operation mode setting unit that generates a locking completion signal in response to a pulse signal and a phase comparison signal under the control of a reset signal and the locking suspension signal.12-04-2008
20120268175ADAPTOR CIRCUIT FOR POWER SUPPLY - A adaptor circuit for a power supply includes a first comparison circuit, a timing circuit; and a second comparison circuit. An input of the first comparison circuit is electrically connected to a PS_ON terminal. The first comparison circuit includes a diode. An input of the second comparison circuit is electrically connected to the diode of the first comparison circuit via the timing circuit. When the PS_ON signal is powered on, the diode is off, and the timing circuit charges up in a predetermined time, and the second comparison circuit outputs a PWR_GOOD signal after the predetermined time. When the PS_ON signal is powered off, the diode turns on, and the timing circuit discharges, so the second comparison circuit stops outputting a PWR_GOOD signal.10-25-2012
20100231273SEMICONDUCTOR DEVICE - A semiconductor device has a first MOS transistor being connected between a signal terminal and a first power supply line and having a gate connected to a second power supply line; a first capacitive element connected between the signal terminal and the second power supply line; a second MOS transistor being connected between the signal terminal and the second power supply line and having a gate connected to a first terminal; a third MOS transistor being connected between the first power supply line and the first terminal and having a gate connected to the second power supply line; a fourth MOS transistor being connected between the first terminal and a second terminal and having a gate connected to the second power supply line; a second capacitive element connected between the first power supply line and the second terminal; and a fifth MOS transistor being connected between the second terminal and the second power supply line.09-16-2010
20120280727POWER-ON RESET CIRCUIT - A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.11-08-2012
20120092047POWER-ON RESET CIRCUIT - A power-on reset circuit including a voltage divider, a first transistor and a second transistor is provided. The voltage divider is electrically connected between a first source voltage and a first ground voltage, and generates a sensing voltage. A drain of the first transistor is electrically connected to a second source voltage, and a gate and a source of the first transistor are connected to each other. A conductive channel of the second transistor is the same with that of the first transistor, and a type of the second transistor is different from a type of the first transistor. Furthermore, a drain of the second transistor is electrically connected to the source of the first transistor. A gate of the second transistor receives the sensing voltage. A source of the second transistor is electrically connected to a second ground voltage.04-19-2012
20120092046LOW POWER POWER-ON-RESET (POR) CIRCUIT - In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit.04-19-2012
20120286833Power-On Reset Circuit - An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.11-15-2012
20130113532PROCESSING SYSTEM AND POWER CONTROL DEVICE THEREOF - A power control device is provided. The power control device includes a power supply unit, a reset unit, and a power control unit. The power supply unit determines whether a supplied voltage from an external voltage supply source is being provided to the power supply unit to generate a determination signal. The power supply unit further generates an operation voltage and a standby voltage according to the supplied voltage. The reset unit receives the determination signal and the standby voltage and generates a reset signal according to the determination signal and the standby voltage to activate a reset operation. The power control unit receives the reset signal and generates a power enabling signal according to the reset signal. The power supply unit outputs the operation voltage or does not according to the power enabling signal.05-09-2013
20130141144POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.06-06-2013
20110210771RECEIVING CIRCUIT AND RECEIVING SYSTEM - An output circuit (09-01-2011
20100283516VOLTAGE GENERATION CIRCUIT - A reference voltage generation circuit includes a driving control unit configured to output an enable signal during a first time period in response to a power-on reset (POR) signal, a reference voltage generation unit configured to have an initial operation determined in response to the enable signal and to output a reference voltage maintained at a constant voltage level after the first time period, and a reference voltage control unit configured to fix the voltage level of the reference voltage to a first voltage upon a voltage level of the reference voltage being increased to at least a set voltage level.11-11-2010
20100289536CIRCUIT FOR GENERATING POWER-UP SIGNAL OF SEMICONDUCTOR MEMORY APPARATUS - A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.11-18-2010
20120274369POWER-ON-RESET CIRCUIT AND RESET METHOD - Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage.11-01-2012
20110234268Apparatus and Method for Host Power-On Reset Control - A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.09-29-2011
20100315133POWER-UP CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.12-16-2010
20130187687POWER-ON RESET CIRCUIT AND METHOD OF USE - The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.07-25-2013
20090284289 METHOD OF IMPLEMENTING POWER-ON-RESET IN POWER SWITCHES - A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period,; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.11-19-2009
20120019292CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT - An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.01-26-2012
20120019291RESET CIRCUIT AND CONTROL APPARATUS INCLUDING THE RESET CIRCUIT - A reset circuit for resetting and terminating the resetting of a reset target includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), a gate drive circuit configured to switch a drain voltage of the n-channel MOSFET from a low level to a high level when a power supply voltage exceeds a predetermined threshold, a sink circuit configured to maintain the drain voltage at the low level by sinking a current flowing from a drain side of the n-channel MOSFET to the sink circuit, and a block circuit configured to block the current sinking to the sink circuit when the power supply voltage exceeds the predetermined threshold. The low level indicates a state where the reset target is in a reset state and the high level indicates a state where the reset state of the reset target is terminated.01-26-2012
20120019290INPUT CIRCUIT - An input terminal receives an external input signal. An input transistor is arranged such that the control terminal thereof is connected to the input terminal, and configured to change its state according to the input signal. An initializing transistor is arranged between the input terminal and the ground terminal. When the power supply for the input terminal is turned on, the control circuit turns on the initializing transistor, following which the control circuit turns off the initializing transistor.01-26-2012
20130194011POWER-ON RESET CIRCUIT - The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.08-01-2013
20130194009POWER ON RESET APPARATUS - A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.08-01-2013
20130194010SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.08-01-2013
20120086481POWER SUPPLY SYSTEM - A power supply system, for discharging a resume and reset (RSMRST) signal during the RSMRST signal pull down, includes a voltage regulating circuit, a delay circuit, a switch circuit, and a discharge circuit. The voltage regulating circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal once fully charged. The switch circuit receives the second voltage signal and then outputs a RSMRST signal. The discharge circuit discharges the delay circuit. The delay circuit is charged during a first state and discharged during a second state.04-12-2012
20130207696Low Voltage CMOS Power on Reset Circuit - An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.08-15-2013
20130207697DIGITAL POWER ON RESET CONTROLLER - A digital power-on reset circuit for an electronic device includes at least one reset register and a comparator circuit. The power-on reset circuit is incorporated into the electronic device and the comparator circuit is configured to compare values in the at least one reset register with at least one predetermined value when a power-on reset state is determined and generate a reset signal when the values do not match the at least one predetermined value.08-15-2013

Patent applications in class Responsive to power supply