Entries |
Document | Title | Date |
20080204088 | HIGH-SPEED DIVIDER WITH REDUCED POWER CONSUMPTION - A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off. | 08-28-2008 |
20080265953 | Frequency Divider - A frequency divider comprising, a first latch circuit ( | 10-30-2008 |
20080297209 | Circuits and Methods for Programmable Integer Clock Division with 50% Duty Cycle - Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. The present invention advantageously provides for a frequency divider structure that can be easily programmed to provide any integer divide ratio with a 50% duty cycle. | 12-04-2008 |
20080303561 | Frequency divider including latch circuits - A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source current, a second level for receiving a pair of input signals and for generating a pair of output signals, and a third level for receiving the source current and a pair of clock signals. The second level is coupled between the first level and the third level. The first level includes a first transistor having a source terminal and a substrate both coupled to a source voltage. The third level includes a plurality of transistors controlled by the pair of clock signals. Each transistor in the third level has a source terminal and a substrate both coupled to ground. | 12-11-2008 |
20090079472 | RATIO GRANULARITY CLOCK DIVIDER CIRCUIT AND METHOD - In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every I | 03-26-2009 |
20090079473 | FIFTY PERCENT DUTY CYCLE CLOCK DIVIDER CIRCUIT AND METHOD - In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every I | 03-26-2009 |
20090096494 | Circuit Arrangement For Generating A Complex Signal And The Use Of This Circuit Arrangement In A High-Frequency Transmitter Or Receiver - A circuit arrangement for generating an IQ signal which comprises an oscillator ( | 04-16-2009 |
20090102520 | DIRECT INJECTION-LOCKED FREQUENCY DIVIDER CIRCUIT WITH INDUCTIVE-COUPLING FEEDBACK ARCHITECTURE - A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module. These features allow the proposed frequency divider circuit to have higher operating frequency with wider frequency locking range, low power consumption, and small integrated circuit layout area. | 04-23-2009 |
20090108885 | Design structure for CMOS differential rail-to-rail latch circuits - A design structure including a CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes. | 04-30-2009 |
20090146699 | DUAL-MODULUS PRESCALER CIRCUIT OPERATING AT A VERY HIGH FREQUENCY - The dual-modulus prescaler circuit ( | 06-11-2009 |
20090153201 | DIFFERENTIAL MULTIPHASE FREQUENCY DIVIDER - A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one latch stage are connected to the corresponding differential D-inputs of the next latch stage. For even numbers of latch stages, the differential clock inputs of each are connected together and alternately to the divider clock input and its complement. The last differential Q-output is returned and cross-connected to the differential D-inputs of the first latch stage. For odd numbers of latch stages, the differential clock inputs of each are respectively connected in parallel to the divider clock input and its complement. The last differential Q-output is returned and straight-connected to the differential D-inputs of the first latch stage. | 06-18-2009 |
20090167373 | MULTI-PHASE FREQUENCY DIVIDER - A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change-of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches. | 07-02-2009 |
20090167374 | Jitter-Free Divider - A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase. | 07-02-2009 |
20090174441 | Peak Power Reduction Methods in Distributed Charge Pump Systems - A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage. | 07-09-2009 |
20090184739 | DUAL-INJECTION LOCKED FREQUENCY DIVIDING CIRCUIT - A dual-injection locked frequency dividing circuit is proposed, which is designed for integration to a gigahertz signal processing circuit system for providing a frequency dividing function to gigahertz signals. The proposed circuit architecture is characterized by the provision of a dual-injection interface module on the input end for dividing the input signal into two parts for use as two injection signals, wherein the first injection signal is rendered in the form of a voltage signal and injected through a direct injection manner to the internal oscillation circuitry, while the second injection signal is rendered in the form of an electrical current and injected through a resonant circuit to the internal oscillation circuitry. This feature allow the proposed frequency dividing circuit to have broad frequency locking range and low power consumption. | 07-23-2009 |
20090212833 | Frequency divider circuit - Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an output signal of the 3rd FF and an output signal of the 4th FF and outputs an output signal of a first value, when both inputs thereof are of a second value, the output signal of the third logic gate being supplied to an input of the 5th FF, an output signal of the 5th FF being fed back to an input of the 1st FF. | 08-27-2009 |
20090230999 | Clock Divider - There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. The true single phase logic clock divider is capable of reliably operating at frequencies of greater than or equal to two gigahertz. | 09-17-2009 |
20090251176 | FREQUENCY DIVIDER CIRCUITS - A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop. | 10-08-2009 |
20090256596 | FLIP-FLOP, FREQUENCY DIVIDER AND RF CIRCUIT HAVING THE SAME - A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples. | 10-15-2009 |
20090278574 | Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider - A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal. | 11-12-2009 |
20090289671 | FREQUENCY DIVIDER CIRCUIT - A frequency divider circuit comprises a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate. | 11-26-2009 |
20090322385 | DEVICE HAVING CLOCK GENERATING CAPABILITIES AND A METHOD FOR GENERATING A CLOCK SIGNAL - A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal. | 12-31-2009 |
20100079179 | Semiconductor Device - It is an object of the present invention to provide a semiconductor device that has a simple circuit structure, a small scale, and low power consumption, and can generate a desired clock signal. The semiconductor device has a clock generation circuit which generates a clock signal by dividing a modulated carrier wave, a divider circuit which generates a first divided signal by dividing a carrier wave, and a correction circuit which generates a second divided signal by further dividing the first divided signal, and has a function of performing correction for inverting the second divided signal in a period corresponding to a half period of the clock signal during modulation of the carrier wave and selecting whether the correction is performed or not. | 04-01-2010 |
20100109719 | PRESCALING STAGE FOR HIGH FREQUENCY APPLICATIONS - A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair. | 05-06-2010 |
20100123487 | DIVIDER CIRCUITRY - Divider circuitry for a phase-locked loop frequency synthesizer, the divider circuitry comprising
| 05-20-2010 |
20100123488 | DIGITAL PLL WITH KNOWN NOISE SOURCE AND KNOWN LOOP BANDWIDTH - A phase locked loop (PLL) based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The PLL is configured as an all digital PLL and includes a bang-bang phase frequency detector, digital loop filter, and digitally-controlled oscillator. The frequency translator is located in either the reference clock path for division or the PLL feedback loop path for multiplication. The SDM produces a predictable noise characteristic set with known stochastic properties which can be used to smooth any discontinuity in the bang-bang phase frequency detector. The predictable noise of the SDM will produce a dithering delay that eliminates any hard discontinuities. This allows for a bang-bang phase frequency detector based digital PLL. | 05-20-2010 |
20100134154 | ODD NUMBER FREQUENCY DIVIDING CIRCUIT - A method and a frequency dividing circuit ( | 06-03-2010 |
20100176851 | Pulse Width Modulation Circuit Capable of Linearly Adjusting Duty Cycle with Voltage and Related Method - A pulse width modulation circuit capable of linearly adjusting duty cycle with voltage, which comprises an input voltage source for generating an input voltage, a regulator for generating a regulated voltage, a first voltage-dividing unit for providing a first divided voltage, a second voltage-dividing unit for providing a second divided voltage, a third voltage-dividing unit for providing a third divided voltage, a voltage adder for adding the first divided voltage and the third divided voltage for generating a high level voltage, a waveform generator for generating an oscillating signal according to the high level voltage and the third divided voltage, and a comparator having a first input terminal coupled to the second voltage-dividing unit, a second terminal coupled to the waveform generator, and an output terminal for comparing the second divided voltage with the oscillating signal to output a pulse width modulation signal through the output terminal. | 07-15-2010 |
20100201408 | Digital Time Base Generator and Method for Providing a First Clock Signal and a Second Clock Signal - A digital time base generator and method for providing a first clock signal and a second clock signal in which a base clock signal having a base frequency is generated to provide two clock signals of slightly different frequencies with defined time or phase delay. Here, the base frequency is divided by a first integer to produce a first auxiliary signal, the frequency of the first auxiliary signal is multiplied by a factor to obtain the first clock signal, the base frequency is further divided by a second integer to produce a second auxiliary signal, and the frequency of the second auxiliary signal is multiplied by the factor to obtain the second clock signal. | 08-12-2010 |
20100207671 | FREQUENCY DIVIDING CIRCUIT - A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals. | 08-19-2010 |
20100207672 | SYSTEM TIMER AND A MOBILE SYSTEM INCLUDING THE SAME - A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count. | 08-19-2010 |
20100225365 | CLOCK DIVIDING CIRCUIT - A clock dividing circuit includes a control logic unit and a flip-flop. The control logic unit outputs an enable signal and a data signal according to a clock signal and a division ratio. The flip-flop outputs a divided clock signal based on the clock signal, the enable signal and the data signal. The clock signal can be directly outputted as the divided clock signal through the flip-flop. | 09-09-2010 |
20100253397 | FREQUENCY DIVIDER CIRCUIT - Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. | 10-07-2010 |
20100301906 | MULTIPHASE SIGNAL DIVIDER - A divider of an input multiphase signal by a given division factor so as to obtain an output multiphase signal, the divider having a circuit adapted to divide a first signal component of an input multiphase signal by an given division factor to obtain a first component of a output multiphase signal, and a plurality of N−1 devices including a first device adapted to sample the first component with a component of the input multiphase signal to obtain the component of the output multiphase signal corresponding to the one component of the input multiphase signal. Every other device of the plurality of N−1 devices is adapted to sample the component of the output multiphase signal of the preceding device with another component of the input multiphase signal, phase shifted by a further constant factor to obtain the corresponding component of the output multiphase signal. | 12-02-2010 |
20100308874 | CLOCK SWITCH CIRCUIT AND CLOCK SWITCH METHOD OF THE SAME - A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values. | 12-09-2010 |
20110001521 | Frequency Divider - This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path. | 01-06-2011 |
20110025381 | MULTI-PHASE CLOCK DIVIDER CIRCUIT - A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal. | 02-03-2011 |
20110050294 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to is determine a logic level of the frequency division control signal in response to the detected result. | 03-03-2011 |
20110050295 | SEMICONDUCTOR DEVICE - A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result. | 03-03-2011 |
20110128051 | Programmable Clock Divider - In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal. | 06-02-2011 |
20110133793 | CLOCK DIVIDER WITH SEAMLESS CLOCK FREQUENCY CHANGE - A clock divider circuit including a clock input, a clock selection input, a divider stage and a toggle stage is provided. The clock divider circuit provides an output clock based on a clock input received at the clock input. The clock selection input is coupled to the divider stage, and the divider stage is coupled to the toggle stage. A clock divide setting is updated at the clock selection input synchronously to an operation of the divider stage. In one implementation, for example, the clock divider setting is updated seamlessly. A method of transitioning an output clock signal is also provided. The method includes receiving an input clock signal and a first clock divide setting; providing an output clock signal having a first output clock frequency by dividing the input clock signal based upon the first clock divide setting utilizing a divider stage of a clock divider circuit; providing an updated second clock divide setting synchronously to an operation of the divider stage; and transitioning the output clock signal to a second output clock frequency based upon the updated second clock divide setting. A power management system is also provided. | 06-09-2011 |
20110148480 | Divider with Enhanced Duty Cycle for Precision Oscillator Clocking Sources - A divider is disclosed that presents an enhanced duty cycle for use with precision oscillators in clock sources. In one example, the invention includes a first divider chain to receive an input clock and produce a first divided output, a second divider chain to receive the input clock and produce a second divided output, and a combiner to combine the first and second divided output to produce a third divided output with a duty cycle greater than the first and second divided output. | 06-23-2011 |
20110187418 | CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND METHOD - A mask circuit ( | 08-04-2011 |
20110193596 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - A clock frequency divider circuit | 08-11-2011 |
20110215842 | PROGRAMMABLE DIGITAL CLOCK SIGNAL FREQUENCY DIVIDER MODULE AND MODULAR DIVIDER CIRCUIT - A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output. | 09-08-2011 |
20110234265 | Programmable Frequency Divider - A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be programmable by writing the N-bit value to a register. The divisor may be even or odd. During operation, the clock divider may decrement a counter down from an initial value (derived from the N-bit value representing the divisor) to a trigger value. When the trigger value is detected, the clock divider may cause the output clock to toggle. The trigger value may depend on whether the divisor is even or odd. The clock divider may be re-programmed during operation by writing a new N-bit value into the register. Re-programming may include changing the divisor from an even value to an odd value. | 09-29-2011 |
20110234266 | FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL - A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. | 09-29-2011 |
20120001664 | CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME - A clock divider circuit has a plurality of dividers for which dividing ratios are settable, a preset register group that stores the dividing ratios set for the plurality of dividers, and a selector that selects a single preset register within the preset register group, and imparts the dividing ratios stored in the selected preset register to the plurality of dividers. | 01-05-2012 |
20120001665 | FRACTIONAL FREQUENCY DIVIDER - A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period. | 01-05-2012 |
20120007638 | SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION - A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts. | 01-12-2012 |
20120019288 | FREQUENCY DIVIDER CIRCUIT - Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. | 01-26-2012 |
20120025877 | LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME - A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods. | 02-02-2012 |
20120032715 | HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 02-09-2012 |
20120081156 | High Speed RF Divider - High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors, The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring. | 04-05-2012 |
20120126862 | FREQUENCY DIVIDER WITH PHASE SELECTION FUNCTIONALITY - A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals. | 05-24-2012 |
20120161823 | FREQUENCY DIVISION OF AN INPUT CLOCK SIGNAL - Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop. In a first mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop so that each first type of edge causes the signal provided to the data input of the flip flop to toggle such that the output of the flip flop has a frequency which is substantially half of the frequency of the input clock signal, and wherein in a second mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop with the exception that toggling of the signal provided to the data input of the flip flop is selectively prevented despite toggling of the output of the flip flop on an edge of the first type such that the output of the flip flop has a frequency which is at most a third of the frequency of the input clock signal. The feedback circuitry is arranged to operate independently from a second type of edge of the input clock signal in providing the signal to the data input of the flip flop, such that the output of the flip flop is independent from the duty cycle of the input clock signal. | 06-28-2012 |
20120169382 | DIVIDING METHOD AND DIVIDING APPARATUS FOR GENERATING NOISE-REDUCED FREQUENCY DIVIDED SIGNAL BY UTILIZING NOISE REDUCING CIRCUIT - A dividing apparatus is provided. The dividing apparatus includes a frequency dividing circuit and a noise reducing circuit. The frequency dividing circuit is arranged to receive a first clock signal and generate a frequency divided signal corresponding to the first clock signal. The noise reducing circuit is coupled to the frequency dividing circuit and arranged to receive a second clock signal and the frequency divided signal, and is utilized for referring to the second clock signal and the frequency divided signal to reduce noise of the frequency divided signal to generate a noise-reduced frequency divided signal. The first and second clock signals may be identical clock signals or different clock signals. | 07-05-2012 |
20120229178 | Method and apparatus for calibrating frequency - Methods and apparatuses for calibrating frequency are provided according to the embodiment of the present disclosure. A method for calibrating frequency may comprise: providing an actual frequency of a reference frequency signal and a frequency offset between the actual frequency of the reference frequency signal and the expected frequency of the reference frequency signal; determining a frequency division ratio according to the frequency of a target frequency signal and the expected frequency of the reference frequency signal; determining a calibration value of the frequency division ratio according to the frequency offset; providing a calibrated frequency division ratio by calibrating the frequency division ratio according to the calibration value; and providing the target frequency signal by dividing the frequency of the reference frequency signal according to the calibrated frequency division ratio. | 09-13-2012 |
20120229179 | PLL CIRCUIT AND OPTICAL DISC APPARATUS - A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data. | 09-13-2012 |
20120229180 | Method and Device for Generating Low-Jitter Clock - The present invention discloses a method for generating a low jitter clock, including: inserting a time delay in each low-speed clock period to finely adjust a high-speed clock, and then performing frequency division operation on the adjusted high-speed clock to obtain the required low-speed clock. The present invention also discloses an apparatus for generating the low jitter clock at the same time. By using the method and the apparatus, the jitter of the low-speed clock can be decreased. The implementation method is simple and convenient and the device cost is saved. | 09-13-2012 |
20120235714 | FREQUENCY SYNTHESIZER PRESCALER SCRAMBLING - Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a plurality of multiplexers connected in series with the clock signal, each having a plurality of inputs of different phase delays. The apparatus also includes a delta sigma modulator connected to control inputs on the plurality of multiplexers. The delta sigma modulator is adapted to repeatedly select different ones of the pluralities of inputs of different phase delays in the plurality of multiplexers to change a divide ratio between the clock signal and an output of the plurality of multiplexers. The apparatus also includes a multiplexer usage accumulator connected to the delta sigma modulator to track usage of the plurality of multiplexers. The apparatus also includes a scrambler circuit connected between the delta sigma modulator and the control inputs on the plurality of multiplexers, adapted to control settings in the plurality of multiplexers based at least in part on the multiplexer usage accumulator. | 09-20-2012 |
20120249192 | CLOCK GENERATION CIRCUIT, PROCESSOR SYSTEM USING SAME, AND CLOCK FREQUENCY CONTROL METHOD - A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal. | 10-04-2012 |
20120262207 | Clock Generation System - A clock generation system for deriving a second clock signal from a first clock signal with a predetermined clock frequency ratio, where the first clock frequency is divided by a first integer, the second clock signal is divided by a second integer, an error signal is generated by comparing the division results, a voltage-controlled oscillator is controlled in dependence on said error signal to generate the second clock signal, and a switch is provided for alternately switching each of the clock signals to a single frequency divider or for alternately switching one of the clock signals to one of two frequency dividers and simultaneously switching the other one of the clock signals to the other one of the two frequency dividers to eliminate errors that may result from processing the two clock signals in different circuit sections. | 10-18-2012 |
20120268170 | SEMICONDUCTOR DEVICE HAVING GEAR DOWN MODE, METHOD OF CONTROLLING SAME, AND INFORMATION PROCESSING SYSTEM - Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal. | 10-25-2012 |
20120286830 | Clock Generation System - A clock generation system for generating first and second clock signals at slightly different clock frequencies comprising a clock signal generator providing the first clock signal, frequency dividers dividing the clock frequencies by integers to produce auxiliary signals, a timer for measuring a first time lag between first signal edges of the auxiliary signals and a second time lag between second signal edges of the auxiliary signals, a comparator device for providing an error signal by comparing the difference between the measured time lags with a predetermined time value, and a voltage-controlled oscillator controlled in dependent on the error signal to generate the second clock signal. | 11-15-2012 |
20120286831 | CIRCUIT AND METHOD FOR GENERATING A CLOCK SIGNAL - A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator. | 11-15-2012 |
20120299626 | DIVIDER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided. | 11-29-2012 |
20130002314 | METHOD AND APPARATUS FOR LOW JITTER DISTRIBUTED CLOCK CALIBRATION - A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated. | 01-03-2013 |
20130015891 | DYNAMIC DIVIDE BY 2 WITH 25% DUTY CYCLE OUTPUT WAVEFORMS - Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state. | 01-17-2013 |
20130021068 | Low-Voltage High-Speed Frequency Divider with Reduced Power Consumption - A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal. | 01-24-2013 |
20130021069 | DIRECT DIGITAL SYNTHESIZER FOR REFERENCE FREQUENCY GENERATION - A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator. | 01-24-2013 |
20130021070 | LOW-POWER FREQUENCY DIVIDERS - A bias-shaping circuit for adjusting power consumption in a frequency divider to a temperature-dependent minimum includes a temperature-dependent bias source for producing a temperature-dependent bias. The bias is combined with an input signal to create an output bias. The output bias changes in response to a change in temperature to compensate for at least a portion of a temperature-induced change in the frequency divider, thereby adjusting power consumption in the frequency divider to a temperature-dependent minimum. | 01-24-2013 |
20130043913 | FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL - A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal. | 02-21-2013 |
20130049820 | CLOCK DIVIDER UNIT - A clock divider unit includes a plurality of divider circuits which divides a common reference clock, and a gate circuit disposed before the plurality of divider circuits. The reference clock is supplied to the divider circuits via the gate circuit after a reset state of each divider circuit is released so that dividing action of each divider circuit is allowed. | 02-28-2013 |
20130082748 | PROGRAMMABLE DIVIDER - A technique includes controlling a modulus of a programmable divider, including selectively activating and deactivating cells of the divider. The activation for at least one of the cells includes configuring an output signal of the cell to exhibit a predetermined signal state when the cell transitions from a deactivated state to an activated state. | 04-04-2013 |
20130099833 | INTEGRATED CIRCUIT CHIP AND SYSTEM HAVING THE SAME - An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period. | 04-25-2013 |
20130106472 | INTEGRATED CIRCUIT | 05-02-2013 |
20130127501 | SPREAD SPECTRUM CLOCK GENERATORS - Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio. | 05-23-2013 |
20130147526 | METHODS OF CONTROLLING CLOCKS IN SYSTEM ON CHIP INCLUDING FUNCTION BLOCKS, SYSTEMS ON CHIPS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero. | 06-13-2013 |
20130176060 | Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing - This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence. | 07-11-2013 |
20130187685 | DITHER CONTROL CIRCUIT AND DEVICES HAVING THE SAME - A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal. | 07-25-2013 |
20130194008 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. | 08-01-2013 |
20130214826 | FULLY DIGITAL METHOD FOR GENERATING SUB CLOCK DIVISION AND CLOCK WAVES - The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free. | 08-22-2013 |
20130222016 | Digital PLL Circuit and Clock Generator - A circuit according to the present invention includes: an oscillator; an divider; a time-to-digital converter comparing the phase and frequency of a reference clock signal REF from the divider with an internal clock signal and outputting digital data D | 08-29-2013 |
20130278302 | CLOCK SIGNAL GENERATOR - Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate. | 10-24-2013 |
20130293271 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal. | 11-07-2013 |
20130293272 | High Speed RF Divider - High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring. | 11-07-2013 |
20140070853 | RF LOGIC DIVIDER - An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch. | 03-13-2014 |
20140091841 | APPARATUS AND METHODS FOR CLOCK CHARACTERIZATION - A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement. | 04-03-2014 |
20140111256 | DESERIALIZERS - Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal. | 04-24-2014 |
20140159780 | DATA INTERFACE CLOCK GENERATION - In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data. | 06-12-2014 |
20140176201 | TIME-INTERLEAVED DIGITAL-TO-TIME CONVERTER - A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage. | 06-26-2014 |
20140184281 | SYSTEM, A METHOD AND A COMPUTER PROGRAM PRODUCT FOR ELECTRONIC SUB-INTEGER FREQUENCY DIVISION - An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal. | 07-03-2014 |
20140240009 | State Machine for Low-Noise Clocking of High Frequency Clock - Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates. | 08-28-2014 |
20140240010 | CLOCK CIRCUIT FOR A MICROPROCESSOR - A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output. | 08-28-2014 |
20140247072 | CORRECTION CIRCUIT AND REAL-TIME CLOCK CIRCUIT - The present invention provides a correction circuit. The correction circuit includes a frequency dividing circuit, a frequency dividing coefficient operation circuit, a built-in temperature collection circuit, and a power-on and power-off detection circuit. The built-in temperature collection circuit is configured to collect a temperature of the chip; the power-on and power-off detection circuit is configured to detect power-on and power-off of the chip; the frequency dividing coefficient operation circuit is configured to calculate, according to the temperature of the chip collected by the built-in temperature collection circuit when the power-on and power-off detection circuit detects that the chip is powered off, a frequency dividing coefficient, and output the frequency dividing coefficient to the frequency dividing circuit; and the frequency dividing circuit is configured to provide, according to the frequency dividing coefficient output by the frequency dividing coefficient operation circuit, a timing pulse for a real-time clock. | 09-04-2014 |
20140247073 | M-ARY Sequence Clock Spreading - The invention concerns a device for providing a spread frequency clock signal, comprising: -an input ( | 09-04-2014 |
20140247074 | CLOCK GENERATION CIRCUIT, PROCESSOR SYSTEM USING SAME, AND CLOCK FREQUENCY CONTROL METHOD - A microcomputer includes a register that stores division ratio setting information, a frequency divider that determines first and second division ratios based on the division ratio setting information, frequency-divides a first clock having a first frequency at the first division ratio, and frequency-divides a second clock having a second frequency at the second division ratio, and a CPU. The first and second division ratios are determined in such a manner that a frequency of the first clock that is frequency-divided at the first division ratio and a frequency of the second clock that is frequency-divided at the second division ratio are made equal to each other. | 09-04-2014 |
20140253188 | DIVIDED CLOCK GENERATION DEVICE AND DIVIDED CLOCK GENERATION METHOD - A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals. | 09-11-2014 |
20140266328 | FREQUENCY SYNTHESIS WITH GAPPER - Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal. | 09-18-2014 |
20140306740 | TIME-INTERLEAVED MULTI-MODULUS FREQUENCY DIVIDER - Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies. | 10-16-2014 |
20140340130 | Clock Generation Using Fixed Dividers and Multiplex Circuits - Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block. | 11-20-2014 |
20140361814 | High Speed Latch - An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal. | 12-11-2014 |
20140375363 | FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP - A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2. | 12-25-2014 |
20140375364 | FREQUENCY SYNTHESIS WITH GAPPER AND MULTI-MODULUS DIVIDER - Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal. | 12-25-2014 |
20150015310 | CLOCK DELAY DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time. | 01-15-2015 |
20150015311 | FRACTIONAL FREQUENCY DIVIDER CIRCUIT - A fractional frequency divider circuit includes: a frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N; a clock addition circuit configured to add one clock to an output of the frequency divider circuit; a counter that counts the number of cycles of the output of the frequency divider circuit by a carry of the frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the frequency divider circuit as an output clock when the match is not detected. | 01-15-2015 |
20150015312 | INTEGER FREQUENCY DIVIDER AND PROGRAMMABLE FREQUENCY DIVIDER CAPABLE OF ACHIEVING 50% DUTY CYCLE - An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock. | 01-15-2015 |
20150116011 | HIGH-SPEED DIVIDE-BY-1.5 CIRCUIT WITH 50 PERCENT DUTY CYCLE - A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry. | 04-30-2015 |
20150311888 | CLOCK FREQUENCY MODULATION METHOD AND CLOCK FREQUENCY MODULATION APPARATUS - Embodiments of the present invention provide a clock frequency modulation method and a clock frequency modulation apparatus. The method includes: determining N digital clocks according to a first digital clock of a system, where the N digital clocks includes a second digital clock and N-1 digital clocks except the second digital clock, and a sum of frequency ratios of the first digital clock to each of the N-1 digital clocks is equal to N-1 times a frequency ratio of the first digital clock to the second digital clock, where N is an integer greater than 2; and fitting, during a modulation period by using the N digital clocks, the first digital clock into the periodic second digital clock. The embodiments of the present invention use a clock frequency modulation technology to make energy concentrated in a frequency spread to a wider frequency range. | 10-29-2015 |
20150333758 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor device includes an operation unit (CPU) provided in a semiconductor chip and a temperature sensor (TS) that measures a temperature of the semiconductor chip. The semiconductor device compares a measured temperature (Ta) measured by the temperature sensor (TS) with a predetermined reference temperature (Tref). When the measured temperature (Ta) is higher than the reference temperature (Tref), the semiconductor device switches a frequency of an operation clock to be supplied to the operation unit (CPU) from a first frequency to a second frequency higher than the first frequency. | 11-19-2015 |
20150341020 | CIRCUIT FOR GENERATING A VOLTAGE WAVEFORM - A circuit for generating a voltage waveform at an output node. The circuit includes a voltage rail connected to the output node via a voltage rail switch; an anchor node connected to the output node via an inductor and a bidirectional switch, wherein the bidirectional switch includes two or more transistors connected in series; and a control unit configured to change the voltage at the output node by controlling the voltage rail switch and the bidirectional switch so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance. The circuit may be included in an apparatus for use in processing charged particles, e.g. for use in performing mass spectrometry or ion mobility spectrometry. | 11-26-2015 |
20150358004 | D-TYPE FLIP-FLOP AND CLOCK GENERATING CIRCUIT - A D-type flip-flop according to embodiments comprises: a transmission element configured in a slave latch, the transmission element fetching an output of a first latch circuit and outputting the fetched output to a first node, based on a clock signal; a first latch circuit constituting element configured in the first latch circuit, the first latch circuit giving an output of one logical value to the first node through the transmission element with the output fixed in a second mode; and a second latch circuit constituting element configured in the second latch circuit that holds a signal which appears at the first node, the second latch circuit constituting element giving an output of other logical value to the first node based on the clock signal with the output fixed in the second mode. | 12-10-2015 |
20160013799 | APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION FOR INTER-DIE SYNCHRONIZED DATA TRANSFER | 01-14-2016 |
20160026208 | HIGH FREQUENCY OSCILLATOR WITH SPREAD SPECTRUM CLOCK GENERATION - Devices, systems, and methods for spread spectrum clock generation are disclosed. The devices, systems, and methods generate a clock signal at a frequency and generate a voltage output based on the frequency of the clock signal, wherein the generated voltage output is indicative of the frequency of the generated clock signal. The devices, systems, and methods also compare the frequency of the clock signal generated to a desired frequency output by comparing the generated voltage output to a voltage reference and adjust the frequency of the clock signal generated based on the results of the comparison. | 01-28-2016 |
20160036455 | SYSTEM AND METHOD FOR CLOCK GENERATION WITH AN OUTPUT FRACTIONAL FREQUENCY DIVIDER - A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ). | 02-04-2016 |
20160072508 | SHARED DIVIDE BY N CLOCK DIVIDER - A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals. | 03-10-2016 |
20160079984 | DEVICE FOR GENERATING A CLOCK SIGNAL BY FREQUENCY MULTIPLICATION - A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal. | 03-17-2016 |
20160085260 | APPARATUSES AND METHODS FOR PROVIDING CLOCK SIGNALS - Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode. | 03-24-2016 |
20160087617 | SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR CONTROLLING CLOCK SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed. | 03-24-2016 |
20160087620 | APPARATUS FOR MANAGING CLOCK DUTY CYCLE CORRECTION (DCC) - Embodiments of the present invention disclose an apparatus for managing clock duty cycle. The apparatus comprises a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle, a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof, a frequency divider for generating a signal with a 50% duty cycle, a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof and an OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal. | 03-24-2016 |
20160087636 | CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF - A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit. | 03-24-2016 |
20160099716 | CONTROL DEVICE FOR CLOCK GENERATION CIRCUIT, CONTROL METHOD FOR CLOCK GENERATION CIRCUIT, AND CLOCK GENERATION CIRCUIT - A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device. | 04-07-2016 |
20160118962 | SIGNAL GENERATING SYSTEM AND SIGNAL GENERATING METHOD - A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer. | 04-28-2016 |
20160142059 | Differential Odd Integer Divider - A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits. | 05-19-2016 |
20160142066 | FREQUENCY DIVISION CLOCK ALIGNMENT - Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal; at a first leaf node of the clock distribution network, detecting a reference event and generating a synchronizing signal based on the detection of the reference event; passing the synchronizing signal along a synchronizing signal path from the first leaf node to the root node via one or more clocked storage cells, each storage cell being clocked from a corresponding point within the clock distribution network; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal resulting in the second clock signal received at the first leaf node being synchronized to the detected reference event. | 05-19-2016 |
20160142067 | FREQUENCY DIVISION CLOCK ALIGNMENT USING PATTERN SELECTION - Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal. | 05-19-2016 |
20160156364 | Fractional Dividing Module and Related Calibration Method | 06-02-2016 |
20160164464 | SIGNAL PROCESSING CIRCUIT FOR MITIGATING PULLING EFFECT AND ASSOCIATED METHOD - A signal processing circuit has a first mixer, a first amplifier, and a pulling effect mitigation circuit. The first mixer mixes a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor. The first amplifier amplifies the first output signal, and generates an amplified output signal at an output terminal of the first amplifier. The pulling effect mitigation circuit is coupled to the output terminal of the first amplifier, and generates a compensation signal to the output terminal for reducing at least an N | 06-09-2016 |
20160164533 | FREQUENCY DIVIDER AND PHASE-LOCKED LOOP INCLUDING THE SAME - A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one. | 06-09-2016 |
20160173110 | SEMICONDUCTOR DEVICE AND CLOCK CORRECTION METHOD | 06-16-2016 |
20160182031 | SEMICONDUCTOR APPARATUS | 06-23-2016 |
20160182056 | SYSTEM AND METHOD FOR PROVIDING PROGRAMMABLE SYNCHRONOUS OUTPUT DELAY IN A CLOCK GENERATION OR DISTRIBUTION DEVICE | 06-23-2016 |
20160197599 | FREQUENCY DIVIDER, CLOCK GENERATING APPARATUS, AND METHOD CAPABLE OF CALIBRATING FREQUENCY DRIFT OF OSCILLATOR | 07-07-2016 |