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Current driver

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327100000 - SIGNAL CONVERTING, SHAPING, OR GENERATING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
327109000 Having semiconductive load 275
327111000 Having capacitive load 32
327110000 Having inductive load (e.g., coil, etc.) 20
Entries
DocumentTitleDate
20130043911Semiconductor Device and Electronic Device Including Semiconductor Device - It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.02-21-2013
20130043910DRIVER CIRCUIT FOR DRIVING A LOAD CIRCUIT - Driver circuits (02-21-2013
20100052737SOURCE DRIVING CIRCUIT FOR PREVENTING GAMMA COUPLING - During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect.03-04-2010
20100164559POWER-ON CIRCUIT - The power-on circuit includes a first I/O voltage detector configured to detect whether or not an I/O voltage is applied and output an I/O voltage detection signal based on the detected result, a second I/O voltage detector configured to detect when the applied I/O voltage becomes a reference level value and output a cut signal based on the detected result, a core voltage detector configured to detect whether or not a core voltage is applied and output a core voltage detection signal based on the detected result, and a power-on signal generator configured to generate a power-on signal based on the I/O voltage detection signal, the cut signal and the core voltage detection signal and forcibly generate the power-on signal if the I/O voltage is stabilized later than the core voltage.07-01-2010
20100013524Load Driving Circuit - A load driving circuit comprising: a bias current circuit configured to generate a bias current having a current value corresponding to a level of a control signal; a control circuit configured to control the level of the control signal so that the bias current is increased and thereafter decreased, when an input signal reaches one logic level; and a driving circuit configured to raise an output voltage for driving a load to a higher logic level in a time corresponding to the current value of the bias current, when the input signal reaches the one logic level, and lower the output voltage to a lower logic level, when the input signal reaches the other logic level.01-21-2010
20090085614Circuits and methods for programming integrated circuit input and output impedances - An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.04-02-2009
20080258779SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit, has a current source having one end connected to a power supply and outputting a reference current; a first MOS transistor having one end connected to an other end of the current source and being diode-connected; a second MOS transistor having a gate connected to a gate of the first MOS transistor and passing an output current obtained by current-mirroring the reference current; a first variable resistor connected between an other end of the first MOS transistor and a ground; a resistive component connected between an other end of the second MOS transistor and the ground; and a first operational amplifier fed with a first potential of the other end of the first MOS transistor and a second potential of the other end of the second MOS transistor and outputting a signal for controlling a resistance value of the first variable resistor to equalize the first potential and the second potential, wherein the resistance value of the first variable resistor is controlled based on the output signal of the first operational amplifier.10-23-2008
20080258778CURRENT MIRROR CIRCUIT - The invention relates to a current mirror circuit (10-23-2008
20110193595OUTPUT DRIVER CIRCUIT - Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN08-11-2011
20090121751Write Driver Circuit - A write driver circuit comprising a first transistor comprising a first source/drain terminal coupled to a first output, a second source/drain terminal coupled with a first reference potential, and a gate terminal; a second transistor comprising a first source/drain terminal coupled to a second output, a second source/drain terminal coupled with the first reference potential, and a gate terminal; and a gate voltage generator coupled to the gate terminals of the first and second transistors.05-14-2009
20090121750Constant Current Drive Device - An object of the present invention is to eliminate fluctuation in the value of the constant current I even if there is characteristic fluctuation in field effect transistors and at the same time, to improve the power consumption. There are provided with a plurality of current mirror circuits consisting of those on the reference side and on the mirror side; current holding capacitors 05-14-2009
20100073037OUTPUT IMPEDANCE CONTROL CIRCUIT - An external resistive element is used to provide a substantially constant output impedance for multiple drivers disposed on an IC. The drivers may operate at different supply voltages. Accordingly, the parameters which depend on the driver output impedance, such as rise/fall time, propagation delay, and the like are made substantially constant and independent of the semiconductor process variations, operating supply voltages, and the temperature. The substantially constant output impedance maintains the stability of the crossing point of a true and its complementary clock signal in high-speed applications, such as in the drivers used in charge-coupled devices. A number of feedback loops are used together with the external resistive element to achieve the substantially constant output impedance. The feedback loops compensate for the ageing effects, temperature gradients and changes in the operating conditions of the IC.03-25-2010
20100073036HIGH-SPEED LOW-VOLTAGE DIFFERENTIAL SIGNALING SYSTEM - A system and a method for communicating data at a rate exceeding about a gigabit per second is described. The system may include circuitry and a current-sourcing module. The circuitry may include an output couplable to a load. The circuitry may output from the output a low voltage differential signal having a first current that drives the load from a first voltage at a first time to a second voltage at a second time. The current-sourcing module may apply a second current to the output at a third time, which occurs03-25-2010
20100073038Method and apparatus for reducing transmitter AC-coupling droop - As part of a transmitter and receiver system a droop compensator is provided between the channel isolation device and the driver system to compensate for reduced transition densities. The droop compensator is configured to improve power transfer to the channel in response to reductions in transition density without affecting power transfer during periods of high transition density. The droop compensator creates an impedance mismatch between the matching circuit and driver in relation to the line impedance. The droop compensator may comprise passive elements, such as capacitors, inductors, or resistor, or active elements including transistors or power control modules. The droop compensator may be configured to operate with transformer line couplers or capacitor line couplers, and either current drivers or voltage drivers.03-25-2010
20130076404LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVING CIRCUIT AND ELECTRONIC DEVICE COMPATIBLE WITH WIRED TRANSMISSION - A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal.03-28-2013
20100039144CURRENT DRIVER CIRCUIT - An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.02-18-2010
20090051393Low side driver - An output driver circuit has an input, an output node, and first and second transistors coupled in series between the output node and a first source of operating potential. Parasitic diodes of the first and second transistors are anti-serially coupled. The output driver circuit has first and second control circuits coupled to control the first and second transistors respectively. The first transistor is controlled as a controlled current source depending on a signal at the input during normal conditions when the current that flows through the output is in a first direction, and the second control circuit controls the second transistor to prevent unwanted DC current at the output from flowing through the output in a second direction. The first and second transistors are also controlled to limit unwanted transient currents during an EMC disturbance substantially symmetrically.02-26-2009
20130082745DRIVING CIRCUIT AND DRIVING CONTROLLER CAPABLE OF ADJUSTING INTERNAL IMPEDANCE - A driving circuit includes a power supply, a plurality of conductive paths and a plurality of driving controller. The power supply is configured for providing a predetermined voltage. The conductive paths are connected to the power supply to receive the predetermined voltage. The driving controllers are connected to the conductive paths correspondingly. A first driving controller of the driving controllers has a first internal circuit configured for employing an internal voltage to perform functions provided by the first driving controller, and a resistance adjustment unit. The resistance adjustment unit is connected between a special conductive path and the first internal circuit. The second driving controller has a second internal circuit configured for employing a second internal voltage to perform functions provided by the second driving controller. A resistance value of the resistance adjustment unit is adjustable to make the first internal voltage same to the second internal voltage.04-04-2013
20130082744Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers - A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.04-04-2013
20130033290APPARATUSES AND METHODS OF COMMUNICATING DIFFERENTIAL SERIAL SIGNALS INCLUDING CHARGE INJECTION - Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.02-07-2013
20130033291MULTI-OUTPUT-RESISTANCE SWITCH DRIVER CIRCUITS - A switch circuit can include an impedance selection switch and a multi-output-resistance switch driver. The impedance selection switch can electrically connect an impedance to an input of an amplifier in response to a driver output signal, and include at least one transistor. The multi-output-impedance switch driver may provide the driver output signal to the switch, and have a first, relatively higher output resistance when providing a first logic state of the driver output signal to turn on the switch, and a second, relatively lower output resistance when providing a second logic state of the driver output signal to turn off the switch. The ratio of the first output resistance to the second output resistance can be greater than a selected predetermined ratio value.02-07-2013
20100045349PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.02-25-2010
20100102855BUFFER DEVICE - In a buffer device a cross couple circuit includes a first power synthesis section in which a source of a first source follower and a drain of a first source-grounded amplifier are connected and a second power synthesis section in which a source of a second source follower and a drain of a second source-grounded amplifier are connected. A first bias circuit adjusts voltage of gates of the first source-grounded amplifier and the second source-grounded amplifier so as to make common-mode voltage of output from the first power synthesis section and output from the second power synthesis section equal to reference voltage. A second bias circuit applies compensation voltage to gates of the first source follower and the second source follower so as to control variation in voltage applied to the gates of the first source follower and the second source follower.04-29-2010
20130038354Discharge Path Circuit of an Input Terminal for Driver IC - Disclosed is a discharge path circuit of input terminal for a driver IC (Integrated Chip), the circuit providing a discharge path to the input terminal of the driver IC including a power input port connected to a first input and an operation mode selection port connected to a second input, the discharge path circuit including an LC (Inductance Capacitance) filter interconnected between the first input and the power input port to filter noise on a power source, and a resistance element interconnected between the first input and a ground terminal, wherein the resistance element provides a discharge path for discharging power charged by the input terminal of the driver IC.02-14-2013
20100109716SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.05-06-2010
20090045851DEVICE FOR DRIVING SWITCHING ELEMENTS - A device for driving switching elements is provided with a potential detector 02-19-2009
20130049812MONOLITHIC HIGH-SIDE SWITCH CONTROL CIRCUITS - A high-side switch control circuit is provided. The high-side switch control circuit includes an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a current source. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp the maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The current source is coupled to the level-shifting transistor. The current source limits the maximum current of the level-shifting transistor.02-28-2013
20130049811HIGH EFFICIENCY DRIVING CIRCUIT - A high efficiency driving circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The first P-type metal-oxide-semiconductor transistor charges a third terminal of the first P-type metal-oxide-semiconductor transistor according to a first control signal, and the first N-type metal-oxide-semiconductor transistor discharges the third terminal of the first P-type metal-oxide-semiconductor transistor according to a second control signal. A high voltage level of the first control signal is at a first voltage, and a low voltage level of the first control signal is at a third voltage; a high voltage level of the second control signal is at a fourth voltage, and a low voltage level of the second control signal is ground.02-28-2013
20130088265GATE DRIVER ON ARRAY, SHIFTING REGESTER AND DISPLAY SCREEN - The embodiment of the present disclosure relates to a technical field of liquid crystal display, and particularly, to a gate driver on array, a shifting register and a display screen. The gate driver on array comprises: a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor and a pulling-down module, the pulling-down module is connected among a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal, and is connected with a low voltage signal terminal, for maintaining the first node and the output terminal being in a low level during a non-operation period of the gate driver on array. Thus, the gate driver on array may achieve a bidirectional scan by designing the functions of the input terminal and the reset terminal in the gate driver on array as being implemented symmetrically, without changing a charging-discharging characteristic of nodes, which ensures a reliability and stabilization of the circuit.04-11-2013
20130088264System, Drivers for Switches and Methods for Synchronizing Measurements of Analog-to-Digital Converters - A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.04-11-2013
20090302897Driver circuit having high reliability and performance and semiconductor memory device including the same - Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node.12-10-2009
20120218008TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING - Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.08-30-2012
20120218007INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An input circuit includes a first differential amplification circuit receiving input from a first power source and an output of a first buffer circuit to output to an input of the first buffer circuit, a second differential amplification circuit receiving input from a second external power source and an output of a second buffer circuit to output to an input of the second buffer circuit, a first resistance coupled between the output of the first differential amplification circuit and the input of the first buffer circuit, and a second resistance coupled between the output of the second differential amplification circuit and the input of the first buffer circuit. The first resistance and the second resistance are arranged at symmetric positions to a node on a signal line from the input signal terminal to the output signal terminal.08-30-2012
20120218006INTERNAL VOLTAGE GENERATING CIRCUIT - An internal voltage generating circuit includes a drive signal generating unit, a drive signal controlling unit, and a driving unit. The drive signal generating unit is configured to compare an internal voltage with first and second reference voltages and generate a first pull-up drive signal and a first pull-down drive signal. The drive signal controlling unit is configured to buffer the first pull-up drive signal and the first pull-down drive signal and generate a second pull-up drive signal and a second pull-down drive signal, wherein the second pull-up drive signal and the second pull-down drive signal are deactivated when the first pull-up drive signal and the first pull-down drive signal are activated. The driving unit is configured to drive the internal voltage in response to the second pull-up drive signal and the second pull-down drive signal.08-30-2012
20130057321Voltage Mode Driver - A driver comprises, an input block for receiving one or more data signals and one or more control signals; a data control block for processing the data signals and the control signals to determine one or more modified control signals, wherein the modified control signal is determined as a function of one or more de-emphasis signals, one or more pre-emphasis signals, and the control signals; and a driver block for receiving the modified control signals and generating one or more output data signals.03-07-2013
20130057320LOW-POWER WIDE-TUNING RANGE COMMON-MODE DRIVER FOR SERIAL INTERFACE TRANSMITTERS - A method is provided for controlling a data transmission device. The method includes providing a reference voltage to the common mode driver and putting the data transmission device in a low power state. The method also includes driving a differential signal pair output from the common mode driver during a portion of the low power state. Also provided is a device that includes a data output driver portion configured to drive an output signal at a common mode voltage and a data output driver portion configured to drive an output signal at a differential voltage level during at least a portion of time when the device is not in a low power state. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the device. Also provided is an apparatus configured to perform the method.03-07-2013
20130057319METHOD AND CIRCUIT FOR PRECISELY CONTROLLING AMPLITUDE OF CURRENT-MODE LOGIC OUTPUT DRIVER FOR HIGH-SPEED SERIAL INTERFACE - A method is provided for selecting a reference voltage value at a data transmission device that comprises a bias circuit and an output driver circuit. The method also includes providing a first electrical current at the bias circuit and a second electrical current at the output driver circuit. The second electrical current amplitude is approximately a multiple of the first electrical current amplitude, and the first electrical current is based on the reference voltage value. The method further includes driving a differential output the second electrical current. A circuit is also provided that includes a data output driver portion and a bias circuit portion. The bias circuit portion is a replica of the data output driver portion. The circuit is configured to drive a data signal. A computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus is also provided.03-07-2013
20090091359CURRENT SOURCE DEVICE - The present invention provides a current source device comprising a plurality of current output circuits each including a current output FET, first and second switch FETS respectively series-connected to source and drain sides of the current output FET to form a series circuit, source voltage supply means which applies a positive-side potential of a source voltage to the first switch FET and applies a negative-side potential of the source voltage to the second switch FET to supply the source voltage to the series circuit, and an output terminal connected between the current output FET and the second switch FET; and a gate voltage supply circuit which supplies a common gate voltage to the gates of the current output FETS, wherein each of the current output circuits further includes a third switch FET provided between the current output FET and the second switch FET.04-09-2009
20090091357LOW VOLTAGE DIFFERENTIAL SIGNALLING DRIVER - A low voltage differential signal (LVDS) driver comprising a cascade current source circuit coupled to a positive voltage supply configured to supply a current, a cascade current sink circuit maintained at a ground voltage configured to receive the current; the cascade current source circuit being coupled to the cascade current sink circuit by a current switching circuit being provided by a positive voltage supply from the cascade current source circuit and with complementary logic signals, the current switching circuit configured to provide a constant differential output voltage while in operation. Other embodiments are also disclosed.04-09-2009
20120187982BUFFER CIRCUIT HAVING SWITCH CIRCUIT CAPABLE OF OUTPUTTING TWO AND MORE DIFFERENT HIGH VOLTAGE POTENTIALS - A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.07-26-2012
20090134920Semiconductor Device - A semiconductor device in which a transistor can supply an accurate current to a load (EL pixel and signal line) without being influenced by variations is provided.05-28-2009
20090267655ANALOG BUFFER WITH VOLTAGE COMPENSATION MECHANISM - An analog buffer having voltage compensation mechanism is disclosed for use in a source driving circuit of a liquid crystal display. The analog buffer includes a reference voltage generator, a plurality of capacitors, a plurality of switches, and a plurality of transistors. Each of the capacitors is utilized to store the gate-source voltage of the corresponding turn-on transistor for performing gate-source voltage compensation operation based on the reference voltages provided by the reference voltage generator. Each of the switches functions to control gate-source voltage compensation operation and is turned on/off in response to a corresponding control signal. The analog buffer is capable of compensating the gate-source voltages of turn-on transistors for generating an output voltage having an acceptable tiny offset with respect to an input voltage.10-29-2009
20090237122Line Driver Method and Apparatus - According to one embodiment, a line driver circuit comprises a plurality of output stages each operable to produce an output signal and one or more pre-output stages operable to perform one or more common functions. The line driver circuit also comprises circuitry operable to selectively couple one or more of the output stages to the one or more pre-output stages based on a wireline communication technology implemented by the line driver circuit.09-24-2009
20090267654High-Speed Transmit Driver Switching Arrangement - The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched.10-29-2009
20130162300HIGH SPEED SERIAL INPUT/OUTPUT BUS VOLTAGE MODE DRIVER WITH TUNABLE AMPLITUDE AND RESISTANCE - A device having a voltage mode driver with tunable amplitude and resistance that supports a predetermined output resistance and output amplitude is described herein. The voltage mode driver includes multiple configurable drivers. The voltage mode driver is controlled by a control module. Resistance tuning is controlled by the number of active configurable drivers and amplitude tuning is controlled by setting the high or low drive state of each active configurable driver. The slew rate of the device is controlled by delaying the setting of the high or low drive state of an active configurable driver by a predetermined interval.06-27-2013
20110012645SIGNAL LINE DRIVING CIRCUIT AND LIGHT EMITTING DEVICE - Dispersion occurs in the characteristics of the transistors. The invention is a signal line driving circuit having a first and a second current source circuits corresponding to each of a plurality of signal lines, a shift register, and a constant current source for video signal, in which the first current source circuit is disposed in a first latch and the second current source circuit is disposed in a second latch. The first current source circuit includes capacitive means for converting the current supplied from the constant current source for video signal into a voltage, according to a sampling pulse supplied from the shift register, and supplying means for supplying the current corresponding to the converted voltage. The second current source circuit includes capacitive means for converting the current supplied from the first latch into a voltage, according to a latch pulse, and supplying means for supplying the current corresponding to the converted voltage.01-20-2011
20130063185Apparatus and Method for Pulse Width Modulation Control for Switching Power Converters - An embodiment apparatus comprises a first two-piecewise linear approximation generator and a second two-piecewise linear approximation generator coupled to an output of the first two-piece wise linear approximation generator. The second two-piecewise linear approximation generator generates a dead time inversely proportional to the output of the first two-piece wise linear approximation generator. A gate drive generator is configured to generate a primary switch drive signal and an auxiliary switch drive signal complementary to the primary switch drive signal. In addition, the dead time between the primary switch drive signal and the auxiliary switch drive signal is adjustable when the power converter operates in a light load condition.03-14-2013
20130063184HIGH TEMPERATURE OPERATION SILICON CARBIDE GATE DRIVER - Versions of the present invention have many advantages, including operation under high temperatures, or high frequencies while providing the required current for switching a SiC VJFET, providing electrical isolation and minimizing dv/dt noise. One embodiment is a silicon carbide gate driver comprising a first group of silicon on insulator devices and passive components and a second group of silicon carbide devices. The first group may have equivalent temperatures of operation and equivalent frequencies of operation as the second group.03-14-2013
20090237125POWER EFFICIENT PUSH-PULL BUFFER CIRCUIT, SYSTEM, AND METHOD FOR HIGH FREQUENCY SIGNALS - A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.09-24-2009
20090237124Input circuit and semiconductor integrated circuit including the same - An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.09-24-2009
20090237123Semiconductor device, display panel and electronic equipment - The present invention provides a semiconductor device having a buffer circuit formed on an insulating substrate using single-channel type thin film transistors, wherein the buffer circuit has an output stage which including first and second thin film transistors connected in series between first and second power sources, and the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor.09-24-2009
20090115464MULTIPLE-BRANCHING CONFIGURATION FOR OUTPUT DRIVER TO ACHIEVE FAST SETTLING TIME - A multiple branching configuration for output driver which achieves a fast settling time is provided. The multiple branching configuration comprises breaking down a typical output buffer stage into multiple branches; and utilizing multiple unit area sized transistors connected in parallel.05-07-2009
20130162301LOW VOLTAGE LINE DRIVER - A line driver includes a transconductance stage that senses a differential voltage present at differential output nodes. The transconductance stage replicates a fraction of the differential voltage and generates a differential output current corresponding to the replicated differential voltage. The differential output current flows through a current mirror stage that mirrors the differential output current to the differential output nodes. The line driver thereby decouples the transconductance stage from the differential output nodes. A lower line driver voltage supply (e.g., 1.8 V) may therefore supply the differential output nodes. A transconductance stage voltage supply separate from the line driver voltage supply may provide the supply voltage for the transconductance stage.06-27-2013
20130162302SEMICONDUCTOR DEVICE HAVING DATA OUTPUT CIRCUIT IN WHICH SLEW RATE THEREOF IS ADJUSTABLE - Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals.06-27-2013
20110043259Multifunctional Output Drivers and Multifunctional Transmitters Using the Same - A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.02-24-2011
20120112799TRANSMITTER HAVING SOURCE FOLLOWER VOLTAGE REGULATOR - A transmitter suitable for signal driving of a semiconductor device includes a driving power voltage generator and an output driver. The driving power voltage generator includes an NMOS transistor having a drain connected with a first voltage supply terminal, a gate connected to receive a second voltage lower than a voltage of the first voltage supply terminal, and a source outputting an output driving voltage and configured to perform source follower voltage regulating.05-10-2012
20100237910High-Speed, Low-Power Driver System - A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC current signal; a first resistor coupled at one end to a first voltage supply; a first current driver coupled to the input current driver and a first switch control; a second switch coupled a first current driver output, another end of the first resistor, and the output control; a dynamic booster coupled between the first voltage supply and the output control; and wherein the reduced power driver is operative for selectively adding an overshoot current to the output control so that power consumption is reduced, while synchronizing the DC current signal with the overshoot current.09-23-2010
20110128049WRITE DRIVING DEVICE - A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration signal generation unit is configured to generate a duration signal which is enabled during a predetermined duration in response to a write command. The data input clock pulse generation unit is configured to generate a data input clock pulse for transferring data to a global line in response to the alignment signal within an enable duration of the duration signal.06-02-2011
20100194447ZERO INPUT BIAS CURRENT, AUTO-ZEROED BUFFER FOR A SAMPLE AND HOLD CIRCUIT - An auto-zeroing, high impedance buffer for a sample and hold module that draws substantially no current from the input and has substantially no offset voltage at the output is discussed. During a hold mode, the offset voltage of an op-amp is accumulated on a capacitor. When the sample operation ensues the input signal is directed to the op-amp input via the capacitor where the circuitry is arranged so that the offset on the capacitor cancels the offset voltage of the op-amp. A second circuit may be fashioned and input to a sample and hold circuit for full differential operation.08-05-2010
20120032706MULTI-CHIP PACKAGE - A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.02-09-2012
20090206886Line Driver With Tuned On-Chip Termination - A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.08-20-2009
20090206887Differential current output driver with overvoltage protection - A differential current output driver and a method for overvoltage protection of a differential current output driver circuit are provided. The output driver includes a differential current output driver circuit operable by a power supply voltage and including first and second driver transistors in a differential current configuration and first and second output pads, and an overvoltage protection circuit configured to generate a protected voltage in response to a voltage on at least one of the first and second output pads and an absence of the power supply voltage, and to apply the protected voltage to at least one transistor of the differential current output driver circuit.08-20-2009
20110285425Buffer circuit having switch circuit capable of outputting two and more different high voltage pontentials - A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing.11-24-2011
20110128048VOLTAGE CONTROLLED CURRENT DRIVER POWERED BY NEGATIVE VOLTAGE RAIL - A method and current drive circuit is provided that accepts a positive voltage input signal and supplies power to a load from a negative voltage rail.06-02-2011
20110291708ELECTRONIC APPARATUS AND METHOD OF DRIVING THE SAME - An electronic apparatus includes an electronic circuit including a driving transistor, an additional capacitive element and a first switch for controlling a connection between a circuit point and a control terminal and a driving circuit which controls the first switch to an off state and changes the potential of the control terminal such that the driving transistor transitions to an on state in a first period, controls the first switch to the on state so as to set the potential of the control terminal to an initial compensation value, in a second period, and controls the first switch to the on state and changes the driving potential from the first potential to the second potential such that the driving transistor transitions to the on state, in a third period.12-01-2011
20110291707Driver with Accurately Controlled Slew Rate and Limited Current - A driver circuit, that provides slew rate control of its output voltage, including a current generator, an output transistor, and optionally, a capacitor. The current generator has an input port, an output port and reference port. The output port couples to the gate of the output transistor. The capacitor couples between the gate and drain of the output transistor. The current generator controls a current I12-01-2011
20100090728Driver and Method for Driving a Device - Embodiments of the invention relate to drivers and methods for driving devices, comprising at least one functional unit at least one of which is adapted to deduce a device parameter of an electronic device from a terminal parameter of the electronic device.04-15-2010
20110215839Input circuit and semiconductor integrated circuit including the same - An input circuit, includes a first buffer circuit, a second buffer circuit, a first differential amplification circuit that includes a first input coupled to a first external power source terminal, a second input coupled to an output of the first buffer circuit, and an output coupled to an input of the first buffer circuit, and a second differential amplification circuit that includes a first input coupled to a second external power source terminal, a second input coupled to an output of the second buffer circuit, and an output coupled to an input of the second buffer circuit.09-08-2011
20090102519A/D CONVERTER - An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is adapted to receive an analog input signal and to output an amplified signal. The converter is coupled to the sample and hold circuit and that converts the amplified signal to a digital signal. The controller is coupled to the converter and that receives the digital signal. The controller includes a plurality of voltage ranges, wherein each voltage range is associated with a current value, and the controller compares the digital signal to at least one of the voltage ranges to output at least one of the current values. The adjustable current circuit is coupled to the sample and hold amplifier and to the controller so that the adjustable current circuit provides a generally constant operating current that corresponds to the current value output from the controller.04-23-2009
20090146697CIRCUIT FOR BUFFERING HAVING A COUPLER - The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low.06-11-2009
20090146696CLASS-AB DRIVER DESIGN WITH IMPROVED FREQUENCY RESPONSE - A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal AB06-11-2009
20080238496Current mode receiver - A current mode receiver is provided. The current mode receiver includes a first current mirror duplicating an input current to output a first output current, a second current mirror duplicating the first output current to output a second output current, a third current mirror duplicating a reference current to output a third output current, and means for pulling high or low an output voltage based on the second output current and the third output current. The first through third current mirrors are respectively inputted and outputting through gain boost circuits to increase the input and output impedance thereof.10-02-2008
20080265949CMOS DRIVING CIRCUIT - A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power.10-30-2008
20090309633CHARGE PUMP FOR SWITCHED CAPACITOR CIRCUITS WITH SLEW-RATE CONTROL OF IN-RUSH CURRENT - A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.12-17-2009
20100123484AC/DC INPUT BUFFER - A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and ‘automatic’ high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.05-20-2010
20080265951DRIVER WITH PROGRAMMABLE POWER COMMENSURATE WITH DATA-RATE - One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in response to an input signal. The driver circuit also comprises at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal.10-30-2008
20100117688DIFFERENTIAL PRE-EMPHASIS DRIVER - Disclosed is a differential pre-emphasis driver. The driver includes a first current source supplying a first current, a second current source supplying a second current greater than the first current, a first select circuit for selectively connecting the first current source to a first output terminal or a second output terminal, and a second select circuit for selectively connecting the second current source to the first output terminal or the second output terminal. The first and second select circuits pre-emphasize a transmission signal by selectively combining the first output terminal, the second output terminal, the first current source and the second current source.05-13-2010
20100085084CLOCK-SHARED DIFFERENTIAL SIGNALING INTERFACE AND RELATED METHOD - The present invention provides a clock-shared differential signaling interface and a method of driving output data to a display panel. The apparatus includes a plurality of driver circuits, wherein each driver circuit in the plurality of driver circuits respectively provides output data. The apparatus also includes a timing controller providing a first clock signal to the plurality of driver circuits via a multi-drop connection, and providing a respective differential data signal to each driver circuit via a respective point-to-point connection.04-08-2010
20100079176Inverter Driver And Load Driver Including The Same, And Driving Method Thereof - A load driver includes an inverter and an inverter driver. The inverter converts an input voltage into a driving voltage of a discharge lamp using at least one first switch for switching according to a duty ratio, and the inverter driver controls the inverter. The inverter driver controls the duty ratio using a voltage of a capacitor and a control signal having a waveform that is repeated with a predetermined frequency. The capacitor is charged and discharged by a current corresponding to a difference between a feedback voltage corresponding to a current flow to the discharge lamp and a reference voltage. Such inverter driver controls to gradually increase the output voltage of the inverter in the soft start period by setting the voltage of the capacitor as a voltage corresponding to the control signal.04-01-2010
20100079175PHASE DOUBLER - A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current. Drive circuitry generates drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal.04-01-2010
20080211548Semiconductor integrated circuit controlling output impedance and slew rate - The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.09-04-2008
20100148830GATE DRIVER CIRCUIT, SWITCH ASSEMBLY AND SWITCH SYSTEM - It is presented a gate driver circuit for driving an electric switch, the switch being arranged to control a main current using a gate signal. The gate driver circuit comprises: a non-linear capacitor means having a lower capacitance when an applied voltage is under a threshold voltage and a higher capacitance when an applied voltage is over the threshold voltage, wherein the non-linear capacitor is arranged to be connected between a high voltage connection point of the switch and a connection point for the gate signal; a current change rate sensor, the current change rate sensor being configured to detect changes in a main current of the electric switch and to control a gate signal of the electric switch depending on the current change; a gate buffer; and at least one current source, arranged to drive the gate buffer. The current change rate sensor is connected to control the current source to thereby control the gate signal of the electric switch.06-17-2010
20090289668Output driver circuit for an integrated circuit - An integrated circuit 11-26-2009
20100127736LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER WITH PROGRAMMABLE ON-CHIP RESISTOR TERMINATION - A low voltage differential signaling driver is disclosed and may include a current steering output circuit having a first driver output and a second driver output. The low voltage differential signaling driver may also include a programmable on-chip resistor.05-27-2010
20090261867SEMICONDUCTOR DEVICE HAVING VOLTAGE OUTPUT CIRCUIT - Input and output nodes, an output circuit and a drive circuit are provided. The output circuit includes first and second n-channel MOS transistors connected to each other in series. A drain of the first n-channel MOS transistor is connected to a first line. A source of the first n-channel MOS transistor, a drain of the second n-channel MOS transistor, and a drain of a first p-channel MOS transistor are commonly connected to the output node. A source of the second n-channel MOS transistor is connected to a second line. A source of the first p-channel MOS transistor is connected to the first line. The drive circuit generates first to third control signals in response to an input signal provided to the input node. The control signals are respectively outputted to gates of the first and second n-channel MOS transistors and to a gate of the first p-channel MOS transistor.10-22-2009
20090261866VOLTAGE DIVIDER CIRCUIT - Provided is a voltage divider circuit for dividing an input voltage in accordance with a predetermined ratio with high accuracy, in which a source current does not flow from a voltage source and a sink current does not flow into the voltage source. The voltage divider circuit according to the present invention includes: a first resistor; a constant current circuit for outputting a current flowing through the first resistor correspondingly to an input voltage as a constant current; a first current mirror circuit, in which the constant current becomes an input current, for outputting a first output current; a second current mirror circuit, in which the first output current becomes an input current, for outputting a second output current; and a second resistor connected to an output terminal to which the second output current of the second current mirror circuit is output, in which a divided voltage, which is a potential difference between both ends of the second resistor, is adjusted by a current mirror ratio between the first current mirror circuit and the second current mirror circuit, and a resistance ratio between the second resistor and the first resistor.10-22-2009
20110199129Line Driver with Reduced Dependency on Process, Voltage, and Temperature - According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.08-18-2011
20120293215DRIVING CIRCUIT HAVING CURRENT BALANCING FUNCTIONALITY - A driving circuit having current balancing functionality includes a control unit, a bias resistor, a current switch unit and plural current driving modules. The control unit is utilized for generating a control signal having at least one bit according to a control current. The bias resistor is put in use for providing a bias voltage according to a bias current. The current switch unit employs the control signal and plural bias setting currents to generate the bias current, for keeping the bias voltage within a preset voltage range. The current driving modules are used to provide plural driving currents according to the bias voltage and the control signal. Each current driving module includes a current-limit control unit which is utilized for controlling a corresponding driving current according to the control signal.11-22-2012
20110267112OUTPUT DRIVER AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal.11-03-2011
20120119795SYSTEM INCLUDING DRIVER CIRCUIT FOR ELECTRICAL SIGNALING AND OPTICAL SIGNALING - A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.05-17-2012
20120119794POWER REDUCTION IN SWITCHED-CURRENT LINE-DRIVERS - A differential switched-current line-driver implements a method to reduce power consumption by eliminating output current that does not contribute to the required differential output signal. This output current is used for example during a training phase, and the current elimination can take place after the training phase is complete.05-17-2012
20120119793INTERFERENCE-TOLERANT COMMUNICATION CIRCUIT - An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.05-17-2012
20090167368PRE-DRIVER CIRCUIT HAVING A POST-BOOST CIRCUIT - A pre-driver is provided that includes a pre-boost circuit and a post-boost circuit. The post-boost circuit may include a pulse generator circuit to provide a feedback to be used to control an output of the pre-driver.07-02-2009
20090167370Output Buffer - An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer. The current detector includes a duplicated structure which replicates a portion of the buffer circuit without altering the performances of the buffer itself.07-02-2009
20090167369LVDS OUTPUT DRIVER - An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors.07-02-2009
20120119792ADJUSTABLE FINITE IMPULSE RESPONSE TRANSMITTER - Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter includes driver circuitry configured to generate an output signal at an output node and an allocation control module coupled to the driver circuitry. The driver circuitry includes a plurality of driver legs configured to generate the output signal based on a plurality of data bits. The allocation control module is configured to allocate a respective subset of the plurality of driver legs to a respective data bit of a plurality of data bits, wherein the each subset generates a component of the output signal that is influenced by its respective data bit.05-17-2012
20080278201Buffering circuit of semiconductor device - A buffering circuit of a semiconductor device includes: a first buffer configured to receive a first power voltage and a second power voltage as driving power voltages to buffer an input signal; a power supplier configured to adjust supply amounts of the first and second power voltages in response to a plurality of driving power signals to supply first and second driving power voltages; and a second buffer configured to receive the first and second driving power voltages, and to buffer an output signal of the first buffer.11-13-2008
20080290909Source driver in liquid crystal display device, output buffer included in the source driver, and method of operating the output buffer - Provided is an output buffer, which may be included in a source driver of a liquid crystal display (LCD) device. The output buffer may include a differential amplification unit and an output unit. The differential amplification unit may generate control currents by amplifying the difference between the voltages of an analog image signal and a signal output from the output buffer. The output unit outputs the amplified analog image signal in response to the control currents. The amount of bias current used to drive the differential amplification unit increases during a charge recycling period, and the amount of quiescent current flowing through the output unit decreases during the charge recycling period. The amount of the bias current used to drive the differential amplification unit decreases during a driving period, and the amount of the quiescent current flowing through the output unit increases during the driving period.11-27-2008
20080290910METHOD AND APPARATUS FOR A VOLTAGE TRIGGERED CURRENT SINK CIRCUIT - A current sink circuit is disclosed. An apparatus according to aspects of the present invention includes a sensing element, a pass element coupled to the sensing element and a setting element coupled to the pass element. The setting element provides both a voltage threshold level and a current regulation reference. The pass element is to pass current conducted through the current sink circuit in response to the setting element. The current conducted through the current sink circuit is substantially zero when a voltage applied across the current sink circuit is below the voltage threshold level. A signal generated by the sensing element is regulated in response to the current regulation reference by regulating a current conducted through the pass element when a voltage applied across the current sink circuit is above the voltage threshold level.11-27-2008
20120293214ELECTRONIC SWITCHING DEVICE - An electronic switching device comprises a first bipolar junction transistor (BJT) (11-22-2012
20100201405DYNAMIC PHASE TIMING CONTROL FOR MULTIPLE REGULATORS OR PHASES - A drive control circuit generates switching drive signals for a single phase of a multiphase voltage regulator. A driver circuitry generates the switching drive signals for the voltage regulator responsive to a clock signal. A clock circuitry generates the clock signal responsive to a monitored external clock signal. A phase number detector determines a number of active phases in the multiphase voltage regulator in real time responsive to an indicator on a phase number input monitored by the phase detector.08-12-2010
20100201404Active Free-running Frequency Circuit for Phase-locked Loop Applications - This disclosure relates to a Phase-Locked Loop (PLL) device and a method for providing a stable free-running voltage signal to a voltage controlled oscillator.08-12-2010
20080211547Inverter citcuit - An inverter circuit includes an IGBT (09-04-2008
20090015299OUTPUT CIRCUIT - A reference voltage is applied from a reference voltage generating circuit to the non-inverting input terminal of an amplifier for supplying a drive voltage to the gate terminal of an NMOS transistor, and the output voltage appearing at the source terminal of the NMOS transistor is divided by a resistor pair and applied to the inverting input terminal of the amplifier. The voltage obtained by adding a voltage equal to or higher than the voltage for sufficiently driving the NMOS transistor to the output voltage appearing at the source terminal of the NMOS transistor is generated by a charge pump circuit and supplied to the amplifier as a power supply voltage. With this configuration, the drive voltage for the NMOS transistor is suppressed to the required minimum voltage while the drive voltage is obtained securely. The power consumption in the amplifier can thus be suppressed.01-15-2009
20080290908Variable Power Write Driver Circuit - A storage system (e.g., a magnetic disk system or a magnetic tape system) employing a write head, a write controller and a write driver circuit. In operation, the write head records data on a magnetic media (e.g., a magnetic tape or a magnetic disk) based on a flow of a write current through the write head, and the write driver circuit includes a variable power supply network and a variable power return network driving the write current through the write head based on a selection by the write controller of an operating power mode among a plurality of selectable power modes of the variable power supply network and the variable power return network. Each power mode of the variable power supply network and the variable power return network drives the write current with a different magnitude from the variable power supply network through the write head to the variable power return network.11-27-2008
20110006812DRIVER CIRCUIT AND ADJUSTMENT METHOD THEREFOR - A driver circuit includes an output section; a voltage-dividing section configured to divide a first voltage at a coupling point between the output section and a termination resistor; a comparison section configured to compare a voltage difference with one of the first voltage and a second voltage, the voltage difference being a difference between the second voltage at a coupling point between the termination resistor and a transmission path and a third voltage output from the voltage-dividing section; and an adjustment section configured to adjust a voltage division ratio of the voltage-dividing section on the basis of the comparison result obtained in the comparison section.01-13-2011
20110006813Input circuit and semiconductor integrated circuit including the same - An input circuit, includes a first buffer circuit whose output is couple to an output signal terminal of the input circuit, and whose input is coupled to an input signal terminal of the input circuit, a second buffer circuit, a third buffer circuit, a first differential amplification circuit whose first input is coupled to a first external power source terminal, whose second input is coupled to an output of the second buffer circuit, and whose output is coupled to an input of the second buffer circuit, a second differential amplification circuit whose first input is coupled to a second external power source terminal, whose second input is coupled to an output of the third buffer circuit, and whose output is coupled to an input of the third buffer circuit, a first resistance whose one end is coupled to the output of the first differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit, a second resistance whose one end is coupled to the output of the second differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit.01-13-2011
20130120028METHOD, SYSTEM, AND CIRCUIT WITH A DRIVER OUTPUT INTERFACE HAVING A COMMON MODE CONNECTION COUPLED TO A TRANSISTOR BULK CONNECTION - A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.05-16-2013
20090021286PSEUDO DIFFERENTIAL OUTPUT BUFFER, MEMORY CHIP AND MEMORY SYSTEM - An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.01-22-2009
20090160494OUTPUT DRIVING CIRCUITS - An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.06-25-2009
20090160497Signal line driving device comprising a plurality of outputs - A driving device that outputs signals of different polarities from plural output terminals includes: a first power source wire that connects power terminals of some of plural first output circuits each outputting a signal of one polarity and power terminals of some of plural second output circuits each outputting a signal of the other polarity; and a second power source wire that connects power terminals of the rest of the plural first output circuits and power terminals of the rest of the plural second output circuits, the second power source wire being different from the first power source wire.06-25-2009
20120139588Current Driver, Electronic Device and Current Driving Method - The present invention provides a current driver for driving a current driven device. The current driver includes a driving circuit, configured to generate a driving current to drive the current driven device, and conduct or cut off a driving current path through which the driving current flows according to a voltage level of a driving control node, and an accelerating circuit, coupled to the driving control node of the driving circuit, configured to provide an accelerating current flowing through the driving control node to accelerate a voltage level transition at the driving control node during an activation period of the driving circuit, and automatically cut off the accelerating current when a voltage level of the driving control node reaches a specific level.06-07-2012
20090140777DIFFERENTIAL TRANSISTOR PAIR CURRENT SWITCH SUPPLIED BY A LOW VOLTAGE VCC - The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T06-04-2009
20090140778DIFFERENTIAL DRIVE CIRCUIT AND COMMUNICATION DEVICE - A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.06-04-2009
20090015298Output buffer circuit - In the case of a conventional output buffer circuit, it is difficult to adjust rising and falling times of a signal outputted from each of differential output terminals (OUTP/OUTN). Provided is an output buffer circuit including: a delay circuit including a first, second and third delay paths coupled to a first, second and third nodes, respectively, each of the first, second, and third delay paths performing time shifting transmission for the input signal, thereby extracting a first, second and third signals from the first, second and third nodes, respectively; a first output buffer coupled from the first node to drive an output terminal in response to the first signal; a second output buffer coupled from the second node to drive the output terminal in response to the second signal; and a third output buffer coupled from the third node to drive the output terminal in response to the third signal.01-15-2009
20090212828Load Driving Circuit - To provide a load drive circuit that has a satisfactory phase characteristic and can be realized as a low-price LSI chip. A series circuit of nonlinear resistive elements (P08-27-2009
20090096491DRIVER CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - A driver circuit includes a first capacitor provided between a first node and a reference node, a second capacitor provided between a second node and the reference node, a first switch element provided between the first node and an input node, a second switch element provided between the first node and an analog reference power supply, a third switch element provided between the second node and an output node, a fourth switch element provided between the second node and the analog reference power supply, and a fifth switch element provided between the output node and the reference node. A first capacitor area and a second capacitor area are disposed along a first direction. The first switch element and the second switch element are disposed in a third direction with respect to the first capacitor area and the second capacitor area. The third switch element and the fourth switch element are disposed in the first direction with respect to the first capacitor area and the second capacitor area. A reference node line is provided in a second direction with respect to the first switch element, the second switch element, the third switch element, and the fourth switch element.04-16-2009
20090096492Output Driver Equipped with a Sensing Resistor for Measuring the Current in the Output Driver - An electronic circuit has an output driver for providing a driving signal. The output driver has a transistor with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal, a power supply terminal, an output terminal for providing the driving signal that is coupled to the second main terminal, and a sensing resistor coupled between the power supply terminal and the first main terminal. The output driver further has means for temporarily disabling the coupling between the control terminal and the control signal during a peak voltage across the sensing resistor. The means may have a circuit that has a unidirectional current behavior, such as a diode, in series with the control terminal of the transistor.04-16-2009
20090085612MULTI-PURPOSE CURRENT DRIVER SYSTEM AND METHOD - A current driver system and method for generating one or more independent current signals for controlling or driving an external device. In one embodiment the system includes a programmable controller having both serial and parallel interfaces, and controls six independent current driver channels. Each current driver channel may form a dual stage channel that generates two different level current signals. Each current driver channel may include an overcurrent monitoring circuit as well as a loop back subsystem, where the loop back subsystem generates a signal that the programmable controller, and thus an external device in communication with the controller, can use to verify that proper communication is occurring between the controller and the current driver channel. The controller also synchronizes the turn on and turn off points for each current signal to a master system clock.04-02-2009
20090085613LOW CURRENT WIDE VREF RANGE INPUT BUFFER - A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.04-02-2009
20090201053LAYOUT STRUCTURE OF SOURCE DRIVER AND METHOD THEREOF - A layout structure of a source driver having a plurality of driving channels, and a method thereof are provided herein. The layout structure of the source driver includes a plurality of pads and a plurality of routings. The pads are used for making electric contact between the source driver and an external circuit. The routings are respectively coupled between the driving channels and the pads for transmitting the signal. Besides, the routings respectively includes a plurality of resistance units, and each of the resistance units is used for adjusting the resistance of the respective routing so as to minimize a variation of the driving ability between the pads.08-13-2009
20090002036LIQUID EJECTING APPARATUS AND LIQUID EJECTING METHOD - A liquid ejection apparatus includes an element that is charged and discharged so as to perform an operation to eject a liquid, an analog signal generating unit that generates an analog signal having a voltage change pattern for determining the operation of the element, a charging transistor that amplifies a current of the analog signal while the element is charged, and pushes the amplified current toward the element, the charging transistor having a current source terminal, to which a current source is connected, and a push terminal for pushing the current, and a current source connector that selects at least one current source from among a plurality of current sources according to a voltage of the analog signal, and connects the selected current source to the current source terminal.01-01-2009
20090212830BUFFER DEVICE FOR SWITCHED CAPACITANCE CIRCUIT - An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.08-27-2009
20090212829LINE DRIVER ARCHITECTURE FOR 10/100/1000 BASE-T ETHERNET - A multimode line driver circuit is provided having improved performance. The multimode line driver comprises at least first and second driver circuits that, when “active,” respectively transmit data using first and second modes. The multimode line driver further comprises a circuit arrangement including a voltage regulator and an associated set of switches. In operation, at least some of the switches are coupled to the second driver circuit and are turned on when the first driver circuit is active. The voltage regulator supplies a direct current to at least some of the turned-on switches in order to decrease a common mode voltage at the second driver circuit while the first driver circuit transmits data using the first mode. As such, components of the second driver circuit can be powered off while the first driver circuit is active, thus reducing power consumption in the first mode.08-27-2009
20100039145HYBRID DRIVING APPARATUS AND METHOD THEREOF - A hybrid driving apparatus and a method thereof are provided. The hybrid driving apparatus includes a first driving unit, a second driving unit, and a resistor. The first driving unit has a first output end. The second driving unit has a second output end coupled to a first bonding pad. The resistor is coupled between the first output end and the first bonding pad to serve as a matching impedance. When the driving apparatus operates in a first transmission mode, the first driving unit and the second driving unit jointly drive the first bonding pad. When the driving apparatus operates in a second transmission mode, the first driving unit and the second driving unit drive the first bonding pad and a second bonding pad respectively.02-18-2010
20090243665Cascode Driver with Gate Oxide Protection - An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages.10-01-2009
20090243666A DRIVING CIRCUIT TO DRIVE AN OUTPUT STAGE - A driving circuit to drive an output stage comprising a high side NMOS and a low side NMOS is provided. The driving circuit comprises: a diode comprising an anode and a cathode, wherein the anode is electrically connected to a first voltage source and the sources of a first and a second PMOS; a third and a fourth PMOS both comprising a drain, a source and a gate, wherein the sources are respectively connected to the gates of the second and first PMOS, the drains are respectively connected to the drains of the first and second PMOS. A first and a second NMOS both comprise a drain, a source and a gate, wherein the drains are respectively connected to the drain of the fourth and third PMOS, the sources are coupled to a second voltage source, the gates are respectively connected to a first input and a second input.10-01-2009
20090251175Input buffer capable of reducing delay skew - An input buffer includes a delay compensation unit for combining (a) a first signal obtained by buffering an input signal using another signal, which is out of phase with the input signal, with (b) a second signal obtained by buffering the input signal using a reference voltage signal, to output a third signal.10-08-2009
20090251174OUTPUT BUFFER OF A SOURCE DRIVER APPLIED IN A DISPLAY - An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V10-08-2009
20090315593Partial Switch Gate Driver - A power switch driver includes a top driver switch, a bottom driver switch, a driver node between them, and driver logic. The power switch driver can turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a lower second voltage level. The driver logic may include a pulse width generator programmer and a pulse width generator. The pulse width generator is controlled by the pulse width generator programmer and an input signal. Some power switch drivers include a feedback loop, coupled to the driver node and to the driver logic. The feedback loop may include a track-and-hold circuit, coupled to the driver node, to the pulse width generator through an error amplifier and to the input terminal.12-24-2009
20100148829LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller.06-17-2010
20100156473CLCOK DRIVER CIRCUIT - Clock driver circuit having upper and lower transistors06-24-2010
20100176849CLOSED LOOP SURGE PROTECTION TECHNIQUE FOR DIFFERENTIAL AMPLIFIERS - A differential amplifier with surge protection is described. The differential amplifier includes a first output driver device, a second output driver device, a first replica device, a second replica device, a current comparator, and a clamp circuit. The first replica device is configured to be a replica of the first output driver device. The second replica device is configured to be a replica of the second output driver device. The current comparator is configured to generate a threshold current, and to compare the threshold current to a first current through the first replica device and a second current through the second replica device. The clamp circuit is configured to limit a third current through the first output driver device and a fourth current through the second output driver device if the current comparator determines that the threshold current is greater than the first current or the second current.07-15-2010
20100176848INPUT/OUTPUT BUFFER CIRCUIT - A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.07-15-2010
20100156474GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate drive circuit includes m stages cascade connected to one another, each stage respectively outputting one of a plurality of gate signals. An m-th stage includes a pull-up part, a pull-down part, a boost-up part, a first maintenance part and a second maintenance part. The pull-up part outputs a high voltage of a first clock signal at the high voltage of an m-th gate signal. The pull-down part applies a low voltage to an output node of the pull-up part. The boost-up part boosts a voltage charged by an offset second clock signal. The first maintenance part maintains the first node at a low voltage in response to the boosted voltage of the second node. In addition, the second maintenance part maintains the m-th gate signal at the low voltage in response to the high voltage of the first clock signal.06-24-2010
20090079471LOW POWER BUFFER CIRCUIT - A dual-output buffer circuit for providing a first reference voltage and a second reference voltage has a first buffer circuit, a second buffer circuit, a first reference voltage coupled to the first buffer circuit, a second reference voltage coupled to the second buffer circuit, and a diode circuit coupled to a first output terminal of the first buffer circuit and a second output terminal of the second buffer circuit.03-26-2009
20100164557ACTIVE ECHO ON-DIE REPEATER CIRCUIT - A repeater circuit. The repeater circuit includes two output circuits, two echo circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, which is configured to drive an output signal on an output node. A corresponding echo circuit is configured to be activated and to drive an input node responsive to activation of the corresponding output circuit. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the corresponding echo circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuit.07-01-2010
20130214820APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.08-22-2013
20100013522Serial Bus Interface Circuit - An interface circuit for a serial bus is disclosed and includes a receiving terminal, an output terminal, a first switching circuit, a voltage source, and a second switching circuit. The receiving and output terminals are used for receiving an input signal and outputting a first voltage signal respectively. The first switching circuit is used for determining a coupling relationship between the output terminal and the grounded terminal according to difference between the input signal and a grounding voltage provided by the grounded terminal. The voltage source is used for producing a voltage drop based on a driving voltage driving the serial bus interface circuit to provide a first voltage. The second switching circuit is used for determining a coupling relationship between the first switching circuit and the voltage source according to difference between the input signal and the first voltage.01-21-2010
20100001768MEMS Capacitor Circuit and Method - A communications circuit processes a signal in at least one predetermined communications standard such as GSM or UMTS. A switched capacitor impedance matching unit is provided, controlled by driver control unit. The driver control unit is arranged to control the driver to start switching of the capacitors of the switched capacitor array during transition periods in the signals.01-07-2010
20100277206GATE DRIVE CIRCUIT AND METHOD OF DRIVING THE SAME - In a gate drive circuit including stages which are cascaded and which output gate signals each of the stages includes a first node, an output part, a first holding part and a second holding part. A voltage of the first node is converted to a high voltage in response to one of a vertical start signal and a carry signal of one of previous stages. The output part outputs a first clock signal as a gate signal through an output terminal in response to the high voltage of the first node. The first holding part applies a first low voltage to the output terminal, in response to a gate signal output from at least one of following stages. The second holding part applies a second low voltage, which is less than the first low voltage, to the first node in response to a gate signal output from at least one stage among following stages.11-04-2010
20100253394BUFFER WITH AN OUTPUT SWING CREATED USING AN OVER-SUPPLY VOLTAGE - A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply.10-07-2010
20100237909PHYSICAL QUANTITY DETECTION CIRCUIT AND PHYSICAL QUANTITY SENSOR DEVICE - A physical quantity detection circuit (09-23-2010
20100253393BUFFER AND DISPLAY DEVICE - A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 10-07-2010
20100253392I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES - The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.10-07-2010
20110057687INPUT BUFFER CIRCUIT - There are provided a differential input circuit, a PMOS transistor 03-10-2011
20100164560SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - A semiconductor integrated circuit apparatus includes a first circuit block including a critical path and second and third circuit blocks not including the critical path. A threshold voltage of a semiconductor element of a circuit in the first circuit block is equal to or lower than a threshold voltage of a semiconductor element of a circuit in the second circuit block and a supply voltage supplied to the first circuit block is equal to or higher than a supply voltage supplied to the second circuit block, wherein the critical path in the first circuit block is eliminated. A threshold voltage of a semiconductor element of a circuit in the third circuit block is equal to or lower than the threshold voltage of the semiconductor element of the circuit in the second circuit block, and a supply voltage supplied to the third circuit block is equal to or lower than the supply voltage supplied to the second circuit block, wherein power consumption of the third circuit block is reduced.07-01-2010
20120194225DIFFERENTIAL OUTPUT BUFFER - According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.08-02-2012
20100259303REFERENCE BUFFER CIRCUIT - A reference buffer circuit is provided, comprising a reference buffering stage and a driving stage. The buffering stage provides a first driving voltage based on a first input voltage. The driving stage is driven by the first driving voltage to output a first output voltage. In the buffering stage, a first operational amplifier has a first input end for receiving the first input voltage, a second input end, and an output end for outputting a first tracking voltage. A first level shifter is coupled to the output end of the first operational amplifier, shifting a level of the first tracking voltage to generate the first driving voltage. A first buffering transistor has a drain coupled to a first supply voltage, a source connected to the second input end of the first operational amplifier, and a gate coupled to the first charge pump for receiving the first driving voltage.10-14-2010
20110128047HALF-POWER BUFFER AMPLIFIER - A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.06-02-2011
20100013523CURRENT DRIVER CIRCUIT - In a case where potential of the first input terminal is lower than that of the second input terminal by an amount of the offset voltage, in a normal operation mode, the control circuit controls the polarity switching circuit so as to input the first contact voltage of the first contact to the first input terminal and input the control voltage to the second input terminal. On the other hand, in a case where the potential of the first input terminal is higher than that of the second input terminal by an amount of the offset voltage, in the normal operation mode, the control circuit controls the polarity switching circuit so as to input the first contact voltage at the first contact to the second input terminal, input the control voltage to the first input terminal, and invert the polarity of the amplified signal.01-21-2010
20090201052LOW VOLTAGE, HIGH-SPEED OUTPUT-STAGE FOR LASER OR MODULATOR DRIVING - The present invention provides a driving circuit (08-13-2009
20090160496Output driver circuit - In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors.06-25-2009
20090146695HYBRID IC FOR ULTRASOUND BEAMFORMER PROBE - A hybrid integrated circuit package for a microbeamformer in an ultrasound probe includes a substrate, a driver circuit for generating transmit pulses to be transmitted to the transducer elements of the probe for producing a transmit beam, and a beamformer circuit including time delay circuits and a summation circuit, the time delay circuits being operatively arranged for receiving a plurality of reflected pulses from the transducer elements and delaying the reflected pulses and the summation circuit operatively arranged summing groups of the delayed reflected pulses for producing beamformed signals. The driver circuit is part of a high voltage integrated circuit device including said driver circuit. At least a portion of the beamformer circuit is part of a low voltage integrated circuit device, wherein the high voltage integrated circuit and the low voltage integrated circuit are mounted on the substrate.06-11-2009
20090115463Buffer Circuit - A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation.05-07-2009
20080303559ELECTRONIC DEVICE AND RELATED METHOD FOR PERFORMING COMPENSATION OPERATION ON ELECTRONIC ELEMENT - The present invention discloses an electronic device and related method for performing a compensation operation on an electronic element, wherein the electronic device includes: a control module, for outputting a control signal according to an input signal; a driver module, coupled to the control module and the electronic element, for providing a driving current to the electronic element according to the control signal; a sensor module, for outputting at least a sensor signal according to a variation of an operation environment; a compensation control module, coupled to the sensor module, for outputting at least a compensation control signal according to the at least a sensor signal and the input signal; and a compensation driver module, coupled to the electronic element and the compensation control module, for providing at least a compensation driving current to the electronic element according to the at least a compensation control signal.12-11-2008
20080303558DATA OUTPUT DRIVER CIRCUIT - A data output driver circuit can be configured to comprise a predriver control unit generate a plurality of pullup output load control signals and a plurality of pulldown output load control signals depending upon a sensed external voltage, and a predriver is configured to output a signal by adjusting a slew rate of an inputted data in response to the plurality of pullup output load control signals and the plurality of pulldown output load control signals.12-11-2008
20110032007Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof - A method for increasing responding speed and lifespan of a buffer includes detecting an edge of an input signal of the buffer, triggering a pulse signal with a predetermined period according to the detected edge, and driving the buffer for generating an output signal according to the pulse signal and the input signal.02-10-2011
20110032006BI-DIRECTIONAL CHANNEL AMPLIFIER - An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.02-10-2011
20080265950LOW-POWER IMPEDANCE-MATCHED DRIVER - One embodiment of the invention includes a driver circuit. The driver circuit comprises a high-side switch that is activated in response to a positive driver input signal to provide a positive output signal at a driver output. The driver circuit also comprises a low-side switch that is activated in response to a negative driver input signal to provide a negative output signal at the driver output. The positive and negative driver input and output signals can be relative to respective cross-over magnitudes. The driver circuit further comprises at least one impedance-matching device configured to activate the low-side switch in response to a positive signal reflection at the driver output and to activate the high-side switch in response to a negative signal reflection at the driver output.10-30-2008
20080231329DIFFERENTIAL SIGNAL OUTPUT CIRCUIT FOR TIMING CONTROLLER OF DISPLAY DEVICE - A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.09-25-2008
20100295581BUFFER WITH ACTIVE OUTPUT IMPEDANCE MATCHING - Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.11-25-2010
20100134153Low Latency Multi-Level Communication Interface - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.06-03-2010
20110109350Stable Current Source for System Integration to Display Substrate - A technique to implement a stable and high impedance current sink or source onto a display substrate using a single device. The high output current source or sink circuit includes an input that receives a fixed reference current and provides the reference current to a node in the current source or sink circuit during a calibration operation of the current source or sink circuit. The circuit further includes a first transistor and a second transistor series-connected to the node such that the reference current adjusts the voltage at the node to allow the reference current to pass through the series-connected transistors during the calibration operation. The circuit includes one or more storage devices connected to the node, and an output transistor connected to the node to source or sink an output current from current stored in the one or more storage devices to a drive an active matrix display with a bias current corresponding to the output current.05-12-2011
20090066371BUFFER CIRCUIT WHICH OCCUPIES LESS AREA IN A SEMICONDUCTOR DEVICE - The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.03-12-2009
20090066372HIGH SPEED CMOS OUTPUT BUFFER FOR NONVOLATILE MEMORY DEVICES - An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.03-12-2009
20110025380OUTPUT DRIVER OPERABLE OVER WIDE RANGE OF VOLTAGES - An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.02-03-2011
20100171531OUTPUT BUFFER WITH HIGH DRIVING ABILITY - An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level.07-08-2010
20100164558FOLLOWER OUTPUT BUFFER - Embodiments include but are not limited to apparatuses and systems including an output buffer including an input terminal for receiving an input signal, an output terminal for outputting an output signal, and a follower circuit coupling the input terminal and the output terminal, the follower circuit including at least one set of an NMOS transistor and a PMOS transistor, a drain terminal of the NMOS transistor coupled to a local supply voltage, and a drain terminal of the PMOS transistor coupled to a local ground voltage. Other embodiments may be described and claimed.07-01-2010
20100164556CONVERTING DYNAMIC REPEATERS TO CONVENTIONAL REPEATERS - A method for converting a repeater circuit from a dynamic repeater circuit to a static repeater circuit. The method includes disconnecting a feedback path coupled to a first stage of the dynamic repeater circuit and electrically shorting gate terminals of first and second transistors of a second stage to each other, wherein the transistors of the second stage are configured to drive an output signal on an output node. Disconnecting the feedback path and electrically shorting the gate terminals is performed by reconfiguring a plurality of selection devices in the repeater circuit from a first configuration to a second configuration. The repeater circuit includes at least one keeper configured to provide an output signal on the output node.07-01-2010
20110241735DRIVING CIRCUIT AND DRIVING METHOD FOR CURRENT-DRIVEN DEVICE - A driving circuit and a driving method for drive a current-driven device having a first terminal and a second terminal are provided. The first terminal is coupled to a first power source potential. The driving circuit includes a switching module, a first capacitor and a second capacitor. The switch module is coupled to a data line, the second terminal and a second voltage source and further is for determining whether to allow a current to flow through the current-driven device. A first end and a second end of the first capacitor are respectively coupled to different nodes in the switch module. The first end of the first capacitor receives a potential on the data line in a particular time period. A first end and a second end of the second capacitor are respectively coupled to the second end of the first capacitor and a second power source potential.10-06-2011
20110241736INPUT BUFFER - An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal.10-06-2011
20110084734CIRCUIT HAVING SAMPLE AND HOLD FEEDBACK CONTROL AND METHOD - A drive circuit and a method for maintaining an operating state of the drive circuit. The drive circuit includes a capacitor connected to an inverting input terminal of an operational amplifier and to a terminal of a current sensitive load through a switch. The output of the operational amplifier is connected to a switching regulator which has an output terminal connected to another terminal of the current sensitive load. An energy storage element is connected to the inverting input terminal of the operational amplifier. Energy is stored in the energy storage element during a first portion of a PWM pulse which is used during a second portion of the PWM pulse to generate the error signal. A drive signal is generated from the error signal where the drive signal is used to generate a voltage that biases the current source during the second portion of the PWM pulse.04-14-2011
20110084736ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS - An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.04-14-2011
20110084735SCART INTERFACE CONTROL CIRCUIT AND VIDEO DEVICE USING THE SAME - A SCART interface control circuit outputs a mode switch signal to a switch signal pin of the SCART interface according to standby, widescreen and normal modes of video signals. The SCART interface control circuit comprises a first voltage circuit, a second voltage circuit, a voltage combination circuit and an amplifier circuit. The first and second voltage circuits output first and second voltage signals according to the video signal modes, respectively. The voltage combination circuit combines the first and second voltage signals into a combination voltage signal. The amplifier circuit amplifies the combination voltage signal so as to output the mode switch signal for indicating the video signal modes.04-14-2011
20110084733DRIVING CIRCUIT WITH SLEW-RATE ENHANCEMENT CIRCUIT - A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage.04-14-2011
20110084737FREQUENCY RESPONSIVE BUS CODING - A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.04-14-2011
20100039143OUTPUT CIRCUIT AND DRIVING METHOD THEREOF - An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals.02-18-2010
20110248749SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having an output driver and a driver replica. The output driver is based on a scalable low-voltage signaling technology and capable of operating on low power and making automatic adjustments of output characteristics in accordance with the magnitude of a reference current. The driver replica, which is a duplicate of the output driver, adjusts the magnitude of the reference current in accordance with the difference between its own output and a reference voltage and outputs the adjusted current to the output driver.10-13-2011
20100066418DIFFERENTIAL CURRENT DRIVING TYPE DATA TRANSMISSION SYSTEM - A differential current driving type data transmission system includes a line drive controller for outputting differential transmission signals and common mode line control signals, in response to a transmission signal; current sources for generating an excitation current and a base current and for driving positive/negative transmission lines with the base current; a first switch for selectively switching the excitation current to the positive/negative transmission lines, in response to the differential transmission signals; and a second switch for equalizing the positive/negative transmission lines within a common mode interval, in response to the common mode line control signals, wherein, in the common mode, the positive/negative transmission lines are driven at a level above or below an intermediate current level by a predetermined common mode current difference.03-18-2010
20110102025DATA OUTPUT CIRCUIT - The data output circuit includes a first decoder, a second decoder, a first selective output circuit, a second selective output circuit, and an output driver. The first decoder is configured to generate a pull-up selection signal by decoding a pull-up code. The second decoder is configured to generate a pull-down selection signal by decoding a pull-down code. The first selective output circuit is configured to select and output a voltage level of a pull-up level signal in response to the pull-up selection signal. The second selective output circuit is configured to select and output a voltage level of a pull-down level signal in response to the pull-down selection signal. The output driver is configured to drive output data in response to receiving a pre-pull-up signal and a pre-pull-down signal.05-05-2011
20090153199Operational comparator, differential output circuit, and semiconductor integrated circuit - An operational comparator 06-18-2009
20110068831LOW POWER LINE DRIVER AND METHOD THEREOF - A line driver for a communications system requiring multiple power sources for different modes of operation comprises a current source and a voltage source coupled in parallel with the current source. The current source has a first terminal and a second terminal. The line driver further comprises a first source resistor coupled to the first terminal of the current source and a second source resistor coupled to the second terminal of the current source. The current source provides a driving current and the voltage source provides a driving voltage at the same time during operations of the communications system.03-24-2011
20090027090CURRENT MODE MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a first circuit to receive input signals and to drive signals at first circuit output nodes, and a second circuit to receive at least a portion of current passing through the first circuit output nodes and to generate output signals at second circuit output nodes, the second circuit including a pair of transistors coupled to the second circuit output nodes with gates of the pair of transistors to receive different signals to affect a value of a voltage difference between the output signals, the different signals being different from the output signals. Other embodiments including additional apparatus, systems, and methods are disclosed.01-29-2009
20090027089Driver Circuit; Electronic Circuit Having Driver Circuit and Corresponding Method - A driver circuit includes an output, at least one transistor including a load section coupled between the output and a supply voltage, and a circuit coupled to a control terminal of the at least one transistor to apply a control voltage to the control terminal in at least one operation mode of the driver circuit. The control voltage is within a predetermined voltage range de-pending on a first predetermined voltage below a nominal voltage range of the output.01-29-2009
20110050290OUTPUT DRIVER CIRCUIT - An output driver circuit includes a pre-driver unit and a first driving unit. The pre-driver unit is configured to generate a driving selection signal and a driving signal from a pre-driving signal in response to a group selection signal and a code signal. The first driving unit is configured to drive a data pad in response to the driving selection signal and the driving signal.03-03-2011
20110050289INPUT BUFFER - An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals.03-03-2011
20110001520Driver circuit and image forming apparatus - A driver circuit includes a memory cell for storing data and a data switching circuit. The memory cell includes a first inverter having a first output terminal and a first input terminal and a second inverter having a second output terminal and a second input terminal. The first output terminal is connected to the second input terminal and the second output terminal is connected to the first input terminal. A switch is connected to the first input terminal so that the data is fed to the memory cell through the switch. A voltage shifter supplies a first supply voltage to the first inverter and second inverter while the data is being written into the memory cell and a second supply voltage to the first inverter and second inverter after the data has been written into the memory cell.01-06-2011
20110254593POWER SUPPLY DRIVER CIRCUIT - A power supply driver circuit for providing power to an electronic device includes a switch module, a voltage regulator and a driver module. The switch module receives a control signal and turns on according to the control signal. The voltage regulator receives a first voltage and outputs a second voltage when the switch module turns on. The driver module provides power to the electronic device when the driver module receives the second voltage.10-20-2011
20080303560DRIVE CIRCUIT FOR VOLTAGE DRIVEN ELECTRONIC ELEMENT - A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.12-11-2008
20090153200LOAD DRIVE CIRCUIT - A load drive circuit which can operate at high speed with low consumption current while performing the gate-to-source over voltage protection for its load driving field-effect transistor. A Zener function device is connected between the gate and the source of the load driving field-effect transistor, and an on/off-switch circuit to supply either on-potential or off-potential to the gate of the field effect transistor is provided. The current flowing through the Zener function device when the load driving field-effect transistor is conductive is limited by the on/off-switch circuit.06-18-2009
20090015297SOURCE DRIVER WITH CHARGE SHARING - A source driver includes four output switches, two resistors, and a charge-sharing switch. The first output switch and the first resistor are coupled in series to a first output channel of the source driver. The second output switch and the second resistor are coupled in series to a second output channel of the source driver. The third output switch is coupled in parallel to the first output switch. The fourth output switch is coupled in parallel to the second output switch. The charge-sharing switch is coupled between the first resistor and the second resistor. The third output switch and the fourth output switch are controlled to adjust the resistance of the output current path of the source driver.01-15-2009
20120169380SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.07-05-2012
20080204086APPARATUS FOR DRIVING SOURCE LINES AND DISPLAY APPARATUS HAVING THE SAME - An apparatus for driving source lines includes an output buffer, a first switch and a second switch. The output buffer outputs a first voltage and a second voltage having an opposite phase to the first voltage during an output interval including a first interval portion and a second interval portion. The first switch applies the first and second voltages to an m-th source line and an (m+1)-th source line respectively during the first interval portion and blocks the first and second voltages during the second interval portion. The second switch includes a plurality of switching elements, the second switch short-circuiting the m-th source line and the (m+1)-th source line during the second interval portion, wherein the m-th source line has at least two connecting portions to be electrically connected to the (m+1)-th source line.08-28-2008
20100321069AC-COUPLED INTERFACE CIRCUIT - A differential driver (12-23-2010
20110050291Method and apparatus for adjusting driver output current and electronic apparatus - According to an aspect of the embodiment, a driver outputs a driver current to a reception LSI, and a receiver included in the reception LSI receives an analog voltage signal corresponding to a value of the driver current as a receiver input. An A/D converter converts the voltage signal of the receiver input to a digital value, and transmits the digital value to a driver current controller in a transmission LSI. The driver current controller adjusts a number of PMOS driving stages in the driver or a number of NMOS driving stages in the driver, to make the digital value of the voltage signal of the receiver input belong to a predetermined range.03-03-2011
20110133789Driver circuit, driver apparatus, and image forming apparatus - A driver circuit drives a plurality of groups of light emitting elements. Each element includes an anode, a cathode connected to the ground, and a gate that controls electrical conduction between the anode and cathode. A first driver section simultaneously drives the anodes of the elements of the plurality of groups of elements. A second driver section simultaneously drives the gates of the elements in a corresponding group of the plurality of groups. The second driver section includes a series connection of a first switch element and a voltage level shifter. The series connection is connected between a power supply and the group of gates. The second driver section further includes a second switch element connected between the group of gates and the ground.06-09-2011
20110254594SUB SAMPLING ELECTRICAL POWER CONVERSION - The present invention relates to a solution for electrical power conversion using a first gate (10-20-2011
20100117690SEMICONDUCTOR DEVICE - A semiconductor device includes a first buffer circuit transmitting input signals, a second buffer circuit having a lower drive capability than the first buffer circuit and transmitting the input signals, and a control circuit detecting transitions of the input signals, and activating the first buffer circuit during a period when the input signals make the transitions.05-13-2010
20100117689Clock buffer circuit of semiconductor device configured to generate an internal clock signal - A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.05-13-2010
20110133788DUAL FUNCTION VOLTAGE AND CURRENT MODE DIFFERENTIAL DRIVER - A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.06-09-2011
20100213986CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.08-26-2010
20100213985FAST COMMON MODE FEEDBACK CONTROL FOR DIFFERENTIAL DRIVER - A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.08-26-2010
20120098576DATA OUTPUT DRIVER AND INTEGRATED CIRCUIT INCLUDING THE SAME - A data output driver includes a pull-up output pre-driver configured to output a plurality of pull-up signals, wherein whether each of the plurality of pull-up signals is enabled is determined in accordance with a driver mode signal, a pull-down output pre-driver configured to output a plurality of pull-down signals, wherein whether each of the plurality of pull-down signals is enabled is determined in accordance with the driver mode signal, and an output driver circuit configured to output data, wherein a driver strength of the output driver circuit is determined in accordance with the pull-up signals and pull-down signals.04-26-2012
20100060325Driver circuit - A driver circuit includes a main driver which receives an input signal and outputs a first signal corresponding to the input signal, a sub driver which receives the input signal and outputs a non-inverted signal and an inverted signal corresponding to the input signal, a differentiating circuit including resistors and a variable capacity condenser, which outputs signals by differentiating the non-inverted signal and the inverted signal, respectively, and an addition unit which outputs a high frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the non-inverted signal, or a low frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the inverted signal.03-11-2010
20080218222Circuit and method for current-mode output driver with pre-emphasis - An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.09-11-2008
20100194445POWER SUPPLY CONTROLLER WITH INPUT VOLTAGE COMPENSATION FOR EFFICIENCY AND MAXIMUM POWER OUTPUT - A controller for a power supply includes a logic block and a time-to-frequency converter. The logic block is to generate a drive signal in response to a clock signal. The drive signal is to be coupled to control switching of a power switch of the power supply to regulate an output of the power supply. The time-to-frequency converter is coupled to the logic block and generates the clock signal having a frequency responsive to a time period of the drive signal.08-05-2010
20100194446SOURCE DRIVER, DELAY CELL IMPLEMENTED IN THE SOURCE DRIVER, AND CALIBRATION METHOD FOR CALIBRATING A DELAY TIME THEREOF - A delay cell for delaying an input data signal to generate an output data signal includes a logic circuit and a bias current generator. The logic circuit is used for processing the input data signal to generate the output data signal. The bias current generator is coupled to the logic circuit for providing a first bias current to the logic circuit to control a delay time of the delay cell based on a process corner at which the delay cell is manufactured in a wafer. The bias current generator includes a first transistor coupled between a first power supply and the logic circuit for steering the first bias current of the logic circuit, wherein the first transistor is biased by a first bias voltage.08-05-2010
20110148474Circuitry and Methods for Improving Differential Signals That Cross Power Domains - Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occurs at an odd numbered stage in one differential output path and at an even numbered stage in the other differential output. Defining the power supply domain boundary in this manner can help ensure that the same logical state is present at the boundary in either of the differential output paths. This same logic signal should affect subsequent stages similarly from a speed perspective, and so should similarly affect the differential signals generated by each of the output paths. This means, among other things, that the differential signal as generated should tend to cross nearer to a midpoint voltage, which increases its compliance with certain integrated circuit specifications such as the Vox specification used for the differential data strobe in an SDRAM.06-23-2011
20100026348HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.02-04-2010
20100019806STACKED CASCODE CURRENT SOURCE - Apparatus are provided for a stacked cascode current source. An apparatus is provided for an electrical device comprising an input node and an output node. A first transistor stack is coupled to the input node. The first transistor stack includes a first transistor and a second transistor. A drain terminal and a gate terminal of the first transistor are coupled to the input node. A drain terminal of the second transistor is coupled to a source terminal of the first transistor and a gate terminal of the second transistor is coupled to the input node. A second transistor stack coupled to the first transistor stack and the output node to create a current mirror for the first transistor stack.01-28-2010
20090261865High voltage CMOS output buffer constructed from low voltage CMOS transistors - A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.10-22-2009
20090174439MULTIFUNCTIONAL OUTPUT DRIVERS AND MULTIFUNCTIONAL TRANSMITTERS USING THE SAME - A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.07-09-2009
20120146689DIFFERENTIAL SIGNAL TERMINATION CIRCUIT - A multi-mode differential termination circuit has a pair of differential input terminals for receiving external differential signals, a pair of series-connected load elements coupled between said differential input terminals, and an analog interface terminal coupled a common junction point of said load elements. A bias circuit is coupled to the common junction point of the load elements for selectively applying a bias voltage thereto in response to a digital control signal. A control input receives the digital control signal to activate the bias circuit.06-14-2012
20120306543SEMICONDUCTOR DEVICE INCLUDING OUTPUT DRIVER - According to one embodiment, a semiconductor device includes first and second pull-up deriver units, a pull-down driver unit, and a calibration circuit including a comparator. The first and second pull-up driver units adjust a pull-up driver. The pull-down driver unit adjusts a pull-down driver. When calibrating the pull-up driver, the calibration circuit causes the comparator to compare a reference voltage with the output voltage of the first pull-up driver unit based on a reference resistance. When calibrating the pull-down driver, the calibration circuit causes the comparator to compare the reference voltage with the voltage of a connection node between the second pull-up driver unit and pull-down driver unit.12-06-2012
20120306544DRIVING STRENGTH CONTROL APPARATUS, DRIVING STRENGTH CONTROL METHOD AND TERMINAL EQUIPMENT - The embodiments of the present invention provide a driving strength control apparatus and method and terminal equipment. The control apparatus comprises: a signal receiving unit to receive a test signal transmitted by a peripheral device; a signal sampling unit to sample the test signal received by the signal receiving unit to obtain a plurality of rising edges and falling edges of the test signal; an interval measuring unit to measure the time interval between a rising edge and a falling edge, or between a rising edge and another rising edge, or between a falling edge and another falling edge; and a controlling unit to adjust the driving strength imposed on the peripheral device according to the time interval. With the embodiments of the present invention, the driving strengths imposed on the peripheral device may be made identical, preventing signal deviation and improving the quality of compatibility.12-06-2012
20090273375Low-noise LVDS output driver - An LVDS output is described herein that has wideband operation down to 2.5V without degrading spur performance or dramatically increasing die are. A current mirror used in a conventional LVDS output is eliminated in such as way as to reduce noise coupling and produce especially clean output signals.11-05-2009
20090219062BUFFER CIRCUIT AND PHOTORECEIVING CIRCUIT USING THE SAME - A buffer circuit includes a first transistor having a base connected to a first power supply, an emitter as a current signal input node, and a collector as a current signal output node, a second transistor having a base connected to the first power supply, a first constant current circuit using a difference between outgoing current from the emitter of the first transistor and an input current at the current signal input node as a constant current, and determining outgoing current from the emitter of the second transistor as a current same as the constant current; and a first mirror circuit that makes a collector current of the first transistor equal to a collector current of the second transistor in which the first mirror circuit has a third transistor with a collector connected to the collector of the first transistor and a fourth transistor with a collector connected to a collector of the second transistor, a first operating point voltage is provided to the current signal output node between the third transistor and the first transistor, and a second operating point voltage based on the first operating point voltage is provided to a node between the fourth transistor and the second transistor.09-03-2009
20090115462DRIVER CIRCUIT WITH EMI IMMUNITY - A driver circuit suitable for outputting a signal onto an output line affected by conducted EMI, has a slope control circuit and an output circuit, (op-amp, Mo, M05-07-2009
20100253391APPARATUS AND METHOD FOR CONTROLLING DELAY STAGE OF OFF-CHIP DRIVER - A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.10-07-2010
20090184737SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH AUXILIARY CURRENT SINK - A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit outputting a detection signal in response to a level of an input signal. An input buffer buffers the input signal by performing a differential amplifying operation through a first current sink unit. A second current sink unit, sharing an output with the input buffer, differentially amplifies the input signal of the input buffer in response to a level of the detection signal.07-23-2009
20080211546INTEGRATED DRIVER CIRCUIT FOR A LIN BUS - An integrated driver circuit is provided for a LIN bus comprises a first input terminal, a second input terminal, and an output terminal, which is to be connected to a bus line of the LIN bus and at which an output data signal, dependent on an input data signal, is output, whereby the output data signal is output according to a first or according to at least one second LIN bus specification depending on whether the input data signal is applied at the first input terminal or the at least second input terminal.09-04-2008
20090091358Compensated output buffer for improving slew control rate - The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes. The compensation codes are provided by a compensation circuit, which sense the variation in PVT conditions and reflect these variations in the compensation codes.04-09-2009
20110050288SEMICONDUCTOR SWITCH - A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.03-03-2011
20120062280OUTPUT DRIVER - An output driver includes a control signal generation unit configured to generate a control signal in response to a driving strength signal and a power supply voltage level, and a driving signal generation unit configured to buffer a pre-driving signal and generate a driving signal for driving an output data, wherein a driving strength of the driving signal is adjusted in response to the control signal.03-15-2012
20110316590Driver Supporting Multiple Signaling Modes - A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.12-29-2011
20110102024DATA OUTPUT CIRCUIT - The data output circuit includes a pull-up signal generator, a pull-down signal generator and a driver. The pull-up signal generator is configured to generate a pull-up signal that is driven to a first level state when a pre-pull-up signal is activated and driven to a second level state after a first delay period. The pull-down signal generator is configured to generate a pull-down signal that is driven to a third level state when a pre-pull-down signal is activated and driven to a fourth level state after a second delay period. The driver is configured to drive output data in response to receiving either the pull-up signal and the pull-down signal.05-05-2011
20120043997METHOD AND APPARATUS FOR REDUCING TRANSMITTER AC-COUPLING DROOP - As part of a transmitter and receiver system a droop compensator is provided between the channel isolation device and the driver system to compensate for reduced transition densities. The droop compensator is configured to improve power transfer to the channel in response to reductions in transition density without affecting power transfer during periods of high transition density. The droop compensator creates an impedance mismatch between the matching circuit and driver in relation to the line impedance. The droop compensator may comprise passive elements, such as capacitors, inductors, or resistor, or active elements including transistors or power control modules. The droop compensator may be configured to operate with transformer line couplers or capacitor line couplers, and either current drivers or voltage drivers.02-23-2012
20120206168INVERTER AND SCAN DRIVER USING THE SAME - An inverter is capable of improving the reliability of driving. The inverter includes a first transistor and a second transistor. The first transistor is coupled between a first power source and an output terminal of the inverter, and has a first gate electrode coupled to a first input terminal of the inverter and a second gate electrode coupled to a third power source. The second transistor is coupled between the output terminal and a second power source, and has a first gate electrode coupled to a second input terminal of the inverter and a second gate electrode coupled to the third power source.08-16-2012
20110156763RESPONSE OF AN UNDER-DAMPED SYSTEM - An embodiment of a circuit for driving an under-damped system comprises first and second signal generators. The first generator is operable to generate a first drive signal. And the second generator is operable to receive the first drive signal and a second drive signal, and to generate from the first and second drive signals a system drive signal having a first amplitude for a first duration and having a second amplitude after the first duration, the system drive signal operable to cause the under-damped system to operate in a substantially damped manner. Either or both of the first and second generators may be programmable such that one may adjust the response of any under-damped system by generating an appropriate drive signal instead of by physically modifying the system itself. In another embodiment, an under-damped system is caused to oscillate at a damped frequency having a first phase, and is also caused to oscillate at substantially the damped frequency having a second phase such that the oscillation at the first phase substantially cancels the oscillation at the second phase. Such embodiments may allow one to realize a faster settling time without slowing down the response time of an under-damped system.06-30-2011
20110156764METHOD FOR CALIBRATING AND CONTROLLING SIGNAL SLEW RATE, AND OUTPUT STAGE USING THE SAME - An output stage configured to control a driving voltage thereof is provided. The output stage includes: a first switching current module, coupled to a node for outputting a first current; a second switching current module, coupled to the node for outputting a second current; a switching capacitor module with a capacitance, coupled to the node; a calibrating control circuit, for calibrating the first current, the second current and the capacitance; a time constant calibrating circuit, for generating a reference slew rate, and controlling the calibrating control circuit to selectively calibrate the first current, the second current and the capacitance, such that a ratio of the first current and the capacitance and the ratio of the second current and the capacitance conform to the reference slew rate; and a voltage clamper for setting a high/low voltage range and limiting a amplitude of the driving voltage within the high/low voltage range.06-30-2011
20110156762OPERATIONAL CIRCUIT AND RELATED CONTROL METHOD - An operational circuit includes: a first stage having a first input terminal for receiving an input signal and a second input terminal for receiving an output signal of the operational circuit, for outputting a first control signal at a first output terminal and a second control signal at a second output terminal according to the input signal and the output signal; and a second stage coupled to the first stage, for generating the output signal according to a first driving current controlled by the first control signal and a second driving current controlled by the second control signal; and a protection circuit coupled between the first stage and the second stage, for adjusting the first driving current from a first predetermined threshold current toward a second predetermined threshold current when the first driving current reaches the first predetermined threshold current.06-30-2011
20110156761OPERATIONAL CIRCUIT AND RELATED CONTROL METHOD - An operational circuit includes: a first stage having a first input terminal for receiving an input signal and a second input terminal for receiving an output signal of the operational circuit, for outputting a first control signal at a first output terminal and a second control signal at a second output terminal according to the input signal and the output signal; a second stage coupled to the first stage, for generating the output signal according to a first driving current controlled by the first control signal and a second driving current controlled by the second control signal; and a protection circuit coupled between the first stage and the second stage, for detecting the first driving current to selectively adjust the first control signal.06-30-2011
20120001662CONTROL OF A RESONANT SWITCHING SYSTEM WITH MONITORING OF THE WORKING CURRENT IN AN OBSERVATION WINDOW - Controlling a resonant switching system, which includes a first switch and a second switch in a half-bridge configuration for driving a resonant load. A corresponding control system includes command means for switching on and switching off the switches alternatively according to a working frequency of the switching system. The control system includes detection means for detecting a zeroing of a working current being supplied by the switching system to the resonant load in a temporal observation window; the observation window follows each switching off of at least one of the switches, and has a length equal to a fraction of a working period of the switching system. Correction means are then provided for modifying the working frequency in response to each detection of the zeroing in the observation window.01-05-2012
20120001661VARIABLE RESISTOR VOLTAGE DRIVER WITH SELF-NOISE COMPENSATION CIRCUIT - A multi-PAM line driver circuit to drive input data along a transmission line from a voltage source is disclosed. The driver circuit includes a voltage source to supply a regulated voltage and a regulator current. A main branch is coupled between the voltage source and the transmission line and includes variable impedance circuitry. The main branch draws a drive current from the voltage source. A compensating branch is coupled to the voltage source in parallel with the main branch and includes a second variable impedance circuit to draw a compensating current from the voltage source based on the drive current, such that a sum of the drive current and the compensating current is substantially constant during the transmission of the input data.01-05-2012
20090045852Low Voltage Differential Signalling Driver with Pre-Emphasis - There is provided a LVDS driver arranged to receive an input signal which switches between two voltage levels. The driver comprises a pre-emphasis block (02-19-2009
20100308872Monolithic Low Impedance Dual Gate Current Sense MOSFET - A power switch includes a first power transistor having a first source electrode, a first gate electrode, and a first drain electrode, and a second power transistor having a second source electrode, a second gate electrode, and a second drain electrode. The power switch further includes a first pilot transistor has a third source electrode, a third gate electrode, and a third drain electrode. The first, second and third drain electrodes are electrically connected together. The first and second source electrodes are electrically connected together. The first and third gate electrodes are electrically connected together and can be biased independently from the second gate electrode. The first power transistor is the same size as or smaller than the second power transistor and the first power transistor is larger than the first pilot transistor. The first power transistor, the second power transistor, and the first pilot transistor are monolithically integrated in an integrated circuit.12-09-2010
20120206167Multi-Supply Symmetric Driver Circuit and Timing Method - Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.08-16-2012
20090134919Input buffer for high-voltage signal application - An input buffer for a high-voltage signal application is provided. The input buffer uses a clamper and an inverter to clamp the output voltage in a proper range even if the input voltage is too high or too low. The proper range of the output voltage is controlled by a voltage source and the ground, so that an electrical device can be triggered safely by the output voltage.05-28-2009
20120025872Buffer Enable Signal Generating Circuit And Input Circuit Using The Same - An input circuit comprises a buffer enable signal generating circuit for generating a buffer enable signal having an predetermined enable period in response to an external command, and a buffer circuit for buffering and outputting the external command and an external address signal in response to the buffer enable signal.02-02-2012
20120025871SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a first buffer element configured to buffer a first mode signal inputted from the outside of the semiconductor device, and a second buffer element configured to buffer a second mode signal inputted from the outside by being enabled in response to an output signal of the first buffer element.02-02-2012
20110089979SOURCE DRIVER WITH CHARGE SHARING - A source driver includes an output buffer for outputting a driving signal; a first current path coupled between the output buffer and a data line; and a second current path coupled in parallel to the first current path. During a first driving period, the output buffer utilizes both the first current path and the second current path to drive the data line. During a second driving period, the output buffer utilizes only the first current path to transmit the driving signal so as to improve the stability of the source driver.04-21-2011
20120212260Dynamic Feedback-Controlled Output Driver with Minimum Slew Rate Variation from Process, Temperature and Supply - In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.08-23-2012
20100244904Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials - A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages. The buffer includes a logic control circuit, a first MOS transistor provided between a power supply for feeding the first high voltage and an output terminal, the first MOS transistor including a gate receiving a control signal of the first high voltage level outputted from the logic control circuit, and a backgate receiving the first high voltage, a second MOS transistor provided between a power supply for feeding the second high voltage and the output terminal, the second MOS transistor including a gate receiving a control signal of the second high voltage level outputted from the logic control circuit, and a backgate receiving the second high voltage, and a first switch circuit provided between the first MOS transistor and the output terminal and controlled ON/OFF state thereof by the control signal of the second high voltage level.09-30-2010
20100244905Input buffer circuit of semiconductor device having function of adjusting input level - An input buffer circuit of a semiconductor device, the input buffer circuit including a buffer, the buffer configured to adjust an input level of an input signal in response to a selected bias voltage, a voltage generating and distributing unit, the voltage generating and distributing unit configured to generate and distribute a plurality of bias voltages having different levels, and a selector, the selector configured to select from among the plurality of bias voltages according to an applied selection signal and to apply the selected bias voltage to the buffer.09-30-2010
20100244906CURRENT DRIVE CIRCUIT - A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.09-30-2010
20120313669Level Shifter and Boost Driving Circuit - A level shifter and an associated booster driving circuit are provided. The level shifter includes an input stage and an output stage. The input stage includes an input switch, which receives an input signal and is selectively turned on according to the input signal. The output stage outputs a gate driving signal. The gate driving signal is at a low logic level when the input switch is turned on, and is at a high logic level when the input switch is turned off. The logic level of the input signal is substantially the same as the logic level of the gate driving signal.12-13-2012
20120126858LOAD DRIVING APPARATUS - A load driving apparatus for driving a load with a constant current includes a shunt resistor and a driver circuit. A shunt current corresponding to the constant current flows though the shunt resistor. The driver circuit is connected to a first end of the shunt resistor to supply the constant current corresponding to the shunt current to the load. The driver circuit includes a reference voltage source for generating a predetermined reference voltage. The driver circuit adjusts the magnitude of the constant current by performing a feedback-control of the magnitude of the shunt current in such a manner that a first voltage corresponding to the reference voltage and a second voltage corresponding to a voltage at the first end of the shunt resistor become equal to each other.05-24-2012
20120161816VOLTAGE-MODE DRIVER WITH PRE-EMPHASIS - A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.06-28-2012
20120126859LOAD DRIVER WITH CONSTANT CURRENT VARIABLE STRUCTURE - A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.05-24-2012
20120126857COMMAND BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - A command buffer circuit of a semiconductor apparatus includes a first buffer configured to receive a first command signal and generate a first command control signal, a second buffer configured to receive a second command signal and generate a second command control signal, a second block configured to select and output the first command control signal or the second command control signal in response to a rank control signal, and a control signal generation block configured to generate the rank control signal in response to a single rank signal and a chip select signal.05-24-2012
20120161818BI-DIRECTIONAL DRIVER - An H-bridge driver without implementing with the PWM mode is disclosed. The H-bridge driver of the invention includes a non-inverting amplifier and an inverting amplifier commonly connected to the control signal. When the control signal exceeds the reference, the non-inverting amplifier commonly drives the first pair of transistors diagonally connected to the load. The low side transistor fully turns on but the high side transistor linearly operates. When the control signal is less than the reference, the inverting amplifier commonly drives the second pair of transistors also diagonally connected to the load.06-28-2012
20100207668CIRCUIT DEVICE NAD METHOD OF CONTROLLING CIRCUIT DEVICE - A circuit device has a first output buffer including a first adjustment circuit for adjusting a level of the first output signal, a first input buffer connected to the first output buffer, an adjustment controller for outputting a test signal to the first output buffer, outputting a control signal to the first adjustment circuit so that the level of the first output signal is adjusted on the basis of the control signal, monitoring an output of the first input buffer, and adjusting the control signal on the basis of the monitoring the output of the first input buffer, a second output buffer connected to the adjustment controller and operable to assume either an active or a non-active state, for outputting a second output signal when controlled to assume an active state, including a second adjustment circuit, and a second input buffer.08-19-2010
20100207667METHOD OF DRIVING GATE LINES, GATE LINE DRIVE CIRCUIT FOR PERFORMING THE METHOD AND DISPLAY DEVICE HAVING THE GATE LINE DRIVE CIRCUIT - A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.08-19-2010
20120212261CURRENT DRIVING CIRCUIT - A current driving circuit includes a constant current source circuit delivering a driving current to a load, and an output voltage difference amplifier circuit detecting a voltage change produced at a load driving end during a preset time period and delivering a current or a voltage corresponding to the voltage change to the load during a time period different from the preset time period. During first time period, capacitance circuit compares potential during a preceding time period to that during the current time period, and causes a potential at the load driving end during the current time period to store in any of capacitance elements depending on result of comparison. The amplifier circuit buffering an average value of the potential values stored in the capacitance elements during the second time period following the first time period, to deliver the average value to the load.08-23-2012
20110181322Device and method for generating a current pulse - A device for producing a current pulse includes supply terminals for providing a power supply voltage, and a switch which is situated in a control current branch between the supply terminals, which switch is configured to switch a control current through the control current branch as a function of an actuation signal. The device also has a current mirror having a control transistor and a signal transistor, the control transistor being situated in series to the first switch in the control current branch, and the signal transistor being configured to provide the current pulse as a function of the control current through the control transistor.07-28-2011
20120161817ELECTRICAL LOAD DRIVING APPARATUS - The electrical load driving apparatus includes means for alternately lowering the gate voltages of two current supply transistors connected in parallel to each other at regular time intervals, a current being supplied to an electrical load through drain-source paths of both the current supply transistors, and means for detecting wire breakage in two current supply wires in which the current supply transistors are interposed respectively at portions opposite the electrical load with respect to the current supply transistors based on the drain-source voltages of the current supply transistors.06-28-2012
20090058474Output driver of semiconductor memory device - An output driver of a semiconductor memory device is capable of controlling falling and rising edges of an output data. The output driver prevents the first output data form being relatively deteriorated compared with other output data in case that the output data are terminated centering around a predetermined voltage level. The output driver includes a pull-up driver for pull-up driving an output terminal in response to a pull-up control signal, a pull-down driver for pull-down driving the output terminal in response to a pull-down control signal, a first acceleration driver for accelerating the pull-up control signal, and a second acceleration driver for accelerating the pull-down control signal, wherein the first and second acceleration drivers are activated when a first data is outputted.03-05-2009
20120176163DRIVING STAGE AND RELATED DRIVING METHOD - A driving stage of a signal transmitting system includes: a driver powered by a first supply source and arranged to output a driving signal via an output port capable of being connected to an external device; and a controllable isolating circuit including: a switching circuit arranged to selectively couple the first supply source to the output port, and a detecting circuit arranged to detect a specific signal derived from the signal transmitting system, wherein when the specific signal indicates the signal transmitting system turns into a power-off state, the detecting circuit controls the switching circuit to disconnect the output port from the first supply source.07-12-2012
20120074987ELECTRONIC DEVICE AND METHOD FOR BUFFERING - A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.03-29-2012
20100271080DRIVER COMPARATOR CIRCUIT - A first resistor is arranged such that a first voltage is applied to a first terminal thereof, and a second terminal thereof is connected to an input/output terminal. The first voltage is applied to a first terminal of a second resistor. A tail current source generates a predetermined tail current. A current switch receives data to be transmitted to a second device, selects one from among the second terminals of the first and second resistors, and connects the terminal thus selected to the tail current source. A voltage dividing circuit includes a third resistor and a fourth resistor provided in series between the second terminals of the first resistor and the second resistor. A load balancer includes a fifth resistor arranged such that a second voltage is applied to a first terminal thereof, and a second terminal thereof is connected to the second terminal of the second resistor.10-28-2010
20100271079POWER SEMICONDUCTOR DEVICE - Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.10-28-2010
20100271078CIRCUITRY IN A DRIVER CIRCUIT - A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.10-28-2010
20100007386Semiconductor device, display panel, and electronic apparatus - A single-channel thin-film transistor buffer includes a first output stage including first and second thin-film transistors connected in series, a seventh thin-film transistor having one main electrode connected to a control electrode of the first thin-film transistor (first control line), the other main electrode connected to a power source of the second thin-film transistor, and a control electrode connected to a second control line, an eighth thin-film transistor having one main electrode connected to a control electrode of the second thin-film transistor (second control line), the other main electrode connected to the power source of the second thin-film transistor, and a control electrode connected to the first control line, and an eleventh thin-film transistor having a control electrode connected to an output terminal of a second output stage connected in parallel with the first output stage and one main electrode connected to the first control line.01-14-2010
20120256660SOURCE DRIVER AND RECEIVER THEREOF - A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.10-11-2012
20120256659CURRENT SHARE COMPENSATION DESIGN - A current share system for providing current to a load includes a first power supply module that controls a first voltage converter to provide a first current to the load, that transmits synchronization information using a first pin, and that transmits at least one second type of information using the first pin. A second power supply module receives the synchronization information at a second pin, receives the at least one second type of information at the second pin, and controls a second voltage converter to provide a second current to the load based on the synchronization information and the at least one second type of information.10-11-2012
20120262204DRIVER CIRCUIT HAVING AN INSULATED GATE FIELD EFFECT TRANSISTOR FOR PROVIDING POWER - In one embodiment, a transistor is connected between a power supply terminal and an output terminal. One end of a first resistor is connected to a gate of the transistor. The other end of the first resistor is connected to a gate voltage terminal. One end of a second resistor is connected to the gate voltage terminal. One end of a first switch is connected to the other end of the second resistor. The first switch is controlled by a control signal controlling the transistor. One end of a second switch is connected to the other end of the first resistor. The other end of the second switch is connected to the output terminal. The second switch is controlled by a signal outputted from the one end of the first switch.10-18-2012
20120262205Circuit and Method for Current-Mode Output Driver With Pre-Emphasis - An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.10-18-2012
20120229172POWER SUPPLY SWITCHING CIRCUIT - Provided is a power supply switching circuit with a smaller circuit scale. When a detector (09-13-2012
20110121868CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.05-26-2011
20100327918HIGH CURRENT EMITTER DRIVE UNIT CELL - A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor. The second transistor is maintained in saturation for a first portion of the input signal range with the first transistor acting as a source follower for that range. Linear current flow through the resistor results allowing high resolution control in the low current range. The second transistor departs saturation in a second portion of the range for the input signal resulting in saturation mode square-law behavior dominating the first transistor which, in turn, causes a rapid increase in current through its channel in response to higher input signal level thereby allowing a lower resolution but higher current for emitter drive at higher temperatures.12-30-2010
20100327917OUTPUT DEVICE AND TEST APPARATUS - An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched.12-30-2010
20120319739SEMICONDUCTOR DEVICE SUPPLYING CHARGING CURRENT TO ELEMENT TO BE CHARGED - A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.12-20-2012
20130169317OUTPUT DRIVER - An output driver includes, inter alia: a code generation unit disposed between a first node and a second node and configured to generate pull-up codes, according to a voltage difference between the first node and an output node, pull-down codes, according to a voltage difference between the output node and the second node, and a driving unit configured to drive the output node in response to a pull-up signal and a pull-down signal to generate output data, wherein a voltage level of the output data is controlled by a driving force which is set according to a combination of the pull-up and pull-down codes.07-04-2013
20120326754High Performance Pre-Mixer Buffer in Wireless Communications Systems - According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.12-27-2012
20100225362Reduced line driver output dependency on process, voltage, and temperature variations - According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.09-09-2010
20100231268Low voltage differential signalling driver - A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, whilst second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.09-16-2010
20100231267Input/Output Driver with Controlled Transistor Voltages - In an embodiment, an integrated circuit comprises core circuitry and at least one driver circuit. The core circuitry is powered by a first supply voltage during use, and comprises a control circuit configured to generate a pull up control signal, a pull down control signal, and at least one reference voltage. The driver circuit is powered by a second supply voltage during use, the second supply voltage having a greater magnitude than the first supply voltage. The driver circuit is connected to a pad to be connected to a pin on a package of the integrated circuit. The driver circuit comprises a cascode connection of a first transistor and a second transistor, and a capacitor coupled between a first gate terminal of the first transistor and a second gate terminal of the second transistor. The first gate terminal is coupled to receive the pull down control signal.09-16-2010
20100231266LOW VOLTAGE AND LOW POWER DIFFERENTIAL DRIVER WITH MATCHING OUTPUT IMPEDANCES - The present invention provides a system and a method for driving a differential signal which includes a differential data input, a plurality of switches coupled to a current source for steering current depending on the differential data input, a first differential output and a second differential output and a coupled to at least two of the plurality of switches and a first source follower and a second source follower coupled to the first differential output for controlling output impedance. This architecture prevents the common mode noise reflected from the driver from becoming a differential signal and meets the requirements of the LVDS and SubLVDS standard down till 1.62V. Also this architecture is capable of operating in Gbps range making it a high-speed differential driver with very low power.09-16-2010
20120280723Driver with Impedance Control - An integrated circuit (IC) may be configured to communicate signals to an external device (e.g., a memory) via a driver. The driver may include a plurality of driver circuits arranged in parallel with respect to each other. Each driver circuit in turn may include a plurality of driver sub-circuits. Based, for example, on the load presented by the external device and/or operating conditions of the IC, a control circuit may provide signals that enable individual ones of driver circuits to result in a selected driver strength. The control circuit may also provide impedance control signals that enable or disable individual sub-circuits within one or more driver circuit, to thereby control the output impedance of each such driver circuit.11-08-2012
20120280724APPARATUS AND METHODS OF REDUCING PRE-EMPHASIS VOLTAGE JITTER - One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.11-08-2012
20110279150BUFFER OPERATIONAL AMPLIFIER WITH SELF-OFFSET COMPENSATOR AND EMBEDDED SEGMENTED DAC FOR IMPROVED LINEARITY LCD DRIVER - A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.11-17-2011
20130009670SIGNAL OPERATING CIRCUIT - A signal operating circuit includes: a loading device; an input stage coupled to the loading device, for converting an output signal into an input signal according to a controlling signal; a latching stage coupled to the loading device and the input stage for latching the output signal according to the controlling signal; and a controlling circuit coupled to the latching stage for at least adjusting an operating current of the latching stage to compensate a loading deviation value according to the loading deviation value of the loading device.01-10-2013
20130009669Voltage Mode Driver - A differential mode driver for driving a differential signal, comprises, at least one unit cell, wherein each of the at least one unit cell comprises at least one resistor and at least one switch resistance and wherein the ratio of the resistances of the at least one resistor and the at least one switch resistance is greater than or equal to a predefined ratio.01-10-2013
20130009671SWITCHING ELEMENT DRIVING DEVICE AND METHOD - A slew rate regulation circuit varies a slew rate of a waveform of a voltage outputted to a DC motor through a N-channel MOSFET. The slew rate regulation circuit lowers a peak level by dispersing frequency components of switching noise, which develops in a frequency range higher than a frequency range determined by a carrier frequency.01-10-2013
20130021066Method and Apparatus for Driving a Display Device with Charge Sharing - A driving device for a display device is disclosed. The driving device includes a first output buffer, for generating a first source driving signal at a first output end; a second output buffer, for generating a second source driving signal at a second output end; and an electric charge storage unit, including a voltage sensing end coupled to the first output buffer and the second output buffer, for receiving and storing electric charges released by the first output buffer via the voltage sensing end when a level of the first source driving signal decreases, and for outputting the electric charges to the second output buffer via the voltage sensing end when a level of the second source driving signal increases.01-24-2013
20120242374BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT - A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.09-27-2012
20080252338Single Threshold and Single Conductivity Type Amplifier/Buffer - An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.10-16-2008
20090160495LOW POWER DIFFERENTIAL SIGNALING TRANSMITTER - A low power differential signaling transmitter includes a switchable current source apparatus and a differential signaling generator coupled to the switchable current source apparatus. The switchable current source apparatus receives a first input voltage and a second input voltage, and generates a plurality of reference currents according to the first input voltage and the second input voltage. The differential signaling generator includes a plurality of first transistors, a plurality of second transistors, a first output voltage terminal and a second output voltage terminal. The on or off states of the first transistors and the second transistors are controlled by the reference currents. The first output voltage terminal outputs a first output voltage, and the second output voltage terminal outputs a second output voltage. The first output voltage and the second output voltage are determined according to the on or off states of the first and second transistors.06-25-2009
20130169318GATE-STRESS TEST CIRCUIT WITHOUT TEST PAD - A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.07-04-2013
20130169319SIGNAL PROCESSING CIRCUIT, DRIVER CIRCUIT, AND DISPLAY DEVICE - A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.07-04-2013
20080224737Current mirror circuit - Provided is a semiconductor device capable of evenly distributing an effect of charge on each gate of adjacent MOS transistors, which form a current mirror circuit, during a production process of the semiconductor device, by directly connecting the gates of the adjacent MOS transistors, which form the current mirror circuit, to each other with polysilicon and by further connecting a fuse, which is connected to a substrate, to a gate portion that is connected with the polysilicon, and capable of reducing the effect by dissipating the charge to the substrate. The fuse is cut off during a trimming process.09-18-2008
20080224736SEMICONDUCTOR DEVICE SUPPLYING CHARGING CURRENT TO ELEMENT TO BE CHARGED - A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.09-18-2008
20130169316TRI-STATE CONTROL FOR A LINE DRIVER - A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.07-04-2013
20130141140STRESS REDUCED CASCODED CMOS OUTPUT DRIVER CIRCUIT - An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.06-06-2013
20090201054DRIVING CIRCUITS IN ELECTRONIC DEVICE - In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced.08-13-2009
20120249188DIFFERENTIAL OUTPUT BUFFER HAVING MIXING AND OUTPUT STAGES - An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.10-04-2012
20100085083GATE DRIVING CIRCUIT HAVING A LOW LEAKAGE CURRENT CONTROL MECHANISM - A gate driving circuit having a low leakage current control mechanism is disclosed for providing a plurality of gate signals forwarded to a plurality of gate lines respectively. The gate driving circuit includes a plurality of shift registers. Each shift register includes a driving unit, an energy store unit, a buffer unit, a voltage regulation unit, and a control unit. The driving unit generates a gate signal based on a driving control voltage and a first clock. The buffer unit functions to receive a start pulse signal. The energy store unit provides the driving control voltage through performing a charging process based on the start pulse signal. The control unit generates a control signal based on the first clock and a second clock having a phase opposite to the first clock. The voltage regulation unit regulates the driving control voltage based on the control signal.04-08-2010
20130093473DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF - A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.04-18-2013
20130093472SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node.04-18-2013
20080197892BUFFER CIRCUIT AND CONTROL METHOD THEREOF - The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion 08-21-2008
20110221479SENSOR OUTPUT IC AND SENSOR DEVICE - A sensor output IC has a switching element that turns on and off between output terminals based on a detection signal from a sensor, and a temperature-limiting circuit that maintains the switching element in an off state when a temperature at the sensor output IC becomes a predetermined value or more.09-15-2011
20110248748LOAD DRIVE CIRCUIT WITH CURRENT BIDIRECTIONAL DETECTING FUNCTION - A load drive circuit with a current bidirectional detecting function includes: a current bidirectional switch connected between a first wire and a second wire and through which a first forward current flows in a direction from the first wire to the second wire and a first backward current flows in a direction from the second wire to the first wire; a forward current detecting switch connected to the first wire and into which a second forward current correlated to the first forward current flowing through the current bidirectional switch flows; a backward current detecting switch connected to the second wire and into which a second backward current correlated to the first backward current flowing through the current bidirectional switch flows.10-13-2011
20130147523CIRCUIT FOR DRIVING A TRANSISTOR - One aspect is a circuit having an input configured to receive an input signal, and an actuation output configured to be connected to an actuation terminal of a transistor. A measurement arrangement is configured to ascertain at least one of a load current through a load path of the transistor, and a load voltage across the load path of the transistor and to provide a measurement signal that is dependent on at least one of the load current and the load path voltage. An actuation current source is configured to receive the measurement signal and to provide an actuation current at the actuation output, the actuation current having a current level dependent on the measurement signal.06-13-2013
20130147524TRANSISTOR CIRCUIT, FLIP-FLOP, SIGNAL PROCESSING CIRCUIT, DRIVER CIRCUIT, AND DISPLAY DEVICE - A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr06-13-2013
20100289534INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION - An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.11-18-2010
20120274366Integrated Power Stage - In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die.11-01-2012
20110234262DRIVER CIRCUIT OF DISPLAY DEVICE - A driver circuit includes a mode control unit and a plurality of source drivers to drive a display panel including pixel cells on each scan line. Each source driver has M driving channels, and two subsets of the driving channels are respectively in a first mode and a second mode according to a preset mode sequence. The 109-29-2011
20100315130DRIVE CIRCUIT - A drive circuit that outputs low-voltage differential signals to an external load circuit, including: first and second nodes to which the external load circuit is connected; a first series circuit including first and second switching elements, connected in series using the first node as a common node; a second series circuit including third and fourth switching elements, connected in series using the second node as a common node; and a first current source that outputs a predetermined current to the first and second series circuits, in which a back gate of a transistor of a first conductivity type included in at least one of the first and third switching elements or the first current source is forward-biased.12-16-2010
20130181747GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.07-18-2013
20130194004INTEGRATED CIRCUIT HAVING INPUT/OUTPUT CELL ARRAY HAVING SINGLE GATE ORIENTATION - An integrated circuit (IC) including a core area containing active devices and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. The at least one I/O cell includes a gate orientation, a pre-driver module, and at least one post-driver module. The pre-driver module and the at least one post-driver module are offset from each other by an angle between zero and ninety degrees with respect to the gate orientation. The gate orientation for every one of the at least one I/O cell is substantially the same.08-01-2013
20130194005GENERATION OF DIFFERENTIAL SIGNALS - The invention relates to an apparatus comprising a differential driver module configured to generate at least one differential signal having steep rise and fall times for at least partially reducing common-mode noise. The invention also relates to a method for causing the differential driver to generate the signal and a system comprising the differential driver and a conductor module for transmission of the generated differential signal. A computer program for performing the method and a computer-readable medium is also part of the invention.08-01-2013
20120032707Load driving device - A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential of the ground terminal is at least a predetermined value to maintain a non-conductive state of the output transistor when a polarity of a power supply coupled between the power supply and ground terminals is normal, and a reverse connection protection circuit coupled between the control terminal and the ground terminal, which brings the output transistor into a conductive state when a polarity of the power supply is reversed.02-09-2012
20090315592PREEMPHASIS DRIVER WITH REPLICA BIAS - In one embodiment, a system includes a replica driver that includes n-type digital-to-analog converter (NDAC) current sources. The replica driver can produce a reference voltage based on current supplied by the NDAC current sources. The system includes driver fingers that are coupled to the replica driver and each include a driver bias circuit and an output driver. The driver bias circuit includes an operational amplifier (op-amp) that can adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.12-24-2009
20130200926DRIVER CIRCUIT - A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.08-08-2013
20130099830INTEGRATED CIRCUIT CHIP - An integrated circuit chip includes a first single ended type buffer configured to receive a first signal through a first pad, a second single ended type buffer configured to receive a second signal through a second pad, a differential type buffer configured to receive a third signal through the first pad and the second pad, a strobe input unit configured to receive a strobe signal synchronized with the third signal inputted to the first pad and the second pad, and a buffer control unit configured to control activation of the first and second single ended type buffers and the differential type buffer in response to the strobe signal.04-25-2013
20120086478SEMICONDUCTOR DEVICE INCLUDING A TEST CIRCUIT OF A MULTIVALUED LOGIC CIRCUIT HAVING AN IMPEDANCE CONTROL - A semiconductor device, having an input terminal configured to receive a multi-valued input signal as input, the multi-valued input signal including a plurality of values, a multi-valued logic circuit that operates with a multi-valued function and output binary signals to an output section in response to the input signal that has been input to the input terminal, the output section having a number of nodes being one less than a number of the plurality of values of the multi-valued input signal, and an impedance control circuit that is connected to the input terminal and the output section, and changes a combined resistance value in response to the binary signals of the plurality of nodes to change a current which flows in the input terminal.04-12-2012
20120086477GATE SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE - Provided is a gate signal line driving circuit including: 2n clock signal lines where 2n-phase clock signals are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with the 2n clock signal lines and outputting a gate signal from an output terminal, in which each of the basic circuits includes a high-voltage applying switching circuit where one clock signal line is connected to an input side and applies a voltage applied to the clock signal line to the output terminal and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit, and a clock signal line where a clock signal having an inverse phase is connected to a switch of the off-signal applying switching circuit.04-12-2012
20120086476Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit - Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.04-12-2012
20130207694HIGH SPEED COMMUNICATION INTERFACE WITH AN ADAPTIVE SWING DRIVER TO REDUCE POWER CONSUMPTION - A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.08-15-2013

Patent applications in class Current driver

Patent applications in all subclasses Current driver