Class / Patent application number | Description | Number of patent applications / Date published |
327099000 | Having selection between plural continuous waveforms | 9 |
20090160492 | Glitchless Clock Multiplexer Optimized for Synchronous and ASynchronous Clocks - A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit. | 06-25-2009 |
20100001767 | CLOCK SIGNAL SELECTION CIRCUIT - There is provided a clock signal selection circuit including: a first AND circuit (AND_A | 01-07-2010 |
20100244902 | APPARATUS AND METHOD FOR PROVIDING A CLOCK SIGNAL - A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal. | 09-30-2010 |
20100315129 | CLOCK SIGNAL SWITCHING DEVICE, CLOCK SIGNAL SWITCHING METHOD, DATA BUS SWITCHING DEVICE, AND DATA BUS SWITCHING METHOD - A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals. | 12-16-2010 |
20110227610 | SELECTOR CIRCUIT - A selector circuit for selecting and outputting plural pieces of output data from input data including plural bits, in which each of the pieces of the output data including plural bits is provided. The selector circuit includes plural first swap circuits, each of the bits of the input data being input to any of the plural first swap circuits, the plural first swap circuits being configured to reorder and output the input bits or output the input bits without reordering; a bus configured to transfer the bits output from the first swap circuits; and plural data field specifying circuits respectively configured to select and take out a predetermined number of continuous bits on the bus. Plural bits taken out by any of the data field specifying circuits are included in the respective pieces of the output data. | 09-22-2011 |
20110316589 | METHOD OF COMPENSATING CLOCK SKEW, CLOCK SKEW COMPENSATING CIRCUIT FOR REALIZING THE METHOD, AND INPUT/OUTPUT SYSTEM INCLUDING THE CLOCK SKEW COMPENSATING CIRCUIT - A method of compensating clock skew may include generating (2M+1) detected values by applying (2M+1) delay clock signals to (2M+1) pieces of delay data, wherein M is a natural number, determining a dominant logic value based on a comparison of a number of logic high detected values and a number of logic low detected values from among the (2M+1) detected values, determining a median delay time based on a number of the (2M+1) detected values having the dominant logic value, and adjusting a phase of a clock signal using the median delay time. | 12-29-2011 |
20120194224 | PRE-EMPHASIS CIRCUIT AND DIFFERENTIAL CURRENT SIGNALING SYSTEM HAVING THE SAME - Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver. | 08-02-2012 |
20140111249 | Time Distribution Switch - Systems and methods for detecting the failure of a precision time source using an independent time source are disclosed. Additionally, detecting the failure of a GNSS based precision time source based on a calculated location of a GNSS receiver is disclosed. Moreover, the system may be further configured to distribute a time derived from the precision time source as a precision time reference to time dependent devices. In the event of a failure of the precision time source, the system may be configured to distribute a time derived from a second precision time source as the precision time signal during a holdover period. | 04-24-2014 |
20140125382 | EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE - Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit. | 05-08-2014 |