Class / Patent application number | Description | Number of patent applications / Date published |
327090000 | Comparison between two characteristics of an input signal | 11 |
20080297204 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N | 12-04-2008 |
20090309632 | HIGH-SIDE SWITCH ARRANGEMENT - High-side switch arrangement having a switching transistor, the collector of which is connected to a battery connection of the high-side switch arrangement and the emitter of which is connected to an output connection of the high-side switch arrangement, an actuating transistor, the emitter of which is connected to the battery connection of the high-side switch arrangement and the collector of which is connected to the base of the switching transistor, and a diagnosis transistor, the emitter of which is connected to the battery connection of the high-side switch arrangement and the collector of which is connected to the output connection of the high-side switch arrangement, wherein the diagnosis transistor has a saturation collector for sensing the saturation current of the diagnosis transistor. | 12-17-2009 |
20110095790 | Fast settling, bit slicing comparator circuit - An improved fast settling bit slicing comparator circuit includes a comparator having a non-inverting and inverting input; the non-inverting input receiving an input signal; a filter circuit for receiving the input signal and being connected with the inverting input of the comparator; a positive feedback circuit interconnected between the output of the comparator and the non-inverting input of the comparator for introducing a predetermined hysteresis offset; the filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of the hysteresis offset. Additionally, the positive feedback circuit may be interconnected with the inverting input of the comparator through the filter circuit for gradually reducing the effect of the hysteresis offset by reducing the differential voltage between the inverting and non-inverting inputs. | 04-28-2011 |
20110115529 | LATCHED COMPARATOR CIRCUIT - A latched comparator circuit ( | 05-19-2011 |
20110133785 | APPARATUS AND METHOD FOR TIMING ERROR DETECTION DECISION LOCK - A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values. | 06-09-2011 |
20120001657 | APPARATUS AND METHOD FOR IMPROVED EDGE TRIGGERING IN A TEST AND MEASUREMENT INSTRUMENT - A digital storage oscilloscope employs an improved edge triggering circuit that discards some of trigger events when it determines that there are many more trigger events than the oscilloscope can use. The determination is made in response to detection of a characteristic of the signal that indicates a repetitive nature of a complex signal. Certain trigger events are selected to be acted upon, and others are discarded, in response to the determination. The circuitry dynamically reacts to changes in the input signal in response to detection of different criteria for a characteristic of repetition as the input signal changes. | 01-05-2012 |
20120056645 | Analog to Digital Acquisition Eliminating Uncertainty of Level Test in High Noise Environments - A method of determining the quality of a sensed signal has capturing, comparing, categorizing, and a decision-making steps. The capturing step is used to capture a plurality of signals. A magnitude of each of the plurality of signals is compared to a predetermined value to determine a relationship between each of the plurality of signals to the predetermined value. A result of each comparison is categorized according to one of a plurality of predetermined criteria. The categorizing step is repeated at least until a predetermined number of results has been reached in at least one of the plurality of predetermined criteria. A decision is made based on which of the plurality of predetermined criteria reaches the predetermined number. | 03-08-2012 |
20130027090 | MULTI-BAND PEAK POWER REDUCTION - Peak power reduction in transmit chains of multi-band radiocommunication devices is performed. By using knowledge of the phase transformations which occur at the upconverter to determine how baseband signal samples will combine at the higher (upconverted) frequency, peak prediction and corresponding baseband signal modification can be performed in a way that reduces peak power of the combined signal. | 01-31-2013 |
20130099827 | MEASURING DEVICE HAVING A TRIGGER UNIT - A measuring device for triggering a test signal with a superposed noise signal includes a trigger unit, which is connected to a recording unit, where the test signal with respectively superposed noise signal is supplied to both. The trigger unit outputs a trigger signal to the recording unit as soon as the test signal with superposed noise signal has completely run through a hysteresis range. The trigger unit is connected to a hysteresis adjustment unit, where the hysteresis adjustment unit specifies a hysteresis range to the trigger unit, and where the hysteresis range specified by the hysteresis adjustment unit is adjustable. | 04-25-2013 |
20130154689 | IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals. | 06-20-2013 |
20140097873 | POWER-ON-RESET (POR) CIRCUIT WITH ZERO STEADY-STATE CURRENT CONSUMPTION AND STABLE PULL-UP VOLTAGE - The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications. | 04-10-2014 |