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Comparison between plural varying inputs

Subclass of:

327 - Miscellaneous active electrical nonlinear devices, circuits, and systems

327001000 - SPECIFIC SIGNAL DISCRIMINATING (E.G., COMPARING, SELECTING, ETC.) WITHOUT SUBSEQUENT CONTROL

327050000 - By amplitude

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
327063000 Comparison between plural varying inputs 89
20130027087DETECTOR CIRCUIT AND METHOD - In accordance with an embodiment, a controller includes a comparator, a delay element, and a timer. The delay element is connected to an input terminal of the comparator and the timer is connected to an output terminal of the comparator. The delay element may include a switch having a control electrode coupled for receiving a control signal. In accordance with another embodiment, a detection signal is generated in response to a comparison signal transitioning to a first level.01-31-2013
20120176161System and Method for Preventing Bipolar Parasitic Activation in a Semiconductor Circuit - In an embodiment, a semiconductor device has a semiconductor body of a first semiconductor type, a first region of a second semiconductor type disposed in the semiconductor body, and a second region of the first semiconductor type disposed within the first region, where the second semiconductor type is opposite the first semiconductor type, and where an interface between the first region and the semiconductor body forms a first diode junction. The semiconductor device also has a comparator with a first input coupled to the semiconductor body and a second input coupled to the first region, and a switch having a first output node coupled to the first region, and a second output node coupled to the semiconductor body. The semiconductor body, the first region and the second region are configured to be coupled to a first supply voltage, a second supply voltage, and a third supply voltage, respectively.07-12-2012
20090267651SWITCH STATE DETECTOR AND ENCODER - A switch state detector for use in a system wherein a plurality of n switches (S10-29-2009
20120223743Time Base Generator and Method for Providing a First Clock Signal and a Second Clock Signal - A time base generator and method for providing a first clock signal and a second clock signal comprising generating the first clock signal at a first clock frequency, dividing the first clock frequency by a first integer to produce a first auxiliary signal, dividing the second clock signal by a second integer to produce a second auxiliary signal, generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, and generating the second clock signal by a voltage-controlled oscillator controlled by the error signal such that two clock signals of slightly different frequencies with defined time or phase delay are provided.09-06-2012
20110298497COMPARATOR CIRCUIT - A comparator circuit can achieve a reduction in current consumption with a simple configuration, and can suppress an increase in current consumption accompanying a rise in power source voltage. A current mirror circuit is connected to a power source, and gates of MOSFETs of the circuit are interconnected. An input signal is applied to a gate of an NMOSFET of the circuit. By determining the value of the signal with a constant voltage device, the voltage across a tail resistor is constant, even in the event that the power source voltage and the input signal change.12-08-2011
20090243662MOS INTEGRATED CIRCUIT AND ELECTRONIC EQUIPMENT INCLUDING THE SAME - A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit.10-01-2009
20110227608Voltage Comparators - A voltage comparator, comprises: a first branch comprising a first transistor, a first resistor (R09-22-2011
20100188121LEAKAGE CURRENT DETECTION CIRCUIT AND LEAKAGE CURRENT COMPARISON CIRCUIT - A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.07-29-2010
20110109347SELF-POWERED COMPARATOR - Embodiments of the invention relate to an input-powered comparator. Embodiments of the invention also pertain to an active diode that includes an input-powered comparator and a switch. In a specific embodiment, the input-powered comparator only consumes power when an input source provides sufficiently high voltage. Embodiments of the active diode can be used in an energy harvesting system. The comparator can be powered by the input and the system can be configured such that the comparator only consumes power when the input is ready to provide power to the load or energy storage element. In a specific embodiment, when there is no input, or the input is too low for harvesting, the comparator does not draw any power from the energy storage element (e.g., battery or capacitor) of the system.05-12-2011
20110102021Differential Hysteresis Comparator Circuits and Methods - A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.05-05-2011
20090115460VOLTAGE LEVEL CLAMPING CIRCUIT AND COMPARATOR MODULE - A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.05-07-2009
20100123483Circuit and Method for a Digital Process Monitor - A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.05-20-2010
20110043255TEMPERATURE RESPONSIVE BACK BIAS CONTROL FOR INTEGRATED CIRCUIT - The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.02-24-2011
20110037499COMPARATOR FOR TECHNOLOGIES WITH TRANSIENT VARIATIONS OF TRANSISTOR PARAMETERS - This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.02-17-2011
20080315922COMPENSATED COMPARATOR FOR USE IN LOWER VOLTAGE, HIGHER SPEED NON-VOLATILE MEMORY - Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.12-25-2008
20090153195COMPARATOR MODULE - A comparator module applied to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) is provided. The IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module and a comparator module. The comparator module has an output terminal, a first input terminal coupled to a first voltage source, and a second input terminal coupled to a second voltage source. The comparator module includes a current source module, a first voltage level adjusting circuit module, a second voltage level adjusting circuit module, and a comparing circuit module.06-18-2009
20080204083Voltage Comparator - Output currents from differentially connected transistors (t08-28-2008
20110148468THRESHOLD COMPARATOR WITH HYSTERESIS AND METHOD FOR PERFORMING THRESHOLD COMPARISON WITH HYSTERESIS - A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.06-23-2011
20090021283HIGH SPEED LATCHED COMPARATOR - An improved latched comparator, including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor. The latch and track select circuit includes a further transistor having an source connected to a current sink connected to ground, having a gate connected to receive a track signal and having a drain connected to the common connection node of the first and second transistors, and a still further transistor having a source connected to the current sink connected to ground, having a gate connected to receive a latch signal and having a drain connected to the common connection node of the third and fourth transistors. Bipolar embodiments are also included.01-22-2009
20120013364SYSTEM FOR ON-CHIP TEMPERATURE MEASUREMENT IN INTEGRATED CIRCUITS - A thermal sensor providing simultaneous measurement of two diodes. A first diode and a second diode are coupled to a first current source and a second current source, respectively. The ratio of the currents provided by the two sources is accurately know The voltage across each of the two diodes may be coupled to the input of a differential amplifier for determination of temperature. Alternatively, the first diode may be coupled to a first current source by a resistor with a known voltage drop, the second diode may be coupled to an adjustable second current source. The current in the second diode is equal to the sum of voltage drop across the first diode and the known voltage drop across the resistor. Under the established conditions, the Diode Equation may be used to calculate a temperature.01-19-2012
20120153991COMPARATOR WITH OFFSET COMPENSATION AND IMPROVED DYNAMIC RANGE - A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.06-21-2012
20110089976MOS INTEGRATED CIRCUIT AND ELECTRONIC EQUIPMENT INCLUDING THE SAME - A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit.04-21-2011
20100207663SEMICONDUCTOR DEVICE FOR RECEIVING EXTERNAL SIGNAL HAVING RECEIVING CIRCUIT USING INTERNAL REFERENCE VOLTAGE - A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.08-19-2010
20120326752DESIGN METHOD AND STRUCTURE FOR A TRANSISTOR HAVING A RELATIVELY LARGE THRESHOLD VOLTAGE VARIATION RANGE AND FOR A RANDOM NUMBER GENERATOR INCORPORATING MULTIPLE ESSENTIALLY IDENTICAL TRANSISTORS HAVING SUCH A LARGE THRESHOLD VOLTAGE VARIATION RANGE - Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.12-27-2012
20100225358METHOD AND DEVICE FOR COMPARATOR OFFSET CANCELLATION - A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.09-09-2010
20100289530ELECTRONIC APPARATUS AND CABLE DEVICE - [Object] To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected.11-18-2010
20120133396COMPARATOR - A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.05-31-2012
327064000 With logic or bistable circuit 9
20090167362COMPARATOR - A comparator is provided. In a first period, input terminal of the pre-amplifier is coupled to a first voltage. A first terminal of the first capacitor is coupled to the second input terminal of the pre-amplifier. A second terminal of the first capacitor is coupled to the first input voltage in the first period, and is coupled to the second input voltage in the second period. The second capacitor is coupled between the output terminal of the pre-amplifier and an input terminal of the gain unit. The switch is coupled between the input terminal and an output terminal of the gain unit. An input terminal of the latch is coupled to the output terminal of the gain unit. The latch outputs a comparison result.07-02-2009
20110215838DIGITAL NOISE FILTER - A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.09-08-2011
20100007385SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.01-14-2010
20090039921VOLTAGE DETECTING CIRCUIT AND BATTERY DEVICE USING SAME - A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit. The voltage detecting circuit and battery device using the circuit, when assembled in battery using equipment, uses a battery up to its usage limit.02-12-2009
20090134914LOW OFFSET COMPARATOR AND OFFSET CANCELLATION METHOD THEREOF - A low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage.05-28-2009
20110068829COMPARATOR CIRCUIT AND DISPLAY DEVICE PROVIDED WITH THE SAME - An inverter is configured by double gate TFTs, and an inverter is configured by double gate TFTs. Top gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(+), and bottom gate terminals are connected to an output of the inverter and an output terminal OUT. Bottom gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(−), and bottom gate terminals are connected to an output of the inverter. With this, threshold voltages of the inverters are controlled so as to facilitate switching operations of the inverters, and whereby the comparator circuit operates at a high speed. It is possible to obtain a comparator circuit that is insusceptible to a variation in the threshold voltages of the transistors and fluctuation of a common mode voltage of an input signal and capable of operating at a high speed.03-24-2011
20090153196VOLTAGE COMPARATOR HAVING IMPROVED KICKBACK AND JITTER CHARACTERISTICS - A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.06-18-2009
20080197886CIRCUIT FOR DISCRIMINATING OUTPUT OF SQUELCH CIRCUIT AND CIRCUIT FOR REGULATING SENSIVITY OF THE SAME - A circuit for discriminating a ‘Noisy’ state of an output of a squelch circuit is disclosed. A circuit for resolve the ‘Noisy’ state of the output of the squelch circuit is also disclosed which uses the output identification circuit. The output of the squelch circuit and a clear signal are input into a first AND gate. The output of the first AND gate is input into a first flip-flop. An inversed signal of the output of the first AND gate is input into a second flip-flop. The outputs of the first and second flip-flops are input into a discriminating unit including a second AND gate. The ‘Noisy’ state is identified by the output of the second AND gate. Based on the identification result, sensitivity of the squelch circuit is regulated.08-21-2008
20120274358IDENTICAL-DATA DETERMINATION CIRCUIT - A identical-data determination circuit includes a first activation unit configured to activate an output signal when first and second signals each have a first level, a second activation unit configured to activate the output signal when the first and second signals each have a second level different from the first level, an initialization unit configured to deactivate the output signal when an initialization signal is applied, and a storage unit configured to store the output signal.11-01-2012
327065000 Differential input 46
20130088262LOW VOLTAGE COMPARATOR CIRCUITS - Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.04-11-2013
20090091354Semiconductor circuit - In a conventional circuit to buffer differential clock signals at plural stages, the deteriorations of duty ratios caused by the variations of transistors constituting the circuit have not been compensated. Further, when it is attempted to increase the effect of compensating the duty ratios, the size of the circuit increases and the consumed electric current also increases accordingly. A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; differential signal output terminals to output output differential signals in accordance with the voltages input into the differential input section; a low-pass filter to extract the DC components of signals output from the differential signal output terminals; and a load resistor section connected to the differential input section, wherein resistance values are determined on the basis of the DC components of the signals extracted with the low-pass filter.04-09-2009
20120112794DIFFERENTIAL DRIVER WITH CALIBRATION CIRCUIT AND RELATED CALIBRATION METHOD - A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage.05-10-2012
20120098572LATCHED COMPARATOR HAVING ISOLATION INDUCTORS - Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).04-26-2012
20090033372SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.02-05-2009
20080238491Interface circuit - An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.10-02-2008
20100141302SIGNAL CONVERTING CIRCUIT - A signal conversion circuit 06-10-2010
20120062279Adaptively Biased Comparator - The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node.03-15-2012
20090128193FAST, LOW OFFSET GROUND SENSING COMPARATOR - A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion. The single-ended output of the second stage may serve as the input into a latch, which may be a bistable set-reset (SR) latch configured to increase the gain and response time while protecting against multiple switching, with the single-ended output of the latch configured as the output of the comparator.05-21-2009
20110140742TRANSMISSION DEVICE HAVING EMPHASIS FUNCTION - A transmission driver including a main driving stage and a sub-driving stage is provided. The main driving stage has a main current source, and is adapted for receiving a first differential input data stream and outputting a differential output data stream by using the main current source. The sub-driving stage has two sub-current sources, and is adapted for receiving a second differential input data stream and counteracting/reducing the attenuation or distortion of the differential output data stream caused by a long transmission distance by using the sub-current sources. There is a delay of a specific bit length between the first and the second differential input data streams.06-16-2011
20110221477HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD - A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.09-15-2011
20090021284Low voltage differential signal receiver - The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.01-22-2009
20100182051INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.07-22-2010
20110057686HYSTERESIS COMPARATOR CIRCUIT AND SEMICONDUCTOR DEVICE INCORPORATING SAME - A hysteresis comparator circuit that compares first and second input signals to output a hysteresis output signal includes a constant current source, a first comparator, a second comparator, and an output circuit. The constant current source includes a load resistor to generate a given constant current. The first comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a first comparison result. The second comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a second comparison result. The output circuit has a pair of inputs thereof connected to the first and second comparators, respectively, which inverts an output thereof in response to each of the first and second comparison results to generate the hysteresis output signal.03-10-2011
20110001516CIRCUIT, APPARATUS, AND METHOD FOR SIGNAL TRANSFER - A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit.01-06-2011
20110025379LATCHED COMPARATOR AND METHODS THEREFOR - A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.02-03-2011
20110109348DYNAMIC COMPARATOR WITH BACKGROUND OFFSET CALIBRATION - A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.05-12-2011
20090033371AMPLIFIER CIRCUIT FOR DOUBLE SAMPLED ARCHITECTURES - A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.02-05-2009
20080218218POTENTIAL COMPARATOR AND TEST APPARATUS - The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object 09-11-2008
20090033370COMPARATOR WITH LOW SUPPLIES CURRENT SPIKE AND INPUT OFFSET CANCELLATION - A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.02-05-2009
20120119790DYNAMIC COMPARATOR BASED COMPARISON SYSTEM - A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.05-17-2012
20110089977Systems and Methods of Low Offset Switched Capacitor Comparators - The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.04-21-2011
20100289531COMPARATOR WITH HYSTERESIS - Techniques for providing a comparator incorporating amplitude hysteresis. In an exemplary embodiment, a current offset stage is coupled to a comparator having a folded cascode architecture. The current offset stage offsets the current generated from an input stage to delay switching of the comparator output to implement amplitude hysteresis. In an exemplary embodiment, rail-to-rail input voltages may be accommodated by providing dual NMOS and PMOS input stages. In another exemplary embodiment, the amplitude hysteresis may be controlled by an adjustable threshold voltage. In yet another exemplary embodiment, a constant transconductance g11-18-2010
20110181321SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.07-28-2011
20090058471Rail-to-rail comparator with hysteresis - A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be proportional to a bias current of the current stage.03-05-2009
20100327914Accurate Hysteretic Comparator and Method - A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window V12-30-2010
20100237906RECEIVING CIRCUIT - A receiving circuit includes an impedance compensating circuit, a first input terminal and a second input terminal coupled to a first signal line and a second signal line, a first signal and a second signal corresponding to differential signals being transmitted at the first input terminal and the second input terminal, respectively, a signal input circuit, coupled to the first input terminal and the second input terminal, which receives the first signal and the second signal are input, and a differential-signal detector that detects whether or not the differential signals are supplied to the first input terminal and the second input terminal.09-23-2010
20120280719Apparatus and Method for Selectively Enabling and Disabling a Squelch Circuit Across AHCI and SATA Power States - An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.11-08-2012
20100213983AMPLIFIERS WITH INPUT OFFSET TRIM AND METHODS - Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.08-26-2010
20130099825VOLTAGE COMPARATOR - The present disclosure provides a voltage comparator including a current source, a differential gain module and a switch module, wherein the magnitude of the current flowing through the current source is nano ampere level; the differential gain module includes a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor and the second transistor are respectively connected to the current source, the third transistor and the fourth transistor form a mirror current structure, the third transistor is connected to the first transistor, and the fourth transistor is connected to the second transistor via a ninth transistor used for forming asymmetric differential gain.04-25-2013
20130099824REDUCED OFFSET COMPARATOR - An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.04-25-2013
20120274359HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD - A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.11-01-2012
20130241599COMPARATOR CIRCUIT HAVING A CALIBRATION CIRCUIT - A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal.09-19-2013
20110316587Bistable CML Circuit - A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.12-29-2011
20120299623RADIO FREQUENCY (RF) POWER DETECTOR SUITABLE FOR USE IN AUTOMATIC GAIN CONTROL (AGC) - In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.11-29-2012
327066000 Current mirror 7
20080265947Current mirror circuit and constant current having the same - A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.10-30-2008
20100001766SYSTEM TO EVALUATE A VOLTAGE IN A CHARGE PUMP AND ASSOCIATED METHODS - A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.01-07-2010
20110001517SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes an input terminal, a power line, a pnp-bipolar transistor connected to the power line, a first resistor connecting an emitter of the transistor to the input terminal, a second resistor connecting a collector of the transistor to ground, an operation circuit operable when the input voltage is a predetermined voltage or higher, the predetermined voltage being set within a first voltage region in which the input voltage cannot turn on the transistor, a comparator comparing an internal voltage with a reference voltage, the internal voltage being changed from a voltage value in a non-conductive state in which the transistor is not turned on, and an output terminal configured to output an output voltage which changes in response to a result of comparing the internal voltage with the reference voltage.01-06-2011
20090027086Comparator and method with controllable threshold and hysteresis - A comparator (01-29-2009
20110095788High-speed comparator with asymmetric frequency response - A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.04-28-2011
20120126855REDUCED TEMPERATURE DEPENDENT HYSTERETIC COMPARATOR - This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents.05-24-2012
20100052735SLEW RATE CONTROLLED LEVEL SHIFTER WITH REDUCED QUIESCENT CURRENT - A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror transistor in the other current path, thereby preventing quiescent current during stable periods. An optional cascode transistor is added to facilitate fabrication using low threshold voltage transistors.03-04-2010
327067000 Having feedback 4
20090243663ANALOG COMPARATOR COMPRISING A DIGITAL OFFSET COMPENSATION - A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.10-01-2009
20090108882LOW POWER LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) OUTPUT DRIVERS - A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors.04-30-2009
20130120025COMPARATOR AND AD CONVERTER PROVIDED THEREWITH - Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.05-16-2013
20120274360SWITCHED CAPACITANCE VOLTAGE DIFFERENTIAL SENSING CIRCUIT WITH NEAR INFINITE INPUT IMPEDANCE - A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes.11-01-2012
327068000 Input provides varying reference signal 4
20090051391ADJUSTABLE INPUT RECEIVER FOR LOW POWER HIGH SPEED INTERFACE - A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.02-26-2009
20080204084LOW HEAT DISSIPATION I/O MODULE USING DIRECT DRIVE BUCK CONVERTER - A current-loop output circuit for an industrial controller provides for low power dissipation and reduced part count by driving current loads of different resistances directly from a switched voltage source. Proper filtering and design of a feedback loop allows the necessary transient response times to be obtained.08-28-2008
20090085610GENERAL PURPOSE COMPARATOR WITH MULTIPLEXER INPUTS - A circuitry comprises a comparator for comparing a signal received on a first input to a signal received on a second input. A control register associated with the first multiplexer stores control values enabling connection of one input of the first multiplexer to the output of the first multiplexer.04-02-2009
20110068830MINIMUM LEADING EDGE BLANKING SIGNAL GENERATOR AND METHOD FOR GENERATING MINIMUM LEADING EDGE BLANKING SIGNAL - A minimum leading edge blanking (MLEB) signal generator is provided. The MLEB signal generator includes a buck unit and a signal generation unit. The buck unit receives an error amplification signal, and generates a reference blanking signal. The reference blanking signal has a voltage lower than a voltage of the error amplification signal. The signal generation unit receives the reference blanking signal, and generates the MLEB signal according to the current sensing signal. When the current sensing signal is equal to the reference blanking signal, the MLEB signal changes its voltage level. As such, the width of the MLEB signal is a time width of the high level or low level of the MLEB signal before the voltage level of the MLEB signal changes. The MLEB is provided to an external unit, such that the external unit can be prevented from misoperation, thus improving the electric performance in its entirety.03-24-2011
327069000 With plural paths 2
327070000 With single output 2
20130207691METHOD FOR PERFORMING A TRI-STATE COMPARISON OF TWO INPUT SIGNALS IN A WINDOW COMPARATOR CIRCUIT, AND WINDOW COMPARATOR CIRCUIT FOR IMPLEMENTING THE METHOD - A method performs a comparison of input signals in a window comparator circuit. In a first phase, input, ground and offset voltages are stored on capacitors. A comparison is performed between a first adapted input voltage and a second adapted input voltage added to an adapted offset voltage, to provide a first output signal. In a second phase, the voltages are stored on the capacitors in a different manner. A comparison is performed between the first adapted input voltage added to the adapted offset voltage and the second adapted input voltage, to provide a second output signal. Finally, a control of the state of the output signals is performed to determine if the comparison is in a low or high state if the output signals have a same low or high output level, or in an intermediate state if the output signals have a different output level.08-15-2013
20120086474Field Device for Process Automation - A field device comprising a signal processing unit that generates a digital measurement, control or regulation signal, and comprises an output stage that converts the digital measurement, control or regulation signal into an analog voltage or current signal, The field device also includes a monitoring device which comprises a measuring device that detects the analog voltage or current signal and converts this signal into a digital voltage or current measurement signal, a first digital low-pass filter for filtering the digital measurement, control or regulation signal, a second digital low-pass filter having the same cut-off frequency as that of the first digital low-pass filter, a comparator downstream of the low-pass filters, and an evaluation device that generates an error message when the deviation between the compared signals exceeds a pre-determined level.04-12-2012
327071000 Three or more inputs 1
20090201050FAULT DETECTION AND ISOLATION OF REDUNDANT SIGNALS - A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.08-13-2009

Patent applications in class Comparison between plural varying inputs

Patent applications in all subclasses Comparison between plural varying inputs