Class / Patent application number | Description | Number of patent applications / Date published |
327051000 | With sensing amplifier | 65 |
20090096487 | SENSE AMPLIFIER CONTROL CIRCUIT - The present invention discloses a sense amplifier control circuit which controls the sense amplifier. A sense amplifier control circuit comprises a voltage comparing unit outputting delay control signals having a value corresponding to each of divided voltages obtained by dividing a potential of a power supply voltage and a pull-up control signal generating unit outputting an overdrive control signal and a pull-up control signal by an active signal and changing an enable pulse width of the overdrive control signal in response to the delay control signals, whereby it is possible to reduce current consumption caused by unnecessary overdrive operation and prevent a potential drop of the power supply voltage and thus provide operational stability of the semiconductor memory device by providing the overdrive control signal of which the enable pulse width is controlled in response to the potential of the power supply voltage. | 04-16-2009 |
20090160490 | REFERENCE VOLTAGE GENERATOR OF ANALOG-TO-DIGITAL CONVERTER - A reference voltage generator, which is used in an analog-to-digital converter, minimizes influence of kickback noise by dividing a full scale reference voltage into a number of reference voltages using a ladder resistor unit, and applying the number of reference voltages to a number of comparators, and matches a reference common mode voltage to an input common mode voltage by forming a common feedback loop using another ladder resistor unit which is a replica of the ladder resistor unit. Therefore, since kickback noise is locally discharged by a decoupling capacitor connected to each ladder resistor and a peak value of the kickback noise is also reduced, it is possible to optimize the ladder resistor unit according to power consumption. Also, since the common feedback loop is formed as a replica of the ladder resistor unit, it is possible to match a reference common mode signal to an input common mode signal. | 06-25-2009 |
20100219863 | Method and Apparatus for Gamma Ray Detection - A high sensitivity, three-dimensional gamma ray detection and imaging system is provided. The system uses the Compton double scatter technique with recoil electron tracking The system preferably includes two detector subassemblies; a silicon microstrip hodoscope and a calorimeter. In this system the incoming photon Compton scatters in the hodoscope. The second scatter layer is the calorimeter where the scattered gamma ray is totally absorbed. The recoil electron in the hodoscope is tracked through several detector planes until it stops. The x and y position signals from the first two planes of the electron track determine the direction of the recoil electron while the energy loss from all planes determines the energy of the recoil electron. | 09-02-2010 |
20110032002 | DEVICES AND METHODS FOR A THRESHOLD VOLTAGE DIFFERENCE COMPENSATED SENSE AMPLIFIER - Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes. | 02-10-2011 |
20110227607 | Sensor Circuit - The present invention provides a sensor circuit. The sensor circuit comprises a first amplifier which receives a measurement signal via an input end thereof, amplifies the received signal, and outputs the amplified signal via a first output end thereof; a first current source which supplies current (Ir) flowing toward the input resistance (Ri) of the first amplifier; a second current source which supplies current (Ic) flowing toward the input capacitance (Ci) of the first amplifier; and a bias current source which reduces the direct current offset voltage in the output of the first amplifier. | 09-22-2011 |
20130141139 | CAPACITIVE SENSOR INTERFACE AND METHOD - Electronic interface and method for reading a capacitive sensor that includes one input capacitor ( | 06-06-2013 |
20130147520 | COMPARATOR WITH IMPROVED TIME CONSTANT - An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier. | 06-13-2013 |
327052000 | Differential amplifier | 50 |
20090102515 | Sense-amplifying circuit having two amplification stages - A sense-amplifying circuit amplifies a voltage difference between a first signal source and a second signal source. A first inverter has a first intermediate node from which a first output extends. A second inverter has a second intermediate node from which a second output extends. The second inverter is recursively cross-coupled with the first inverter. A first power source switch connects the first and second inverters to a first power source line. A second power source switch connects the first and the second inverters to a second power source line. A first sense-amplifying switch connects the first signal source to the first intermediate node. A second sense-amplifying switch connects the second signal source to the second intermediate node. A first pre-charge switch connects the first intermediate node to the second power source line. A second pre-charge switch connects the second intermediate node to the second power source line. | 04-23-2009 |
20090108880 | Systems, Circuits and Methods for Extended Range Input Comparison - Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide comparator circuits that include two input stages that each receive a first input and a second input. One of the input stages is sensitive to a difference between the first input and the second input for at least a low common mode, and provides a first output. The other of the input stages is sensitive to a difference between the positive input and the negative input for at least a high common mode, and provides a second output. The comparator circuits further include a regeneration stage that receives the first output and the second output, and provides a comparator output reflecting the difference between the first input and the second input. | 04-30-2009 |
20090128192 | DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal. | 05-21-2009 |
20090212825 | HIGH SPEED COMPARATOR - A comparator comprises a differential amplifier (T | 08-27-2009 |
20090261861 | Current Detection Circuit - There is provided a current detection circuit capable of preventing an excessive voltage from being applied to an input terminal of a differential amplifier, without resulting in reduction in current detection accuracy. The current detection circuit includes a power MOSFET | 10-22-2009 |
20090284284 | Sense Amplifier and Electronic Apparatus Using the Same - A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected. | 11-19-2009 |
20100001765 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 01-07-2010 |
20100019804 | ARRAY SENSE AMPLIFIERS, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION - A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (āI/Oā) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node. | 01-28-2010 |
20100090725 | SENSE-AMPLIFIER CONTROL CIRCUIT AND CONTROLLING METHOD OF SENSE AMPLIFIER - A sense amplifier control circuit includes an initial-voltage setting circuit configured to set a control signal to an initial voltage, the control signal controlling a sensing operation of a sense amplifier, and a control-signal-level adjusting circuit configured to first change a voltage level of the control signal from the initial voltage to a voltage level at which the sense amplifier can execute a current sensing, and is configured to second change, after a predetermined time elapses, the voltage level at which the sense amplifier can execute the current sensing to a voltage level at which the sense amplifier can execute a voltage sensing. | 04-15-2010 |
20100182050 | GENERATING A TRIGGER FROM A DIFFERENTIAL SIGNAL - A trigger circuit generates a trigger signal when a differential input signal crosses a differential threshold voltage level. A first side of the differential input signal is applied to a first terminal of a first load termination resistor. A second side of the differential signal is applied to a first terminal of a second load termination resistor. A first side of the differential threshold voltage level is applied to a second terminal of the first load termination resistor. A second side of the differential threshold voltage level is applied to a second terminal of the second load termination resistor. A comparator generates the trigger signal when a voltage level at the first terminal of the first resistor exceeds a voltage level at the first terminal of the second resistor. | 07-22-2010 |
20110012643 | APPARATUS AND METHOD FOR TESTING SENSE AMPLIFIER THRESHOLDS ON AN INTEGRATED CIRCUIT - An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage. | 01-20-2011 |
20110043254 | Sense Amplifier and Electronic Apparatus Using the Same - A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected. | 02-24-2011 |
20110050284 | SENSE AMPLIFIER CIRCUIT AND RELATED CONFIGURATION AND OPERATION METHODS - A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET. | 03-03-2011 |
20110204923 | HIGH-SPEED COMPARATOR - Methods, systems, and devices are described for providing voltage comparison adapted to operate at high-speeds and over a relatively large range of supply voltages. | 08-25-2011 |
20110298496 | SRAM SENSE AMPLIIFER - A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage. | 12-08-2011 |
20110304358 | TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS AND METHODS FOR PRECHARGING SENSE AMPLIFIERS - Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored. | 12-15-2011 |
20120169378 | DIFFERENTIAL DATA SENSING - A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line. | 07-05-2012 |
20130021065 | POWER-UP SIGNAL GENERATING CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node. | 01-24-2013 |
20130069693 | SENSE AMPLIFIER AND ELECTRONIC APPARATUS USING THE SAME - A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected. | 03-21-2013 |
20140097871 | Latch comparator device and operation method thereof - A latch comparator device includes a differential input amplifier coupled between a first system voltage and a second system voltage and including a first differential output signal terminal and a second differential output signal terminal, a latch coupled to a third system voltage including a first latch signal terminal and a second latch signal terminal, a switch module including a first switch device and a second switch device, wherein the first switch device is coupled between the first differential output signal terminal and the second latch signal terminal and the second switch device is coupled between the second differential output signal terminal and the first latch signal terminal, and a third switch device is coupled between the latch and a fourth system voltage. | 04-10-2014 |
20140176192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a differential input unit configured to generate internal differential signals based on external differential signals by using a first level voltage, a signal conversion unit configured to generate an internal synchronization signal based on the internal differential signals in response termination control signals by using a second level voltage, and a duty correction unit configured to correct duty of the internal synchronization signal by using the second level voltage. | 06-26-2014 |
20150015307 | COMPARATOR AND AMPLIFIER - A comparator has a differential pair circuit and a current control circuit. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. An amplifier circuit is also disclosed, having a differential pair circuit, a current control circuit, an amplification circuit and a reset circuit. | 01-15-2015 |
20150311875 | SENSE AMPLIFIER WITH IMPROVED RESOLVING TIME - Sense amplifiers that can provide improved resolving times can be used, for example, in clock and data recovery circuits. The sense amplifiers sense the value of a differential input signal using a latch circuit and then, after an initial sensing time, force the latch circuit to resolve a digital value that corresponds to the value of the input signal. An implementation of the sense amplifies uses a first latch with cross-coupled inverters that produce set and reset signals. A transistor pair couples the differential input signal to the cross-coupled inverters via a switch to ground. A discharge path circuit arranged to accelerate the resolving of the latch circuit is also coupled to the cross-coupled inverters. The discharge path can be enabled after an initial sensing time. | 10-29-2015 |
20160254806 | Comparator Apparatus and Method | 09-01-2016 |
327053000 | Current mirror | 7 |
20080297203 | CURRENT MIRROR CIRCUIT - A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area. | 12-04-2008 |
20090302895 | CONSTANT OUTPUT COMMON MODE VOLTAGE OF A PRE-AMPLIFIER CIRCUIT - A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first circuit, a comparator circuit coupled with an output of the first circuit, a pre-amplifier circuit of the comparator circuit, a tracking circuit coupled with a common output location of the pre-amplifier circuit to provide (e.g., source/sink) an additional current to the common output location of the pre-amplifier circuit using an alternate current path in the tracking circuit when an input common mode of the pre-amplifier circuit is beyond a saturation range, and a second circuit of the comparator circuit coupled with the pre-amplifier circuit. A scaled version of a pair of input transistors of a pre-amplifier circuit of the tracking circuit may be created using a scaling factor (āNā). | 12-10-2009 |
20120235708 | Method and System for High Speed Differential Synchronous Sense Amplifier - A sense amplifier may be operable to form a current-mirror reference using a first PMOS transistor and a NMOS transistor. Currents at a first internal terminal and a second internal terminal may be generated based on the current-mirror reference. Voltage signals at the first internal terminal and the second internal terminal may be generated based on received differential input signals and the currents at the first internal terminal and the second internal terminal. The sense amplifier may limit voltage excursions of the voltage signals at the first internal terminal and/or of the second internal terminal using a pair of cross coupled PMOS transistors, respectively. Voltage signals at a third internal terminal and a fourth internal terminal may be generated based on voltage signals at the first internal terminal and the second internal terminal. An output signal may be generated based on the voltage signal at the fourth internal terminal. | 09-20-2012 |
20130187681 | ANALOG SIGNAL SOFT SWITCHING CONTROL WITH PRECISE CURRENT STEERING GENERATOR - A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers. | 07-25-2013 |
20130249599 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a first transistor controlled by a control signal; a sense voltage generating circuit for sensing current flowing through the first transistor, mirroring current flowing through a reference current circuit, and summing the currents to generate voltage based on the summed currents; a reference voltage circuit for mirroring current flowing through the reference current circuit and generating reference voltage; an amplifier for comparing the voltage generated by the sense voltage generating circuit and the reference voltage; and a second transistor which has a gate connected to an output terminal of the amplifier and which can turn off the first transistor. | 09-26-2013 |
20130257483 | SENSE AMPLIFIER-TYPE LATCH CIRCUITS WITH STATIC BIAS CURRENT FOR ENHANCED OPERATING FREQUENCY - Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair. | 10-03-2013 |
20140300388 | ANALOG SIGNAL SOFT SWITCHING CONTROL WITH PRECISE CURRENT STEERING GENERATOR - A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers. | 10-09-2014 |
327054000 | Having feedback | 9 |
20100066413 | CURRENT SENSING CIRCUIT FOR PWM APPLICATIONS WITH PULSE WIDTH MODULATION AND CORRESPONDING CURRENT PROCESS - A current sensing circuit for a pulse width modulation (PWM) application may include first and second input terminals to be coupled to ends of a sensing resistance, an output terminal, and first and second internal circuit nodes. The current sensing circuit further may include an input block comprising a first transconductance amplifier to be coupled to a supply voltage. The first transconductance amplifier may be coupled to the first and second input terminals and to the first and second internal circuit nodes. The current sensing circuit may also include an amplifier block comprising an amplifier to be coupled to a reference voltage, and coupled to the first and second internal circuit nodes and the output terminal, and a feedback block comprising a second transconductance amplifier to be coupled to the supply voltage and being coupled to the output terminal and the first and second internal circuit nodes. The input block may further include a third transconductance amplifier coupled in cascade to the first transconductance amplifier and to the first and second input terminals. | 03-18-2010 |
20100090726 | DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT - A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received. | 04-15-2010 |
20110001515 | COMPARATOR WITH SELF-LIMITING POSITIVE FEEDBACK - A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function. | 01-06-2011 |
20110133782 | METHOD AND CIRCUIT ARRANGEMENT FOR CONTROLLING SWITCHING TRANSISTORS OF AN INTEGRATED CIRCUIT - A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage. | 06-09-2011 |
20130200924 | COMPARATOR WITH TRANSITION THRESHOLD TRACKING CAPABILITY - A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage. | 08-08-2013 |
20140035623 | COMPARATOR WITH TRANSITION THRESHOLD TRACKING CAPABILITY - A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals. | 02-06-2014 |
327055000 | Cross-coupled | 3 |
20090045849 | DATA BUS SENSE AMPLIFIER CIRCUIT - A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated. | 02-19-2009 |
20120133395 | High speed dynamic comparative latch - A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch. | 05-31-2012 |
20140055166 | REFERENCE VOLTAGE CIRCUITS - A reference voltage circuit corrects for bandgap voltage shifts induced during fabrication. The reference voltage circuit generates a reference voltage using first and second base-emitter pairs. The reference voltage circuit sums the voltage across the first base-emitter pair with a difference voltage. During a first time period, the difference voltage is the voltage across the first base-emitter pair minus the voltage across the second base-emitter pair, and during a second time period, the difference voltage is the voltage across the second base-emitter pair minus the voltage across the first base-emitter pair. | 02-27-2014 |
327056000 | With reference signal | 10 |
20090058469 | METHODS AND SYSTEMS FOR COMPARING CURRENTS USING CURRENT CONVEYOR CIRCUITRY - Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output. | 03-05-2009 |
20090315591 | POWER UP CIRCUIT WITH LOW POWER SLEEP MODE OPERATION - A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode. | 12-24-2009 |
20100308870 | SWITCHED CAPACITOR CIRCUIT AND PIPELINED ANALOG-TO-DIGITAL CONVERSION CIRCUIT WITH THE SWITCHED CAPACITOR CIRCUIT - A conversion circuit for converting a differential input signal into an output signal includes an amplifier that has an input terminal and an output terminal; a first capacitor in which, in a first period, a difference voltage of the differential input signal is applied across first and second terminals, and in a second period the first terminal is coupled to the output terminal of the amplifier and the second terminal is coupled to the input terminal of the amplifier; and a second capacitor in which, in the second period, a reference voltage in accordance with the differential input signal is applied to a first terminal, and the second terminal of the first capacitor is coupled to a second terminal of the second capacitor. | 12-09-2010 |
20110121863 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 05-26-2011 |
20140176193 | LOW POWER SQUELCH DETECTOR CIRCUIT - Described is an apparatus comprising: a reference generator to provide a first reference and a second reference; a first input coupled to the first reference; a second input coupled to the second reference; and a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal. | 06-26-2014 |
20140266308 | CLOCK AMPLITUDE DETECTION - In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level. | 09-18-2014 |
20140312933 | LOW NOISE COMPARATOR FOR HIGH RESOLUTION ADC - A low noise comparator for a high resolution ADC is provided. The comparator includes: an inputter configured to receive a signal and amplify the signal; and an outputter configured to output a result of comparing the signal output from the inputter, wherein an inductor is connected to an input terminal of an input element of at least one of the inputter and the outputter. Accordingly, the comparator can satisfy the gain value and the noise performance at the same time by using the inductor which has no voltage headroom problem. | 10-23-2014 |
20150035564 | POWER SUPPLY MONITOR - An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold. | 02-05-2015 |
20150116003 | DIFFERENTIAL AMPLIFIER AND DUAL MODE COMPARATOR USING THE SAME - A differential amplifier includes an input common mode voltage generation unit suitable for generating an input common mode voltage, an input common mode voltage sampling unit suitable for performing an independent sampling operation on the input common mode voltage, and a differential amplifying unit suitable for performing a differential amplifying operation on an input voltage and the sampled input common mode voltage. | 04-30-2015 |
20160065199 | AMPLITUDE DETECTOR - An amplitude detector includes a first amplitude detection transistor and an output terminal. The first amplitude detection transistor receives a first signal by a gate and a second signal that forms a differential pair with the first signal by a drain, and detects an amplitude of the differential pair. The output terminal outputs an amplitude signal in accordance with amplitude detected by the first amplitude detection transistor. | 03-03-2016 |
327057000 | With latching type element (e.g., flip-flop, etc.) | 8 |
20090108881 | Latch-Based Sense Amplifier - Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock. | 04-30-2009 |
20100156469 | HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR - A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC). | 06-24-2010 |
20110140741 | INTEGRATING RECEIVER WITH PRECHARGE CIRCUITRY - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-16-2011 |
20110187414 | PBTI TOLERANT CIRCUIT DESIGN - In an embodiment related to a sense amplifier, the sense amplifier includes a cross latch includes a pair of nodes, a first pair of transistors, a second pair of transistors, a third node, and a circuit. The pair of nodes includes a first node and a second node configured to store data for the sense amplifier. The second pair of transistors includes a first NMOS transistor and a second NMOS transistor. A first gate of the first NMOS transistor is coupled to the first node, and a second gate of the second NMOS transistor is coupled to the second node. The third node is coupled to a first source of the first NMOS transistor and a second source of the second NMOS transistor. When appropriate, the circuit is configured to provide a voltage level to the third node. | 08-04-2011 |
20120119788 | On-chip Power Supply Monitoring Using a Network of Modulators - An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits. | 05-17-2012 |
20120194222 | MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR - An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal. | 08-02-2012 |
20140152345 | SENSE-AMPLIFIER LATCH HAVING SINGLE DATA INPUT - A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low. | 06-05-2014 |
20150061730 | LATCH AND OPERATION METHOD THEREOF AND COMPARATOR - A latch, an operation method of the latch, and a comparator using the latch are disclosed. The latch includes first and second cross-coupled pairs and first and second transistor pairs. First terminals of the first and second current paths of the first cross-coupled pair are respectively coupled to first terminals of the first and second transistors of the first transistor pair. First terminals of the third and fourth current paths of the second cross-coupled pair are respectively coupled to first terminals of the third and fourth transistors of the second transistor pair. Control terminals of the third and fourth transistors are respectively coupled to the first and second current paths. Control terminals of the first and second transistors are respectively coupled to the third and fourth current paths. | 03-05-2015 |