Entries |
Document | Title | Date |
20080290905 | Peak or Zero Current Comparator - The present invention relates to a simple and small-sized circuit configuration ( | 11-27-2008 |
20080309378 | SEMICONDUCTOR DEVICE - A semiconductor device | 12-18-2008 |
20090174437 | Semiconductor Device and Method for Controlling Thereof - A semiconductor device includes a circuit section having an output impedance which changes in accordance with a switching signal for switching between drive capabilities, and transforming an input signal into an output signal in accordance with the output impedance, a reference voltage generating section generating a reference voltage in accordance with the switching signal and the input signal, and a comparing section comparing a voltage of the output signal to the reference voltage. | 07-09-2009 |
20090237117 | ELECTRICAL PHYSICAL LAYER ACTIVITY DETECTOR - A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node. | 09-24-2009 |
20090267650 | PASSIVE OFFSET AND OVERSHOOT CANCELLATION FOR SAMPLED-DATA CIRCUITS - A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase. | 10-29-2009 |
20090278571 | DEVICE AND TECHNIQUE FOR TRANSISTOR WELL BIASING - A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages. | 11-12-2009 |
20100052733 | COMPARATOR CIRCUIT - A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage. | 03-04-2010 |
20100060323 | TEST CIRCUIT AND TEST METHOD - A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit | 03-11-2010 |
20100066412 | Method and Device for Recording Values of a Signal - The present invention relates to a method and an apparatus for reducing the quantity of values of a sampled signal which need to be stored. A value of the signal is stored if the value is outside, or at the edge of a, predefined value range whose size is determined by an upper limiting value and a lower limiting value. According to the invention, the size of the value range is changed, in particular is continuously reduced to zero, staring from a predefined starting size of the value range, which the values are being recorded. | 03-18-2010 |
20100073032 | VOLTAGE COMPARATOR AND ELECTRONIC DEVICE - A differential amplifier circuit, a differentiation circuit and an output amplifier circuit are provided. The differential amplifier circuit differentially amplifies differentially inputted signals and provides an output. The differentiation circuit differentiates the output of the differential amplifier circuit, and adds the differentiated output to a bias voltage of a constant current transistor of the output amplifier circuit. A voltage comparator capable of higher speed operation without increasing its current consumption is provided. | 03-25-2010 |
20100090724 | System And Method For Removing Nonlinearities And Cancelling Offset Errors In Comparator Based/Zero Crossing Based Switched Capacitor Circuits - A method compensates for errors in an output signal of a comparator based/zero crossing based circuit. The method includes generating with a comparator based/zero crossing based switched capacitor circuit a first output signal with an input signal, generating with the comparator based/zero crossing based switched capacitor circuit a second output signal with the input signal of an opposite polarity, and subtracting the second output signal from the first output signal to generate a final output signal for the comparator based/zero crossing based switched capacitor circuit. | 04-15-2010 |
20100201403 | MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR - There is provided a method that includes comparing a voltage level (Vs | 08-12-2010 |
20100253390 | SEMICONDUCTOR PACKAGE, STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME, AND A METHOD FOR SELECTING ONE SEMICONDUCTOR CHIP IN A STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison. | 10-07-2010 |
20100289529 | POWER-ON DETECTOR AND METHOD THEREOF - A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures. | 11-18-2010 |
20100308869 | Dead-time detecting circuit for inductive load and modulation circuit using the same - Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state. | 12-09-2010 |
20110128045 | SYSTEM HAVING CORRECTION UNIT AND CORRECTING METHOD THEREOF - A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit. | 06-02-2011 |
20110163783 | NO POP SWITCH - A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold. | 07-07-2011 |
20110199123 | MULTIPLE DETECTION CIRCUIT FOR ACCESSORY JACKS - This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator. | 08-18-2011 |
20110199124 | ELECTRONIC CIRCUIT - An electronic circuit ( | 08-18-2011 |
20110285424 | DIFFERENTIAL COMMUNICATION DEVICE - When a transmission signal is detected as having been changed from a high level to a low level, two transmission lines are connected for only a predetermined time through a diode by a first transistor and a second transistor. The diode is arranged such that its forward direction is from a high-side transmission line to a low-side transmission line. The diode turns on, when a potential of the high-side transmission line becomes higher than that of the low-side transmission line by ringing and a potential difference therebetween exceeds a forward drop voltage of the diode. As a result, a peak wave level of a positive side in the ringing is limited to the forward drop voltage of the diode. | 11-24-2011 |
20120068737 | SYNCHRONOUSLY SAMPLED SINGLE BIT SWITCH MODE POWER SUPPLY - A power supply is described. The power supply includes a synchronous sampled comparator. The synchronous sampled comparator includes a first input that receives a reference voltage. The synchronous sampled comparator also includes a second input that receives a feedback signal. The power supply also includes power field effect transistors (FETs). The power supply further includes an inductor coupled to the power FETs and coupled to the second input. The power FETs generate a power supply voltage using the inductor. The power supply voltage is a direct current (DC) power supply voltage. | 03-22-2012 |
20120119787 | IMAGING DEVICE - An imaging device includes a pixel section and an amplification unit which amplifies the signal of the pixel section. The amplification unit includes an input capacitor having first and second nodes, an amplification circuit, a first feedback capacitor connected between the input capacitor and an output portion of the amplification circuit, a first MOS transistor switch connected in series with the first feedback capacitor, a second MOS transistor switch which is connected in series with the first feedback capacitor, and has a drain and a source connected to each other, a second feedback capacitor connected between the input capacitor and the output portion, a third MOS transistor switch connected in series with the second feedback capacitor, and a fourth MOS transistor switch which is connected in series with the second feedback capacitor, and has a drain and a source connected to each other. | 05-17-2012 |
20120169377 | Circuit Arrangement including a Common Source Sense-FET - A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current. | 07-05-2012 |
20120176160 | SEMICONDUCTOR CIRCUIT, BATTERY CELL MONITORING SYSTEM, COMPUTER READABLE MEDIUM STORING DIAGNOSTIC PROGRAM AND DIAGNOSTIC METHOD - The present invention provides a semiconductor circuit including: a comparator section that compares discharge sections, each including a first signal line connected to a high potential side of each of a plurality of battery cells that are connected in series, a second signal line connected to a low potential side of each of the plurality of battery cells, a resistance element provided between the first signal line and the second signal line, and a discharge switching element connected in series to the resistance element, wherein the comparator section compares a threshold voltage, set according to a potential difference between a potential of the first signal line and a potential of the second signal line, with a voltage according to a potential between the resistance element and the discharge switching element. | 07-12-2012 |
20130082740 | CONFIGURABLE ANALOG FRONT END - An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal. | 04-04-2013 |
20130271183 | METHOD FOR DETERMINING A TRIGGER LEVEL - A method for determining a trigger level for a periodic analog signal in a digital signal processing system is provided. The method reduces output jitter as much as possible and avoids false trigger events. To this end, the method includes measuring the minimum and maximum values of the signal in a predetermined time, defining a plurality of potential trigger values between the minimum and maximum values, assigning to the respective potential trigger value a jitter value characteristic for the jitter created by processing the signal with the potential trigger value, and determining the optimal trigger level based on the lowest jitter value. | 10-17-2013 |
20130342240 | PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH SELECTION CIRCUITRY HAVING HOLD STATE - A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence. | 12-26-2013 |
20140176191 | COMPARATOR CIRCUIT AND SIGNAL COMPARISON METHOD - A comparator circuit includes a first comparator configured to store an offset during a first period, and to compare first and second input signals while compensating for the stored offset to generate a first comparison signal during a second period, a second comparator configured to compare the first and second input signals while compensating for an offset to generate a second comparison signal, and a compensation amount controller configured to control an offset compensation amount of the second comparator when the first and second comparison signals have different values. | 06-26-2014 |
20140266306 | HIGH SPEED DYNAMIC LATCH - Embodiments of the present disclosure may provide a dynamic latch circuit with increased speed and that can perform comparisons on low input signals. The dynamic latch circuit may include a first input transistor receiving a first input signal and a second input transistor receiving a second input signal. A cross coupled inverters may be included to provide a first and second output signals based on the sampled input signals from the first and second input transistors. A reset circuit may be included to reset the first and second outputs to a reference voltage. The latch circuit may include an impedance controller coupled in parallel with the first and second input transistors. | 09-18-2014 |
20140266307 | CIRCUIT AND METHOD TO EXTEND A SIGNAL COMPARISON VOLTAGE RANGE - A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal. | 09-18-2014 |
20140340122 | CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON - An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage. | 11-20-2014 |
20150061729 | Method and Apparatus for Sub-Hysteresis Discrimination - Embodiments of comparator circuits are disclosed. A comparator circuit may include a differential input circuit, an output circuit, a positive feedback circuit operably coupled between the differential input circuit and the output circuit, and a hysteresis control circuit operably coupled with the positive feedback circuit. The hysteresis control circuit includes a switching device and a transistor. The comparator circuit provides sub-hysteresis discrimination and high speed discrimination. | 03-05-2015 |
20150084674 | DETECTION CIRCUIT FOR DETECTING SIGNAL AMPLITUDE - A detection circuit includes a differential circuit including a pair of differential transistors configured to receive the input differential signal and a first current source, the pair of the differential transistors having a common output terminal connected to the first current source, a hold capacitor connected between the common output terminal and a reference potential for generating a hold potential, a level sensing circuit configured to sense a voltage level of the input differential signal and output a switching signal, and a switch configured to receive the switching signal and electrically connect the common output terminal and a second current source when the switching signal exceeds a threshold level being lower than the hold potential by a predetermined amount, and electrically disconnect the common output terminal and the second current source when the switching signal stays lower than the threshold level. | 03-26-2015 |
20150097596 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 04-09-2015 |
20150102840 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 04-16-2015 |
20150311911 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 10-29-2015 |
20180026618 | HIGH-SPEED CONTINUOUS-TIME COMPARATOR CIRCUIT | 01-25-2018 |