Class / Patent application number | Description | Number of patent applications / Date published |
327031000 | By pulse width or spacing | 28 |
20080297201 | Complex switch control system - A complex switch control system including many switches, a switching voltage control circuit and a comparator is provided. The switching voltage control circuit converts an operating voltage into a switching voltage according to the states of the switches. The comparator compares the switching voltage with a reference voltage and outputs a switch state signal to a keyboard controller. A duty cycle of the switch state signal corresponds to the states of the switches. | 12-04-2008 |
20090091353 | METHOD FOR DETECTING LEADING EDGE BLANKING PARAMETER OF POWER MANAGEMENT CHIP - A method for detecting a leading edge blanking parameter of a power management chip includes generating a pulse signal and inputting the pulse signal to the power management chip, wherein the amplitude of the pulse signal will cause a PWM signal of the power management chip to change its duty cycle; detecting the PWM signal to generate a detecting result; when the detecting result indicates that the duty cycle of the PWM signal does not change, adjusting a pulse width of the pulse signal to generate an adjusted pulse signal, inputting the adjusted pulse signal to the power management chip and detecting the PWM signal; and when the detecting result indicates that the duty cycle of the PWM signal changes, determining the leading edge blanking parameter of the power management chip according to the pulse width of the pulse signal. | 04-09-2009 |
20100127733 | DUTY DETECTION CIRCUIT, DUTY CORRECTION CIRCUIT, AND DUTY DETECTION METHOD - Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection. | 05-27-2010 |
20100171529 | SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE - An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval. | 07-08-2010 |
20120218002 | SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE MEASUREMENT - An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval. | 08-30-2012 |
20130076398 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR DETECTING TIMING VIOLATIONS WITHIN A CLOCK - An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals. | 03-28-2013 |
20130082739 | CLOCK DIAGNOSIS CIRCUIT - A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock. | 04-04-2013 |
327033000 | With sampling | 9 |
20090102514 | Duty cycle detecting circuit for pulse width modulation - A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal. | 04-23-2009 |
20090167360 | Apparatus, circuit and method of monitoring performance - An apparatus includes a first sequential circuit which captures an input signal according to a first clock signal, a second sequential circuit which captures the input signal according to a second clock signal and outputs the captured input signal to a logic circuit, the second clock signal being modulated so that a period of the second clock signal is shorter than that of the first clock signal, a third sequential circuit which captures an output signal of the logic circuit according to the second clock signal, and a verification circuit which verifies whether an output signal of the first sequential circuit and an output signal of the third sequential circuit match with each other. | 07-02-2009 |
20120169375 | PROGRAMMABLE PULSE WIDTH DISCRIMINATOR - Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit. | 07-05-2012 |
20130002304 | THRESHOLD TRACKING EDGE DETECTION - Techniques are disclosed relating to tracking edges of a signal of a buffer circuit. In one embodiment, an apparatus is disclosed that includes a sampling circuit configured to sample a pulse width modulation (PWM) signal to generate a threshold voltage based on an average of the high and low voltage levels of the PWM signal and to provide the threshold voltage to an input of a comparator of the apparatus. The comparator is configured receive the threshold voltage and the PWM voltage and perform edge detection on the threshold voltage and PWM signal. | 01-03-2013 |
20130176057 | PROGRAMMABLE PULSE WIDTH DISCRIMINATOR - Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit. | 07-11-2013 |
20130200923 | JITTER MEASURING TRIGGER GENERATOR, JITTER MEASURING APPARATUS USING THE SAME, METHOD OF GENERATING JITTER MEASURING TRIGGER, AND METHOD OF MEASURING JITTER - A phase adjuster | 08-08-2013 |
20150054549 | SAMPLING CIRCUIT FOR CURRETN TRANSFORMER - A sampling circuit for current transformer includes a current sensing unit, a rectification unit, a sampling unit and a switching unit. The rectification unit is electrically connected to the current sensing unit. The sampling unit is electrically connected to the rectification unit and outputs a first signal. The sampling unit includes an energy leakage device and a switching device. The switching device is electrically connected to the energy leakage device in parallel, and is turned on or off according to a second signal and a third signal. The switching unit is electrically connected to the sampling unit, and is turned on or off according to the second signal. | 02-26-2015 |
20160028387 | MEASURING DELAY BETWEEN SIGNAL EDGES OF DIFFERENT SIGNALS USING AN UNDERSAMPLING CLOCK - A system may measure a first sample, of a first signal, using an undersampling signal. The system may measure a second sample, of a second signal, using the undersampling signal. The undersampling signal may have a frequency that is based on a frequency of the first signal or a frequency of the second signal. The system may detect, based on measuring the first sample, a first edge of the first signal. The system may detect, based on measuring the second sample, a second edge of the second signal. The system may determine a delay, associated with the first signal and the second signal, based on detecting the first edge, based on detecting the second edge, based on a first cycle time of the undersampling signal, and based on a second cycle time of the first signal or the second signal. | 01-28-2016 |
20160041212 | Periodic Signal Measurement Using Statistical Sampling - A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle. | 02-11-2016 |
327034000 | Narrow pulse elimination or suppression | 8 |
20090189644 | Short pulse rejection circuit and method thereof - A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation. | 07-30-2009 |
20090219056 | SIGNAL DETECTION CIRCUIT WITH DEGLITCH AND METHOD THEREOF - A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal. | 09-03-2009 |
20110267109 | PULSE WIDTH FILTER - The present invention relates a pulse width filter generating a modulation signal that is increased in synchronization with one of an increasing edge and a decreasing edge of the input signal and is decreased in synchronization with the other of the increasing edge and the decreasing edge, and transmitting the input signal of the modulation signal. The input signal passed through the filter unit is inverted thereby being an output signal. The pulse width filter controls the increasing and the decreasing of the modulation signal according to the output signal and the input signal passed through the filter unit, and the modulation signal is a signal to determined whether the pulse width of the input signal is more than the predetermined cut-off pulse width. | 11-03-2011 |
20120013363 | METHOD AND SYSTEM FOR A GLITCH CORRECTION IN AN ALL DIGITAL PHASE LOCK LOOP - The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches. | 01-19-2012 |
20120169376 | DEGLITCHER WITH PROGRAMMABLE HYSTERESIS - Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher. | 07-05-2012 |
20120229168 | NOISE REDUCTION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED WITH NOISE REDUCTION CIRCUIT - Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit. | 09-13-2012 |
20120249184 | NARROW PULSE FILTER - A narrow pulse filter is disclosed. The narrow pulse filter includes a first tri-state inverter. The narrow pulse filter further includes a pulse generator coupled to the first tri-state inverter. The pulse generator is configured to cause the first tri-state inverter to enter a high-impedance state to filter out a narrow pulse from a signal input to the first tri-state inverter. | 10-04-2012 |
20140055165 | GLITCH FILTER CIRCUIT AND METHOD - A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations. | 02-27-2014 |
327035000 | Separating by duration or gap (e.g., duty cycle, etc.) | 1 |
20110095787 | PWM Limiter Circuit - The duty ratio of a PWM signal is prevented from being zero immediately after the start of PWM control, for example. A PWM limiter circuit has a structure with which a signal output from the PWM limiter circuit can be prevented from being higher than a certain value or lower than a certain value. The PWM limiter circuit includes a comparator circuit, a controller circuit, and a switch circuit. The highest duty ratio reference voltage V | 04-28-2011 |
327036000 | Selection of a particular pulse width | 1 |
20090121747 | Maintaining Circuit Delay Characteristics During Power Management Mode - A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time. | 05-14-2009 |
327037000 | Comparison by threshold or reference | 2 |
20090189645 | FILTER AND FILTERING METHOD - A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal. | 07-30-2009 |
20140002138 | PULSE WIDTH ANTICIPATOR | 01-02-2014 |