Class / Patent application number | Description | Number of patent applications / Date published |
326105000 | Decoding | 19 |
20080315920 | SIGNAL ENCODER AND SIGNAL DECODER - A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal. | 12-25-2008 |
20090212820 | DECODER CIRCUIT, DECODING METHOD, OUTPUT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion. | 08-27-2009 |
20090237114 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 09-24-2009 |
20090295430 | METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS - A methodology for describing an input-output behavior of a multi-level logic gate to process simultaneously a multiplicity of independent Boolean logic functions, with each Boolean function processing signals carried on an individual, separate channel. An embodiment may simultaneously process the same data with the same function or with different functions, multiple data with the same function, or multiple data with different functions. In addition, multi-level logic signals (having more than two levels) may be processed, so that a higher communication bandwidth may be obtained without necessarily increasing the number of traces (wires). Other embodiments are described and claimed. | 12-03-2009 |
20100141301 | LOGIC CIRCUIT, ADDRESS DECODER CIRCUIT AND SEMICONDUCTOR MEMORY - Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential. | 06-10-2010 |
20100231262 | ADDRESS DECODER AND METHOD FOR SETTING AN ADDRESS - An address decoder that sets an address of a module connected to a bus includes a level comparator, an edge detector, and an output decoder. The level comparator compares an SDA signal, which is input to an SDA terminal, with an address selection signal, which is input to an ADDR terminal, and outputs a comparison result. When the two signals match, the comparison is repeated until slave addresses are all received. When the two signals do not match, subsequent comparisons are not performed. The edge detector detects an edge of the address selection signal input to the ADDR terminal. The output decoder sets an address corresponding to the connected destination of the ADDR terminal to determine an address of a slave module connected to the address decoder. | 09-16-2010 |
20100301902 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 12-02-2010 |
20110095785 | SYSTEM AND METHOD FOR DETERMINATION OF A HORIZONTAL MINIMUM OF DIGITAL VALUES - A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location. | 04-28-2011 |
20110221474 | NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY - A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log | 09-15-2011 |
20120169374 | APPARATUS AND METHOD FOR OBTAINING MAXIMUM VALUE AND MINIMUM VALUE IN PLURALITY OF DIGITAL INPUT SIGNALS - The present invention relates to a digital signal processing circuit, and more particularly, to a method and apparatus for generating a maximum value or a minimum value used for designing the digital signal processing circuit. An apparatus for obtaining a maximum value or a minimum value from N digital input signals may include N×W bit processing elements to receive an input of W bits of each of the N digital input signals, W OR operators to receive an input of N operation values output from bit processing elements, and to perform an OR operation, respectively, and W inverters to invert an output value for each of the W OR operators. | 07-05-2012 |
20120235707 | Nor-or decoder - A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit a | 09-20-2012 |
20130027084 | APPARATUS AND METHOD FOR DECODING AN ADDRESS IN TWO STAGES - Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2 | 01-31-2013 |
20130300457 | NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY - A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log | 11-14-2013 |
20130321028 | NOR-OR Decoder - A decoder for decoding an address having a plurality of bits ranging from a first address bit a | 12-05-2013 |
326106000 | With field-effect transistor | 5 |
20080246514 | DECODER CIRCUIT - A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit. | 10-09-2008 |
20090108876 | DECODER CIRCUIT - The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node. | 04-30-2009 |
20110140736 | SYSTEMS AND METHODS FOR BRAIN-LIKE INFORMATION PROCESSING - Logic circuits provide networks to simulate the functions of neural networks of the brain, and can discriminate degrees of state, and combinations of degrees of state, corresponding to a number of neurons. Logic circuits comprise Recursive AND NOT Conjunctions (RANCs), or AND NOT gates. A RANC is a general logic circuit that performs conjunctions for 2 | 06-16-2011 |
326108000 | CMOS | 2 |
20100201401 | DECODER CIRCUIT - The present invention provides a decoder circuit that can prevent the delay of decoder output. Namely, a switch that is put into an ON state when a node A of an NMOS region is not an output channel of a selected gradation voltage, is connected to the node A. Thus, a voltage raised by electric charges being accumulating by a coupling capacity C | 08-12-2010 |
20120092041 | Decoding Circuit Withstanding High Voltage Via Low-Voltage Mos Transistor And The Implementing Method Thereof - A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. | 04-19-2012 |